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Buffer Space Allocation for Real-Time Priority-Aware Networks Hany Kashif and Hiren Patel Electrical and Computer Engineering 1 H. Kashif and H. Patel (RTAS 2016)
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Buffer Space Al location for Real-Time Priori ty-Aware Networks
Hany Kashif and Hiren Patel
Electrical and Computer Engineering
1 H. Kashif and H. Patel (RTAS 2016)
Motivation
• Multiple processing units require predictable communication
• Increasing data communication demands• Design, analyze and implement
novel interconnects for real-time
• Goal: • Introduce buffer constraints in SLA
of PAR NoC
• Buffer allocation
2 H. Kashif and H. Patel (RTAS 2016)
Motivation
• Router model proposed by Shi and Burns [RTSS08]• Communication has distinct priorities• Fixed-priority pre-emption at flit level• Response-time analysis to derive WC bounds (FLA)
• Works for any buffer size
• SLA [TC15] assumption: infinite buffers in VCs
H. Kashif and H. Patel (RTAS 2016)3
Problem Statement
• Extend SLA • Worst-case response times with buffer constraints using
credit feedback policy
• Buffer space allocation• Given finite number of buffers per router, allocate buffers to
VCs
H. Kashif and H. Patel (RTAS 2016)4
UR DR
+IncrementDecrement
Outl ine
• Motivation
• Problem statement
• Model
• Stage-level analysis• Buffer constraints with credit feedback flow control
• Buffer space allocation algorithm
• Experimental evaluation
• Conclusions
H. Kashif and H. Patel (RTAS 2016)5
P1 > P2 > P3
1 2 3𝜏1 𝜏2
𝜏3
Model
• Communication task• Priority• Period• Deadline • Basic link latency
• # flits in a packet
• Release jitter
• Assume • Given mapping of communication tasks onto NoC• Given priorities
H. Kashif and H. Patel (RTAS 2016)
Processing element
with routerStage
6
Stage-level Analysis (SLA)
H. Kashif and H. Patel (RTAS 2016)7
P1 > P2 > P3
1 2 3𝜏1 𝜏2
𝜏3 Task # of flits Period
𝜏1 3 6
𝜏2 2 6
𝜏3 4 Large
𝜏1 𝜏2 𝜏30 1 2 3 4 5 6 7 8 9 10
𝜏1
0 1 2 3 4 5 6 7 8 9 10
𝜏3Stage (1,2)
Stage-level Analysis (SLA)
H. Kashif and H. Patel (RTAS 2016)8
P1 > P2 > P3
1 2 3𝜏1 𝜏2
𝜏3 Task # of flits Period
𝜏1 3 6
𝜏2 2 6
𝜏3 4 Large
𝜏1 𝜏2 𝜏30 1 2 3 4 5 6 7 8 9 10
𝜏1
0 1 2 3 4 5 6 7 8 9 10
𝜏3Stage (1,2)
Critical instant: higher priority
communication tasks released
with task under analysis
Stage-level Analysis (SLA)
H. Kashif and H. Patel (RTAS 2016)9
P1 > P2 > P3
1 2 3𝜏1 𝜏2
𝜏3 Task # of flits Period
𝜏1 3 6
𝜏2 2 6
𝜏3 4 Large
𝜏1 𝜏2 𝜏30 1 2 3 4 5 6 7 8 9 10
𝜏1
0 1 2 3 4 5 6 7 8 9 10
𝜏3Stage (1,2)
R3 on stage (1,2)
Stage-level Analysis (SLA)
H. Kashif and H. Patel (RTAS 2016)10
P1 > P2 > P3
1 2 3𝜏1 𝜏2
𝜏3 Task # of flits Period
𝜏1 3 6
𝜏2 2 6
𝜏3 4 Large
𝜏1 𝜏2 𝜏30 1 2 3 4 5 6 7 8 9 10
𝜏1
𝜏1 introduces interferences
(gaps) in 𝜏3’s transmission
0 1 2 3 4 5 6 7 8 9 10
𝜏3Stage (1,2)
R3 on stage (1,2)
Stage-level Analysis (SLA)
H. Kashif and H. Patel (RTAS 2016)11
P1 > P2 > P3
1 2 3𝜏1 𝜏2
𝜏3 Task # of flits Period
𝜏1 3 6
𝜏2 2 6
𝜏3 4 Large
𝜏1 𝜏2 𝜏30 1 2 3 4 5 6 7 8 9 10
𝜏1
0 1 2 3 4 5 6 7 8 9 10
𝜏3
Stage (1,2)R3 on stage (1,2)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
𝜏2
𝜏3
Stage (2,3)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Stage-level Analysis (SLA)
H. Kashif and H. Patel (RTAS 2016)12
P1 > P2 > P3
1 2 3𝜏1 𝜏2
𝜏3 Task # of flits Period
𝜏1 3 6
𝜏2 2 6
𝜏3 4 Large
𝜏1 𝜏2 𝜏30 1 2 3 4 5 6 7 8 9 10
𝜏1
0 1 2 3 4 5 6 7 8 9 10
𝜏3
Stage (1,2)R3 on stage (1,2)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
𝜏2
𝜏3
Stage (2,3)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
𝜏1 interference added to 𝜏3’s
transmission to next stage
Stage-level Analysis (SLA)
H. Kashif and H. Patel (RTAS 2016)13
P1 > P2 > P3
1 2 3𝜏1 𝜏2
𝜏3 Task # of flits Period
𝜏1 3 6
𝜏2 2 6
𝜏3 4 Large
𝜏1 𝜏2 𝜏30 1 2 3 4 5 6 7 8 9 10
𝜏1
0 1 2 3 4 5 6 7 8 9 10
𝜏3
Stage (1,2)R3 on stage (1,2)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
𝜏2
𝜏3
Stage (2,3)
R3 on stage (2,3)
𝜏1‘s interference (now a part of
𝜏3) is subject to further
interference from 𝜏2
Buffers with Credit Feedback
• Finite buffers require a flow control policy• DR notifies UR that credits must be replenished
• We use credit feedback mechanism• Notification from DR to UR has a credit feedback delay
H. Kashif and H. Patel (RTAS 2016)14
UR DR
+Increment
Decrement
H. Kashif and H. Patel (RTAS 2016)15
SLA with Buffer Constraints & Credit Feedback Delay
Stage (1,2)
𝜏1
𝜏3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Stage (2,3)𝜏2
𝜏3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 1714 18 19 20 21 22 23
24
24
24 25
1 0 0 Buffers2
H. Kashif and H. Patel (RTAS 2016)16
SLA with Buffer Constraints & Credit Feedback Delay
Stage (1,2)
𝜏1
𝜏3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Stage (2,3)𝜏2
𝜏3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 1714 18 19 20 21 22 23
24
24
24 25
1 0 0 Buffers2
Blockage experienced on (1,2) by 𝜏3
H. Kashif and H. Patel (RTAS 2016)17
SLA with Buffer Constraints & Credit Feedback Delay
Stage (1,2)
𝜏1
𝜏3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Stage (2,3)𝜏2
𝜏3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 1714 18 19 20 21 22 23
24
24
24 25
1 0 0 0 Buffers2
Credit available but feedback
delay of 1
H. Kashif and H. Patel (RTAS 2016)18
SLA with Buffer Constraints & Credit Feedback Delay
Stage (1,2)
𝜏1
𝜏3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Stage (2,3)𝜏2
𝜏3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 1714 18 19 20 21 22 23
24
24
24 25
1 0 0 0 1
0
Buffers2
Credit acknowledged and next flit sent
Next credit sent back to stage (1,2)
H. Kashif and H. Patel (RTAS 2016)19
SLA with Buffer Constraints & Credit Feedback Delay
Stage (1,2)
𝜏1
𝜏3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Stage (2,3)𝜏2
𝜏3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 1714 18 19 20 21 22 23
24
24
24 25
1 0 0 0 1
0
0 0 0 0 0 1
0
0Buffers
2 0 0 0 0 1
0
0 0 0 0 0 1
0
0
H. Kashif and H. Patel (RTAS 2016)20
SLA with Buffer Constraints & Credit Feedback Delay
Stage (1,2)
𝜏1
𝜏3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Stage (2,3)𝜏2
𝜏3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 1714 18 19 20 21 22 23
24
24
24 25
1 0 0 0 1
0
0 0 0 0 0 1
0
0Buffers
2 0 0 0 0 1
0
0 0 0 0 0 1
0
0
Observation 1: Since stage (2,3) is the last stage, 𝜏3 does not
experience further backlog as flits are consumed
H. Kashif and H. Patel (RTAS 2016)21
SLA with Buffer Constraints & Credit Feedback Delay
Stage (1,2)
𝜏1
𝜏3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Stage (2,3)𝜏2
𝜏3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 1714 18 19 20 21 22 23
24
24
24 25
1 0 0 0 1
0
0 0 0 0 0 1
0
0Buffers
2 0 0 0 0 1
0
0 0 0 0 0 1
0
0
Observation 2: Amount of new interference on 𝜏3 on stage (2,3)
contributes to blockage on (1,2): 𝑅
𝑇∗ 𝐿 − 𝑉𝐶
H. Kashif and H. Patel (RTAS 2016)22
SLA with Buffer Constraints & Credit Feedback Delay
Stage (1,2)
𝜏1
𝜏3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Stage (2,3)𝜏2
𝜏3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 1714 18 19 20 21 22 23
24
24
24 25
1 0 0 0 1
0
0 0 0 0 0 1
0
0Buffers
2 0 0 0 0 1
0
0 0 0 0 0 1
0
0
Observation 3: Blockage introduces additional interference.
Carry forward this interference.
H. Kashif and H. Patel (RTAS 2016)23
SLA with Buffer Constraints & Credit Feedback Delay
Stage (1,2)
𝜏1
𝜏3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Stage (2,3)𝜏2
𝜏3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 1714 18 19 20 21 22 23
24
24
24 25
1 0 0 0 1
0
0 0 0 0 0 1
0
0Buffers
2 0 0 0 0 1
0
0 0 0 0 0 1
0
0
Observation 4: A particular flit receives its credit CF + 1 units after transmission.
Blockage = MAX( 0, IBS+ +𝑅
𝑇∗ 𝐿 − 𝑉𝐶 + 𝐶𝐹 + 1)
Buffer Space Al location
• Assume a fixed number of buffers per router• Allocate buffers to VCs in each router at start-up
• Objectives of allocation• Make communication tasks schedulable
• Use minimal buffer space
• Key idea• Allocate more buffer space to VC of router on stage that
suffers most interferenceH. Kashif and H. Patel (RTAS 2016)24
Buffer Space Al location
• Initialize VCs to CF + 1 (Assuming CF = 1)
• Compute R3 on (1,2), and (2,3)
H. Kashif and H. Patel (RTAS 2016)25
P1 > P2 > P3
1 2 3𝜏1 𝜏2
𝜏3 Task # of flits Period Deadline
𝜏1 3 6 --
𝜏2 2 6 --
𝜏3 4 Large 23
Stage (1,2)
𝜏30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
R3 =24 on stage (1,2) Stage (2,3)
𝜏3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 1714 18 19 20 21 22 23
24
24 25
R3 =24 on stage (2,3)
Buffer Space Al location
• Compute total R3 over path, R3 = 25
• R3 > 23• Must allocate more space to a router’s VC
• Select router to increment buffer space: (1,2) or (2,3)• Must have available buffer space
• Must contribute most to interference (no blockage)
H. Kashif and H. Patel (RTAS 2016)26
Stage (1,2)
𝜏10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Stage (2,3)𝜏20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Buffer Space Al location
• Increment VC on stage (2,3) to 3
• Re-compute R3 on (1,2) and (2,3)
H. Kashif and H. Patel (RTAS 2016)27
Stage (1,2)𝜏1
𝜏3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Stage (2,3)𝜏2
𝜏3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 1714 18 19 20 21 22 23
24
24
24 25
R3=21 Meets the deadline of 23
Experimental Evaluation
• As more buffer space is available SLA with buffer constraints offers more schedulable configurations
H. Kashif and H. Patel (RTAS 2016)28
Experimental Evaluation
• For schedulable configurations• BSA uses less buffer space than SLA (~85%)
• But, computation time is higher (~4x)
H. Kashif and H. Patel (RTAS 2016)29
Conclusions
• Extended SLA• Buffer constraints and credit feedback delay
• Buffer space allocation• Reduces required buffer space
• Future work• Hardware implementation of a PAR NoC
H. Kashif and H. Patel (RTAS 2016)30
END
•
H. Kashif and H. Patel (RTAS 2016)31
