PowerPoint-Präsentation - - TU Kaiserslautern · [email protected] 21 July 2010 Reiner...

[email protected]

21 July 2010

Reiner Hartenstein, TU Kaiserslautern, Germany

http://hartenstein.de

© 2010, [email protected] http://hartenstein.de

20 a 21 de Julho de 2010

SEMISH - XXXVII Seminário

Integrado de Software e Hardware

Reiner Hartenstein

TU Kaiserslautern

UnB, HiPEAC

The Grand Challenge

to Reinvent Computing – A New World Model

of Computing

Universidade de Brasilia , European Network of Excellence on High Performance and Embedded Architecture and Compilation

http://hartenstein.de © 2010, [email protected]

2

Outline

• We need our computer-based infrastructures

• The electricity bill will become unaffordable

• The history of of massively wrong decisions

• Huge inefficiency by multiple overhead

• Reconfigurable Computing: the silver bullet

• We need to reinvent computing

• Conclusions

1

Reiner Hartenstein: The Grand Challenge To Reinvent Computing - A new World Model of Computing; CSBC_2010, XXX Congresso da Sociedade Brasileira de Computação, July 20-23, 2010, Belo Horizonte, MG, Brasil

mailto:[email protected]














http://hartenstein.de/



































































[email protected]

21 July 2010

Reiner Hartenstein, TU Kaiserslautern, Germany



http://hartenst © 2010, reiner@hartens

ein.de

tein.de

Computers everywhere

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© 2010, [email protected]

4

... Ecosystem: just one example

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http://hartenste/

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http://hartenste/

















[email protected]

21 July 2010 Reiner Hartenstein, TU Kaiserslautern, Germany


© 2010,

[email protected] http://hartenstein.de


... Supercomputers ...

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6

Banking without Computers

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[email protected]




http://hartenstein.de © 2010, [email protected] Business Information Systems

without Computers

7

Lufthansa

Reservation

anno 1960

http://wiki.answers.com/Q/Why_are_computers_important_in_the_world



8

Outline

• We need our computer-based infrastructures






• Conclsions

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[email protected]




http://hartenstein.de © 2010, [email protected] Power Consumption of Computers

[Albert Zomaya]

Power consumption by internet: x30 til 2030 if trends continue G. Fettweis,

9

at Dallas

[Randy Katz: IEEE Spectrum, Febr. 2009]

Energy cost may overtake

IT equipment cost in the near future

„Google causes 2% of the worlds electricity consumption“

(Google denied)

at Quincey

at Boardman


http://hartenstein.de © 2010, [email protected] Google‘s Electricity Bill

(for example)

Google going to sell electricity,

Patent for water-based data centers

Cost of a data center determined by the monthly power bill

„The possibility of computer equipment power consumption spiraling out of control could have serious consequences for the overall affordability of computing” [L. A. Barrosso, Google]

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[email protected]



© 2010, reiner

@hartenstein.de 11 http://ha

rtenstein.de

http://hartenstein.de © 2010, [email protected] Peak Oil

J. S. Gabrielli de Azevedo: Petrobras e o Novo Marco Regulatório; São Paulo, December 1, 2009



Cheap Oil Era reached its End

80% of crude oil is coming from decline fields.

Rapidly growing energy prices (Birol: factor of 3) predicted.

Standards of living: China, India, Brazil, Mexico, newly industrializing countries.

China passes the U.S. in energy use [IEA]

IEA: “>six more Saudi Arabias for the demand predicted for 2030“

growing electricity consumption of computers: 10 more Saudi Arabias!

50% reserves are under water. Off-shore Projects are re-calculated.

A massive future survival problem for our cyber infrastructures.

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http://ha/

http://ha/

http://ha/

http://ha/























































































[email protected]





Oil crises: weekend driving ban (Germany)

13

1973 1979/1980

(depencence on near east oil countries)



14

Outline

• We need our computer-based infrastructure


• The history of massively wrong decisions




• Conclusions

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[email protected]






Punched card input:

several OoM faster

at SOGESTA

VAX-11/750

standard cell placement and routing

ASI on VLSI at Urbino, Italy, 1981

15

©th20e10, [email protected] sequential mind set was httthp:e//hwarteinnstneine.der


Dead Supercomputer Society

[Gordon Bell, keynote, ISCA 2000]

•ACRI •Alliant •American Supercomputer •Ametek •Applied Dynamics •Astronautics •BBN •CDC •Convex •Cray Computer •Cray Research •Culler-Harris •Culler Scientific •Cydrome •Dana/Ardent/ Stellar/Stardent •Key Computer Laboratories

•DAPP •Denelcor •Elexsi •ETA Systems •Evans and Sutherland Computer

•Floating Point Systems •Galaxy YH-1 •Goodyear Aerospace MPP •Gould NPL •Guiltech •ICL •Intel Scientific Computers •International Parallel Machines

•Kendall Square Research

•MasPar •Meiko •Multiflow •Myrias •Numerix •Prisma •Tera •Thinking Machines •Saxpy •Scientific Computer •Systems (SCS) •Soviet Supercomputers •Supertek •Supercomputer Systems •Suprenum •Vitesse Electronics

most in 1985-1995

- mainly research

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[email protected]



Brad Cox 1990: Planning the Software Industrial

Revolution © 2010, [email protected] http://hartenstein.de



Burroughs B5000/5500: language-friendly stack machine

IBM 260/370 & intel x86 highly complex instruction set

MULTICS (GE, Honeywell): well manageable (impl. in PL/1)

UNIX: complexity problems, compatibility problems

Pascal killed by C, coming as an infection, along with UNIX

KARL killed by VHDL, an infection coming along with Ada

unnecessary complexity

inside

widening the semantic gap

[Harold „Bud“ Lawson]

9

© 201

[email protected]

Nathan’s Law: Software is a gas. It expands to fill all its containers ...

Nathan Myhrvold

―software is slowing faster than hardware is accelerating―

“von Neumann overhead piles up to code sizes C.V.Syndrome”: of astronomic dimensions Ramamoorthy

Critique of von Neumann is not new: 17 Peter G.

Neumann

Dijkstra 1968: The Goto considered harmful Peter G. Neumann 1985-2003: 216x “Inside Risks“ R. Hartenstein, G. Koch 1975: The universal Bus considered harmful 18 years inside back

cover of Comm_ACM Backus 1978: Can programming be liberated from the von Neumann style

L. Savain 2006: Arvind et al., 1983: A critique of Multiprocessing the von Neumann Style Why Software is bad


Critique of the von Neumann model

Niklaus Wirth

Wirth‘s

Law ―software is slowing faster

than hardware is accelerating―
































































































































[email protected]





The transition from machine level to higher level languages led to the biggest productivity gain ever made

It„s alarming that today„s megabytes of code are compiled from languages at low abstraction levels (C, C++,Java)

Java is a religion – not a language

[Yale Patt]

It is alarming [Fred Brooks]

19


http://hartenstein.de © 2010, [email protected] Language-of the Year Phenomenon

[R. Newton]

[courtesy Richard Newton]

20

KARL

10


CHDL conference series killed by

VHDL Lobby












































































































































[email protected]




http://hartenstein.de © 2010, [email protected] Too many Languages

21

Dav

id P

arna

s: P

oIiP

E

rnst

Den

ert

Rel

igio

n fo

under

s cr

eati

ng m

onum

ents

of

them

selv

es



11

Languages & text don‘t help

• Rewriting legacy software ….

• programming FPGAs ….

• need to understand its communication

with the hetero architecture

• Languages & textual descriptions don„t help

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[email protected]





New directions in SE

smart phones are examples

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24

Outline







• Conclusions

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[email protected]





25

tthhee ttrreemmeennddoouuss iinneeffffiicciieennccyy ooff ccoommppuutteerrss ccaauusseess iimmmmeennssee eelleeccttrriicciittyy

ccoonnssuummppttiioonn 25

because of The von Neumann

Syndrome



All but ALU is overhead: x20 efficiency

26

[R. Hameed et al.: Understanding Sources of Inefficiency in General-Purpose Chips;

37th ISCA, June 19-23, 2010, St. Malo, France]

explores methods to eliminate overheads by transformations

(data cashe)

Just one of several overhead layers

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[email protected]





27

Multiple Overhead Phenomena



28

Outline







• Conclusions

14

overhead von Neumann machine

instruction fetch instruction stream

state address computation instruction stream

data address computation instruction stream

data meet PU instruction stream

i/o - to / from off-chip RAM instruction stream

multi-threading overhead instruction stream

… many other overhead instruction stream













































































































































[email protected]



© 2010, reiner@ha


Sphttp:e//harteensteidn.de -up © 2010, [email protected]

29

FFT

pattern matching 100

wireless Reed-Solomon

Decoding 2400

Viterbi Decoding 400

730 900 1000

MAC crypto CT imaging 1000

Multimedia DSP and

molecular 88 dynamics

simulation

52 BLAST

protein

identification 40

288 Smith-Waterman

Bioinformatics A20 strophysics GRAPE

SPIHT wavelet-based image compression 457

real-time face detection

6000

video-rate st

pattern recognition

ereo vision

Image processing, Pattern matching,

3000

28500

DES breaking

8723

100

10 3

106

Spe

edup

-Fac

tor

factors

obtained

by Software

to Configware migration

Abundant on-chip bandwidth available for parallelism of flexible granularity.

A physical signal is the simplest and fastest way of message & data transport.

DNA seq.

© 2010, reiner@h

http://hartenstein.de 30

A20 strophysics GRAPE 100

Spe

edup

-Fac

tor


© 2009, reiner@hartenstein. de

artenstein.de

http://hartenstein. de

Po© 2010, [email protected]

Energy saving factors: ~10% of speedup

FFT 100

molecular

Reed-Solomon Decoding 2400 seq.

Viterbi Decoding 400

730 900 1000

video-rate MAC

Multimedia DSP and wireless

88 dynamics simulation

52 BLAST

protein

identification 40

Smith-Waterman pattern matching

457

SPIHT wavelet-based288

Bioinformatics

crypto 1000

28500 DES breaking

103

106

wer save

factors obtained (FPGAs)

image compression

real-time face detection

6000

stereo vision pattern

recognition

Image processing, Pattern matching,

3000 CT imaging

8723 DNA

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http://harten/

http://harten/

http://harten/

http://harten/

http://harten/

http://harten/

http://harten/

















[email protected]



*) RC = Reconfigurable Computing © 2010, [email protected] http://hartenstein.de


31

Tarek El-Ghazawi

[Tarek El-Ghazawi et al.: IEEE COMPUTER, Febr. 2008] SGI Altix 4700 with RC 100 RASC compared to Beowulf cluster

Application DNA and Protein sequencing

DES breaking

Speed-up factor

8723

28514

Savings Power Cost Size

779 22 253

3439 96 1116 much less equipment

needed much less memory and bandwidth needed massively

saving energy

RC*: Demonstrating the intensive Impact


a single rack without air conditioning


16


Drastically less Equipment needed

For instance: a hangar full of racks replaced by













































































































































[email protected]





Google going Reconfigurable

(MapReduce etc.) (Barton Sano)

[Randy Katz: IEEE Spectrum, Febr. 2009]

at Dallas

each 6500 m2

Will Google be the largest customer of the FPGA industry ?



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The silver bullet

Reconfigurable Computing is really the silver bullet for massively saving energy

We need a good migration strategy

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[email protected]





35

Outline



• The history of massively wrong decisions




• Conclusions



18

New

Programmer

Education

36

New mix of skills needed, currently not available

focusing on memory mapping issues and transfer modes to detect overhead and bottlenecks

essential: awareness of locality,

understanding streams through complex fabrics













































































































































[email protected]




http://hartenstein.de © 2010, [email protected] Two classes of solutions

37

Migration of a particular algorithm to RC

Understanding a complex modern hetero system

to detect overhead and bottlenecks


off-chip memory, streams


http://hartenstein.de © 2010, [email protected] understanding architecture

38

NoC

memory ASIC

ASIP FPGA

µP I/O

the

mem

ory

wal

l

several transfer modes

reconfigurable accelerators

19

ired rators

many-core

memory

memory

ASIC hardw accele

ASIC

ASIP

ASIP

FPGA

FPGA

µP

µP

I/O

I/O













































































































































[email protected]






http://hartenstein.de © 2010, [email protected] Dave Patterson‘s Law

39

I/O

I/O

I/O

Patterson the memory wall



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New Book on NoC

Jih-Sheng Shen, Pao-Ann Hsiung (editors): Dynamic Reconfigurable Network-on-Chip

Designs: Innovations for Computational Processing and Communication; Information

Science Publishers, April 2010

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[email protected]





On Bottlenecks

R. Hartenstein, G. Koch: The Universal Bus

considered harmful; Symposium on the

Microarchitecture of Computing Systems; June 1975, Nice, France [North Holland/American Elsevier].

41

not visible from SE © 2010, [email protected]

world model

is obsolete http://hartenstein.de


CPU-centric flat world model

(Aristotelian model)

This Software-centric

(introduced

in the 40ies)

CCPPUU-“-“cceennttrriicc““ bbuutt nnoo hardware know-

how (kind of tunnel view)

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CPU













































































































































[email protected]



The Generalization of Software Engineering — © 2010, [email protected] http://hartenstein.de


A Heliocentric CS Model needed

auto-sequencing Memory

Triple Paradigm Dual Dichotomy Approach.

43

PE

Program Engineering

*) do not confuse with „dataflow“!

Flowware Engineering

FE

asM time to space

mapping issue

Configware Engineering

structures

SE

Software Engineering

CPU


http://hartenstein.de © 2010, [email protected] Two classes of solutions

44

Migration of a particular algorithm to RC

Understanding a complex modern hetero system

to detect overhead and bottlenecks

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[email protected]




http://hartenstein.de © 2010, [email protected] Bubble Sort

Example

loop i = 2 .. N

loop j = 2 .. N

if key [j-1] > key [j] then swap (key [j-1], key [j])

endif;

endloop j;

endloop i;

45

conditional swap

x

y

complexity: O(n2)



© 2010, [email protected] time to space mapping

time domain:

procedure domain time algorithm

program loop n time steps, 1 CPU

space domain:

structure domain space algorithm

pipeline 1 time step, n DPUs

46

Bubble Sort n x k time steps,

1 „conditional swap“ unit

time algorithm

Shuffle Sort k time steps, n „conditional swap“ units

space/time algorithm

conditional swap

x

y

conditional swap

conditional swap

conditional swap

conditional swap

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[email protected]





Architecture instead of synchro

47

conditional swap

conditional swap

conditional swap

conditional swap

conditional swap

conditional swap

conditional swap

conditional swap

direct time to space mapping

accessing conflicts modification: with

shuffle-function

„Shuffle Sort“

conditional swap

conditional swap

conditional swap

conditional swap

Better Architecture instead of complex synchronisation: half he number of Blocks + up und down of data (shuffle function) – no von Neumann- syndrome !



48

Outline







• Conclusions

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[email protected]





49

Conclusions (1) RC is the

silver bullet

To avoid future unaffordability of our cyber infrastructure

we need a massive software to configware migration

The migration of the huge supply of legacy software creates masses of jobs for decades ….

…. and saves much more energy than most proposals from the climate protection scene

… impossible without reinventing programmer education



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50

Conclusions (2)

We must hurry up to start the required time-consuming

massive campaign as long as we still can afford it

We have to hurry up to activate the public and the

media, currently fully ignoring this wordwide vital issue

We need a huge campaign at least comparable to the Mead-&-Conway Revolution













































































































































[email protected]





51

Obrigado! http://hartenstein.de [email protected]



26

52

thank you for your patience





























































































































































[email protected]





53

END



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54

Computing must to be re-invented because of two main problem areas, both being related to power efficiency.

•The transition to multicore architectures. •Financial limits are reached within about a decade by rising energy cost and rapidly growing power consumption of the entirety of computers worldwide

Without a timely effective solution we‟ll run into a severe economic crisis.

A key issue is the tremendous inefficiency of what we call „software“, i. (instruction-streams). Improvements by orders of magnitude are obtained by massive software to configware migrations. Data-stream-driven reconfigurable architectures are useful to reinvent computing. The talk discusses how to implement a rescue campaign.

(Abstract)













































































































































[email protected]




http://hartenstein.de © 2010, [email protected] Double Dichotomy

1) Paradigm Dichotomy

von Neumann Machine Datastream Machine instruction stream data stream

(Software-Domain) (Flowware-Domain)

2) Relativity Dichotomy

time: space: -Procedure -Structure

(Software-Domain) (Configware-Domain)

55



28

Acceleration Mechanisms

•parallelism by multi bank memory architecture •auxiliary hardware for address calculation •address calculation before run time

•avoiding multiple accesses to the same data. •avoiding memory cycles for address computation •optimization by storage scheme transformations •optimization by memory architecture transformations













































































































































[email protected]






57

10 12 14 16 18 20 22 24 26 28 30 year

relative performance

94 96 98 00 02 0

4

06 08

be

gin

of t

he

m

ultic

ore

e

ra

Multimedia in the Multicore Era

Multimedia Performance Ne

application perform

needs u Audio 800 Graphics 11 Video 160 Digital TV 900

[Pierre Paulin, MPSoC’09]

snc

to MIPS GOPS

GOPS

GOPS

needed performance

growing faster than Moore‘s law

GSM GPRS EDGE UMTSstandard next



58

Dual paradigm mind set: an old hat (mapping from procedural to structural domain)

Mapped into a Hardware mind set: action box = Flipflop, decision box = (de)multiplexer

Software mind set:

flow chart -> control instructions

W. A. Clark: Macromodular Computer Systems; 1967 SJCC, AFIPS Conf. Proc.

C. G. Bell et al: The Description and Use of Register-Transfer Modules (RTM's); IEEE Trans-C21/5, May 1972

1967:

1972:

FF

token bit

FF FF

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[email protected]




we need RC



© 2010, reiner@hart Wenstein.dee need R-CS: Reconfigurable

Computer Science

Reconfigurable Computing (RC)

Configware skills are essential qualifications at the CS job market.

59

has become mainstream in Embedded Systems already many years ago.

Embedded Computer Science (E-CS): we need people who combine understanding of software and hardware/configware

Configware skills need some hardware knowledge.

Configware is modern hardware replacement.

R-CS means modern E-CS.



30

ANN 60





























































































































[email protected]







understanding architecture

61

NoC

memory ASIC

ASIP FPGA

µP I/O

the

mem

ory

wal

l

several transfer modes

reconfigurable accelerators

ired rators

self-reconfigurable accelerators

many-core



62

[Olivier Temam: The Rebirth of Neural Networks; 37th ISCA, June 19-23, 2010, Saint-Malo, France]

31

memory

memory

ASIC hardw accele

ASIC

ASIP

ASIP

FPGA

FPGA

µP

µP

I/O

I/O

ANN

ANN













































































































































[email protected]





63



http://hartenstein.de © 2010, [email protected] Stopped Funding for 15 Years

64


Marvin Minsky,

Seymour Papert:

Perceptrons; 1969.

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[email protected]





Marvyn Minski‘s blind alarm

65

Lernmatrix 1960

20

ye

ars

ea

rlie

r !

W. Hilberg: Karl Steinbuch, ein zu Unrecht vergessener Pionier der Künstlichen Neuronalen Systeme; FREQUENZ 1995, 49#(1-2):28-35.



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33













































































































































[email protected]



[Olivier Temam: The Rebirth

of Neural Networks; 37th

ISCA, June 19-23, 2010, Saint-Malo, France]




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68

threshold logic:

Neuron Model

x1 + x2 + x3 ≥ 1

x1 + x2 + x3 ≥ 3

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[email protected]




resistor with memory © 2010, [email protected]

http://hartenstein.de 69

Memristor

Postulated: KIT 1960

Widrow‟s Memistor 1963-65

“predicted” by UCB 1971

technology detected at hp 2008

TiO2 semicondictor: hi resitance

conductive by doping

resistance manipulated by moving the doping via electrical field

logic function depends on resistor dimensioning © 2010, [email protected]


Memristor LUT http://hartenstein.de 70

FPNA

Field-Programmable Neuron Array

35













































































































































[email protected]





71

Teachable Neuron

generalization of the LUT

from Boolean algebra

to Steinbuch algebra

from Reconfigurable Computing

to Reconfigurable Neuro Computing



36

72

Abstract. Computing has to be re-invented because of two main problem areas, both being related to power efficiency. Technical limits of power dissipation per processor chip caused the transition to multicore architectures. Financial limits will be reached within about a decade or slightly more by rising energy prices and rapid growth of the electricity consumption of the entirety of all kinds of computers everywhere worldwide. If we do not find a timely effective solution we will run into a severe economic crisis.

A key issue is the tremendous inefficiency of what we call „software“, i. e. running on instruction-stream-driven architectures. Improvements by orders of magnitude can be obtained by migration to data streams in the context of massive software to configware migrations. Data-stream- driven reconfigurable architectures are useful by providing the basis to reinvent computing for avoiding the future unaffordability of its electricity bill. The talk discusses how to implement a rescue campaign.

(Abstract)













































































































































[email protected]





73

Computing must to be re-invented because of two main problem areas, both being related to power efficiency.

•The transition to multicore architectures.

•Financial limits are reached within about a decade by rising energy cost and rapidly growing power consumption of the entirety of computers worldwide

Without a timely effective solution we‟ll run into a severe economic crisis.

A key issue is the tremendous inefficiency of what we call „software“, i. (instruction-streams). Improvements by orders of magnitude are obtained by massive software to configware migrations. Data-stream-driven reconfigurable architectures are useful to reinvent computing. The talk discusses how to implement a rescue campaign.

(Abstract)



74

Why computers are important

37













































































































































[email protected]




http://hartenstein.de © 2010, [email protected] Graphic Representation

We need a modeling level less abstract than by textual languages

A graphic representation should transparently illustrate to its

user, how data streams are running through the structures.

to the Domain scientist this is much more informative, than

abstract text-only notations like languages, which do not

provide physical locality awareness. Ease of understanding

should be the main objective.

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http://hartenstein.de © 2010, [email protected] FPGA to ASIC design start ratio

76

ASIC 3%

97% FPGA [Dataquest March 25, 2009]

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[email protected]



http://hartenstein.de [email protected] We need „une' Levée en Masses“ © 2010,


77

We need „une'

Levée en MMaasssseess“

77



Professor (ordinarius emeritus), TU Kaiserslautern Karl Steinbuch

All academic degrees from EE department

at Karlsruhe Institute of Technology (KIT)

1981: visiting professor at UC Berkeley

IEEE fellow, SDPS fellow, FPL fellow, other awards

Founder and co-founder of several international annual conference series

Reiner‘s CV (1)

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[email protected]





Viktor Prasanna called him „The father of Reconfigurable Computing“ (also pre-FPGA era) -- („Gerald Estrin: grandfather of RC“)

1983: founder of German Mead-&-Conway VLSI design scene: the multi university „E.I.S. project“ (grant: 38 million DM)

Author & compiler writer of KARL[1]: in the 80ies

the most successful HDL and trailblazer before VHDL

[1] R. Hartenstein: Fundamentals of Structured Hardware Design, 1977, North Holland / American Elsevier -- bestseller

Reiner‘s CV (2)

79



Complete EDA framework[2] around KARL and ABL: 85 mio ECU grant by ESPRIT programme of the EU

Reiner‘s CV (3)

format-checking functional floorplan graphic editor

[2] R. Hartenstein: The History of KARL and ABL; in: J. Mermet (editor): Fundamentals and Standards in Hardware Description Languages; 1993.

also see: http://xputers.informatik.uni-kl.de/karl/karl_history_fbi.html

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calculus-based

term rewriting floorplan generator,

automatic test generation,

testability analysis,

embedded router,

structured logic synthesis,

simulator …

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http://xputers.informatik.uni-kl.de/karl/karl_history_fbi.html










































[email protected]





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Speed-up by MoM-1 compared to

PISA project

41

6802

0



















































































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