Power_Planning_Signal_Route_Closure.pdf

2014 Synopsys, Inc. All rights reserved. 1

CAE Best Practices for

Power Planning at Advanced Nodes

Enabling Signal Routing Closure

Router CAE Team

September 2013


CONFIDENTIAL INFORMATION

The following material is confidential information of Synopsys and is being

disclosed to you pursuant to a non-disclosure agreement between you or your

employer and Synopsys. The material being disclosed may only be used as

permitted under such non-disclosure agreement.

IMPORTANT NOTICE

In the event information in this presentation reflects Synopsys future plans,

such plans are as of the date of this presentation and are subject to

change. Synopsys is not obligated to develop the software with the features

and functionality discussed in these materials. In any event, Synopsys

products may be offered and purchased only pursuant to an authorized quote

and purchase order or a mutually agreed upon written contract.


Objectives

Understand the challenges introduced by advanced rules

associated with the power mesh

Learn design guidelines and best practices

Improve signal routing closure and design predictability

Designing a power plan at emerging nodes


Agenda

Power Mesh Structure

Challenges and guidelines

Effects of various power mesh structures

Pin Access

set_pnet_options

Obstructions from the power meshs via array

Design Rule Closure

Global routing and detail routing predictability

Double patterning technology

Fat spacing

Wide metal jogs

Forbidden spacing

Customized contact codes



Process (nm) Width (um) Space (um) minWidth (um)

130~250 10~20 < 500 0.16

65~90 5~10 < 100 0.10

28~40 < 2 20~30 0.05

14~20 < 0.5 ~5 0.032

Trend from established to advanced nodes

Larger width and interval Smaller width and interval



Pin access blocked

More routing resources and tracks consumed

Detours at a later signal routing stage predictability

issue

Challenges to signal routing closure

Detours and jogs

around PG vias

Pin access points

not utilized

T0

T1

T2

T3

T4

W_fat

S_fat

Blocked signal

wire tracks



Minimize PG mesh on double-patterning layers

Spare M3 and M4 space for signal routes

Avoid high via walls

Avoid clusters of via arrays

Adjust PG wires to improve signal routability

Minimize the number of tracks occupied by PG wires

Increase PG wire width (smaller widths can trigger additional DRC rules, especially at advanced process nodes)

Use preferred routing direction only

Consider impact during PG rail implementation

Dual PG rails; both M1 and M2

Might need wider M2 rail to improve electromigration and voltage drop

Guidelines for advanced process nodes



Stacked via arrays create high walls

Leads to high wire density and detours around via walls

Avoid high via walls

M8

M1

M2

M3

M4

M5

M6

M7

M8

M1

M2

M3

M4

M5

M6

M7

M8

M1

M2

M3

M4

M5

M6

M7

Two-tier mesh Multi-tier mesh



Clustered via arrays lead to detours and jogs

Avoid clusters of via arrays

P

P

G

G

P

G

Pitch

M8 detours M7 detours

P G

Pair distributed

M3 detours

Cluster of PG via

arrays can impact

the routability on

double-patterning

layers



Fewer detours

Good utilization of routing tracks

Improvement by avoiding clusters of via arrays

M8 M7

P

P

G

P

G P

Sy

Sx

Evenly distributed

M3



Pros and Cons

Paired PG provides more routing

tracks but creates clustered via

arrays that impact routing

closure on double-patterning

(DPT) layers

Evenly distributed PG provides a

better routing pattern in the

preferred direction but has fewer

routing tracks for signals

Paired versus evenly distributed PG meshes

In every 4x4um

window

Paired PG

(# tracks)

Even PG

(# tracks)

M5: (Vertical straps

on non-DPT layers) 44 41

M3: (Via arrays on

DPT layers)

51 (Clustered

via arrays) 53

See further analysis on the next page


Paired Versus Even PG Mesh

Paired: M3

Even: M3

Recommendations (2-tier mesh)

Build a paired PG mesh on upper layers

and do not connect all the way to rails

Build an evenly distributed PG mesh on

lower layers and connect through rails

Detours to DPT layers invoke additional routing rules

Layer M1 : 192 micron







Utilize Routing Tracks Efficiently

Shift PG wires for the fewest number of blocked tracks

Shift PG wires

4 tracks blocked Now only 3 tracks blocked

W W


Utilize Routing Tracks Efficiently

Expand PG wire width without impacting adjacent tracks

For electromigration and voltage-drop improvement

At emerging nodes, a wider strap might have fewer design rules

Widen PG wires

T0

T1

T2

T3

T4

W1

T0

T1

T2

T3

T4

W1 W2


PG Rail Implementation

Dual PG rail both M1 and M2 rail

Might require a wider M2 rail for electromigration and voltage-drop

improvement

Use a wider width to utilize adjacent tracks

Improve reliability

W2 M1 Rail

T0

T1

T2

T3

T4

M2 Rail W1


Summary for Power Mesh Structure

Use PG straps in pairs at higher (non-double-patterning)

layers

Prevent clusters of via arrays on double-patterning layers

Always utilize routing tracks from PG wires efficiently


Agenda




Pin Access

set_pnet_options

Obstructions from power meshs via array

Design Rule Closure

Global routing and detail routing predictability


Fat spacing

Wide metal jogs

Forbidden spacing



Pin Access

Some designs use very thin M3 straps for the secondary

power mesh

Need set_pnet_options to allow standard cells under

the M3 mesh and still expose sufficient space for pin access

Expose more room by using set_pnet_options

M3 strap

M2 pin

M3 strap

M2 pin

Legalize

placement


Pin Access Versus VIA2 PG Array

Cause:

A bigger M3 enclosure for the power mesh via array on VIA2

blocks the M3 access to M1 and M2 pins

Fewer pin access points

Recommendation: Use a thinner PG array

M3 enclosure obstructs the signal wires incoming

M1 Rail

a b

c

VIA2 PG array

M1 pin M3 wire

M1 Rail

a b

c

M1 pin M3 wire

Use a thinner array


M1 Rail

Pin Access Versus PG Cut Spacing PG cut types affect a pins via landing

M1 Rail

M1 pin M2 wire

X X

M1 pin M2 wire

This pin has only one access point;

the other two points are blocked due

to the larger minimum spacing

between a square cut and a

rectangle cut

VIA1 VIA1

This pin has three access points; two

additional points are gained due to the

smaller minimum spacing between

two square cuts


Pin Access Versus VIA2 PG Array

In this standard cell, four M1 access points (a, b, c and d)

are NOT available due to M3 obstruction from the PG array

on VIA2

This issue is caused by the end-of-line spacing requirement

Real example M3 vacancy leads to limited pin access

a b

d

c

VIA2 PG array

VIA2 Array

VIA2 PG array


Pin Accessibility While Cell Shrinks

Fewer horizontal M2 tracks available for pin access

Vertical M3 tracks limited by the end-of-line spacing rule

Staggered via arrays increase local congestion on

M2 and M3

More problems occur on double-patterning layers

12-track 9-track

Clustered PG

via arrays

M3 end-of-line and via

spacing rules take effect


Summary for Pin Access

Avoid M3 PG straps

Can use set_pnet_options to better expose pins

Avoid clustering of via arrays on double-patterning

(lower) layers

Choose proper cut type for smaller spacing requirements


Agenda




Pin Access

set_pnet_options

Obstructions from power meshs via array

Design Rule Closure

Correlation between global routing and detail routing


Fat spacing

Wide metal jogs

Forbidden spacing



Challenges to Design Closure

Predictability from global routing to

detail routing

Detours

Timing fluctuation

Long buffer chain

DRC convergence

Rapidly growing advanced design rules

Violations along

PG via arrays

Advanced design

rule violation

DRC over fixed that tracks

were not properly utilized

1 2 3

Net detouring occurs only

during detail routing


Detour net only seen until

DR stage

Global Routing to Detail Routing Closure

Lessons learned:

- Global router did not see additional spacing requirement around

PG via arrays

- No congestion seen during global routing but many DRC

violations left after detail routing

- Detours occurred during detail routing when the nets were

rerouted to fix DRC violations

Global Router Did Not Consider End-of-Line Spacing

Numerous violations

along PG VIA arrays End-of-line spacing

violation


Global Routing to Detail Routing Closure

Workaround steps:

- Increase size of PG via arrays, and then run global routing

- The global router makes more accurate congestion estimation by

seeing the additional tracks required from the larger via array

- Change PG via arrays back to original size, and then run detail

routing

- The detail router has more room to meet the end-of-line spacing

rule introduced by the original thin via array

Solution:

- Global router enhanced in 2011 to estimate the cost of the end-of-

line rule

Workaround for End-of-Line Spacing Issue


Global Router Predictability Enhancement

fatTbl*ExcludedSpacingRange defines regions where

spacing checks are ignored

Honors exclude range of fat metal spacing rule

fatTblPrefWidthThreshold = (W1, W2, W3,.)

fatTblPrefToPrefXMinSpacing = (0.042,0.042, 0.042,

0.042,0.080, 0.080,

)

fatTblPrefYExcludedSpacingRange = ("0.044, 0.070", "0.044, 0.070",

)

Spacing checks

ignored

W

spacing

In I-2013.12-SP3, the global router honors these regions

and provides accurate congestion estimation


Design Rule Closure Double-patterning spacing rule

VDD1 VDD2

VDD1 VDD2

VSS

VDD1 and VDD2 rails on M1 are

separated by mininum spacing

No double-patterning violations

because routes in preferred routing

direction

After placing standard cells, M1

odd cycle is formed by the metal

shapes inside cells and PG rails

5 1

2

3 4

Cause:

Solution: Increase spacing between M1 rails for different

supply voltages


Design Rule Closure

Cause: Smaller wire width can trigger more design rules

Fat metal spacing rule

T0

T1

T2

T3

T4

W=0.09

S=0.082

fatTblPrefYExcludedSpacingRange = (-1, -1, -1, .

-1, "0.044, 0.070", "0.044, 0.070",

-1, "0.044, 0.070", "0.044, 0.070",

-1, "0.044, 0.070", "0.044, 0.070",

fatTblPrefWidthThreshold = (0.068,0.086,0.136,..)

fatTblPrefYParallelLengthDimension = 3

fatTblPrefYParallelLengthThreshold = (0,0.150,0.200,)

fatTblPrefToPrefXMinSpacing = (0.034,0.034,0.034,

0.034,0.082,0.082,

0.034,0.110,0.110,

Exclude spacing check

in these regions


Design Rule Closure

Solution: Widen wire to make the next track available for

signal routing

Fat metal spacing rule - Improvement

T0

T1

T2

T3

T4

W=0.09

S=0.082

T0

T1

T2

T3

T4

W=0.14

S=0.110

fatTblPrefYExcludedSpacingRange = (-1, -1, -1, .

-1, "0.044, 0.070", "0.044, 0.070",

-1, "0.044, 0.070", "0.044, 0.070",

-1, "0.044, 0.070", "0.044, 0.070",

fatTblPrefWidthThreshold = (0.068,0.086,0.136,..)

fatTblPrefYParallelLengthDimension = 3

fatTblPrefYParallelLengthThreshold = (0,0.150,0.200,)

fatTblPrefToPrefXMinSpacing = (0.034,0.034,0.034,

0.034,0.082,0.082,

0.034,0.110,0.110,


Design Rule Closure

Cause: Redundant via insertion

Wide metal jog spacing rule

fatMetalJogTblSize =

fatMetalJogThresholdTbl = (0.275,0.490,0.700,)

fatMetalJogLengthTblSize = 2

fatMetalJogLengthTbl = (0,0.22)

fatMetalJogMinSpacingTbl = (0.07,0.15,

0.07,0.18,

P G P G

P

G A

B

OK

Failed

Wide metal

jog violation


Design Rule Closure

Solution: Space the PG pair further apart to avoid wide

metal jog rule violations

Wide metal jog spacing rule - Improvement

A

OK


A

C

B

Design Rule Closure

Forbidden spacing violation blocks 2 to 3 routing tracks

Occurs when a metal shape is off-track or wider

Can cause detours after rerouting

Forbidden spacing rule How does it happen?

T0

T1

T2

Ideal case: all wires on track

T3

A

C

B

T0

T1

T2

DRC violation occurs when off track

T3


Design Rule Closure

Generally occurs around PG via arrays

Forbidden spacing rule Where does it happen?

Wide PG via array Off-track PG via array

P

P

G

P

G P

Sy

Sx

PG mesh Forbidden spacing violations


Design Rule Closure

Three Solutions:

1. Move a thin via array on track

Forbidden spacing rule - Improvement

A

C

B

T0

T1

T2

T3

2. Shift the edge of a wide via array outside the forbidden region

A

C

B

T0

T1

T2

T3

minWidth


Design Rule Closure

3. Pick a wider via array that can be waived from the

forbidden*MaxWidth* rule

Forbidden spacing rule Improvement (Continued)

forbiddenSpaceWireMaxWidthThreshold = Wmax

forbiddenSpaceWireMaxSpacingThreshold = .

forbiddenSpaceWireParallelLength =

forbiddenSpaceRangeTblSize =

forbiddenSpaceRangeTbl =

forbiddenSpacePrefForbiddenWireMaxWidthTbl = (Wmax1, Wmax2)

forbiddenSpacePrefTblSize = .

forbiddenSpacePrefWireWidthTbl =

forbiddenSpacePrefWireSpacingTbl =

forbiddenSpacePrefRangeTbl =

C

T2

T3

C

T2

T3

> Wmax


Design Rule Closure

Add new contact codes with specific dimensions for PG routing, but

exclude them for signal routing

Customize contact codes

ContactCode "V1_PG_Only" {

contactCodeNumber = 220

cutLayer = "via1"

excludedForSignalRoute = 1

upperLayerEncWidth =

upperLayerEncHeight =

.

minCutSpacing = }

ContactCode "V1_Signal_Only" {


cutLayer = "via1"

excludedForPGRoute = 1

}

Exclude contact codes for PG routing to prevent DRC violations


Design Rule Closure Customize contact codes - Example

To avoid forbidden spacing rule violations,

Ensure both ends of the via array have exactly half-width

extension from the routing track

Via array dimension R = NxPitch+minWidth for both

vertical and horizontal directions

Forbidden spacing violations

Forbidden spacing violations

ContactCode "V2_PG_Only" {


cutLayer = "via2"

excludedForSignalRoute = 1

upperLayerEncWidth =

upperLayerEncHeight =

lowerLayerEncWidth =

lowerLayerEncHeight =

minCutSpacing =

}

1 2


Summary

Design rules at emerging nodes bring new challenges to PG planning and design closure

Use PG mesh to provide pin access and routing tracks for signals

Minimize the PG shapes on double-patterning technology layers


Thank You

Power_Planning_Signal_Route_Closure.pdf

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