Powering tests

Powering tests

Laura Gonella Physikalisches Institut Uni Bonn

Meaurements

• For different powering configuration, measure

For now done on bare chips. Current PCB does not have circuitry for sensor HV.

Wire bond from VDDA pad to measurement point. Same for VDDD.

VDDA2M is not connected on the PCB. It was removed to make space for regulator testing circuitry.

4386

18/05/20112 L. Gonella - Powering tests

Powering configurations


Setup

• Power is provided via power supply• USBpix is used only to send/receive signals to/from the chip

– Stcontrol– Standard configuration file

• Top row not powered

• Switching on sequence– Power up chip. Both VDDA and VDDD applied at the same time– Start the clock via STcontrol– Configure– Run scans


Direct powering configuration 1



• Rwire = 0.2Ohm round trip


1.5V

1.2V

Rwire RpcbRwb

Rpcb

Rwb

Rwire

Voltages and currents

V @ supply (V) V @ chip (V) I (mA)

Power up A 1.5 1.502 13

D 1.2 1.199 3

Clock on A 1.5 1.502 13

D 1.2 1.174 96

Std cfg A 1.5 1.458 268

D 1.2 (1.22) 1.172(1.191) 106(109)

PrmpVbp*2 A 1.5 1.442 369

D 1.22 1.191 109


Digital and analog scans• Digital scan: The digital

scan is fine when powering from USBPix.

• Analog scan


Threshold scan


Threshold scan – PrmpVbp*2



• VDDD and VDDA shorted at supply• Rwire = 0.2Ohm round trip

Rwire

RpcbRwb

Rpcb

Rwb

Rwire

1.5V


Voltages and currents

V @ supply (V) V @ chip (V) I (mA)

Power up A 1.5 1.502 19

D 1.502

Clock on A 1.5 1.497 129

D 1.476

Std cfg A 1.5 1.460 483

D 1.442

PrmpVbp*2 A 1.5 1.450 511

D 1.455


Digital and analog scan

• Digital scan • Analog scan


Threshold scan


Threshold scan – PrmpVbp*2


Discussion with Mauro• Mauro could provide within one week from now

– Board with LV PP2 regulator– Controller– Easy Labview interface– Type 2 cables

• As we are interested in transients we would need some more realistic cables– Mauro said this might take an extra week to have

• On top add time to get things to work in Bonn (max 1 week?)• Mauro offered to come to Bonn and help at the beginning of

June• Option 1 (type 2 cables): tests could start in 2 weeks form

now (2nd of June)• Option 2 (more realistic cables): tests could start in 3 weeks

from now (9th of June)• These are anyway far from being definitive dates• I agreed with Mauro that I will call him after this meeting to

tell him what we decided18/05/201119 L. Gonella - Powering tests

Future tests

• I am willing to finish the tests of the powering configurations with what I have right now and do them again with what Mauro sends– Provided what I am doing now is interesting and we can wait to

get stuff from Mauro• After that I will go on with tests on the Shunt-LDO regulator

with main focus on the full shunt-LDO mode for serial powering

• Tests of different powering configurations with modules will follow as well

• I will be providing support to people working on developing the powering scheme for the IBL with the Shunt-LDO


Powering tests

Documents

Transcript of Powering tests