PowerDRC/LVS 2.0 Overview
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Transcript of PowerDRC/LVS 2.0 Overview
July 2014
PowerDRC/LVS Overview
Corporate background2
Fastest & most accurate DRC technology
Founded in 2009. Privately held by KM Core
World-wide presence: R&D and support team – Kiev, Ukraine Sales & Marketing provided by TEKSTART LLC ( US, Taiwan, Israel, Japan)
PowerDRC/LVS capabilities3
DRC - design rules checking in layout
LVS – layout vs. schematic verification
NVN – schematic netlists comparison
XOR – diffing of layout versions
Support of antenna rules, pads, latches and other special rules
Fill layers generation
Graphical diagnostics with visualization of violations and shorted nets
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Patent-pending One-Shot™ processing
One-shot ProcessingUnique, encapsulation of rules,
layers & operations
WindowScanning
Unleash
Using
Core technology
PowerDRC™5
The main idea of PowerDRC/LVS is to speed up the process of physical verification by using One-Shot™ processing that delivers maximum CPU efficiency per one rule check
Silicon-proven: 250nm, 180nm, 130nm, 90nm, 65nm, 40nm
Fastest and most accurate flat DRC engine on the market
Predictable performance and behavior
Multi-CPU operations for linear performance gain
Parallel processing 6
PowerDRC benefits from parallel processing of:independent groups of rulesindependent parts of layout
Parallel tasks may be run in multi-CPU mode on:a single hostmulti host grids like Platform LSF or SGENEFELUS cloud service
Scalability proven on 2, 4, 6, 8, 12, 16, 24, 32 CPUs
PowerDRC™- Performance on 1-32x CPUs7
PowerDRC™- Performance on 1-32x CPUs (cont.)8
FAB1, tech 180nm, 36x SRAM memory blocks ~ 20 sq.mm
1600
412
220
140
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0 250 500 750 1000 1250 1500 1750
Pow erDRC 2.0 @1xCPU core
Pow erDRC 2.0 @4xCPU cores
Pow erDRC 2.0 @8x CPU cores
Pow erDRC 2.0 @16x CPU cores
Pow erDRC 2.0 @32x CPU cores
NEFELUS Cloud platform , CPU Intel Xeon E5-2680 V2 2.8 GHz - run tim e, seconds. Less is better
Performance gain with hierarchical mode9
As obtained on real world designs
4.5X Faster
1.94X Faster
1.84XFaster
Design Content:
“A”: 75% logic & 25% memory
“B”: 25% logic & 75% memory
“C”: 2% logic & 98% memory
PowerLVS™10
Supports 7 effective comparison algorithms applied automatically and dynamically depending on the type of encountered blocks to ensure accuracy at the highest level of performance
Silicon-proven: 250nm, 180nm, 130nm, 90nm, 65nm, 40nm
Predictable performance and behavior
Supports extraction of array instances to get up to 10x performance increase
Provides Multi-label, Floating-label, Hier cells and Open nets reports
Graphical debug is provided by PowerRDE and Short Finder utility
PowerLVS performance
Process node: 40nmLP; Hard IP: analog, logic gates and memory cells, ~ 380 million physical gates
Extraction of all devices: 11 hrs + 5 more hrs for output
Comparison: 12.5 hrs
Total LVS time: 28.5 hrs using 1 CPU core and 128 GB of RAM
Process node: PL; Hard IP: LCD 1280x960: analog IP and pixel cell array, ~ 50 million physical gates
Extraction of all devices: 2 min
Comparison: 1 hr and 50 min
Total LVS time: 1 hr and 52 min using 1 CPU and 8 GB of RAM
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Unique features
Advantages from using efficient FLAT engine natively Efficient usage of hardware resources (RAM and CPU) Predictable performance
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Run and Debug Environment (PowerRDE™)13
Allows user to:
Adjust DRC and LVS run parameters
Save them in a run configuration file
Read a saved configuration
Run PowerDRC/LVS
View run progress
Review results
Debug violations, etc.
Proprietary and Confidential
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Short Finder utility (graphical LVS debug component)
Proprietary and Confidential
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Suggests a short location Shorted net polygons in a
table format Allows to assign label for
selected polygon Allows to mark a polygon as
‘deleted’ Recalculates the shortest path Interactive work in KLayout
editor
PowerDRC/LVS integration15
PowerDRC/LVS has interoperability with:
Cadence Virtuoso – CDBA and OpenAccess
SpringSoft Laker – Native
AWR Analog Office
KLayout – Native
Symica DE – demo mode
Supported technology nodes16
Sign-offUMC IHP Silanna L Foundry MOSIS SCMOS
40nm: G & LP65nm: LL, LP & SP180nm: G & LL
250nm130nm 250nm 150nm 500-180nm
Synergic Partnership (AWR)AWR Corporation has been POLYTEDA OEM partner since 2009. PowerDRC/LVS was integrated with Analog Office suite and is available for all Analog
Office customers.More information and demo video are available at:
www.polyteda.com/products-demowww.awrcorp.com/products/analog-office
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To get hand-on experience
PowerDRC/LVS 2.0 – available from either POLYTEDA or NEFELUS Cloud (www.nefelus.com) since July 29, 2014
Order trial version of PowerDRC/LVS online at:
www.polyteda.com/contact-us/submitrequest
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Licensing details• PowerDRC/LVS is licensed on per-CPU basis separately for DRC and LVS
• PowerRDE GUI cockpit requires its own license
• Fill layer generation feature (PowerFIL) requires its own license
• Licensing employs FlexLM license manager
• Licenses are bound either to hostID (MAC-address) or disk serial number or dongle flexID
• Usual license duration is 1 year
• Licenses are valid for all minor version updates but not for major ones, i.e. license for 1.7 is valid for 1.7.1 but not for 2.0
• Short-term licenses may be granted for trial purposes
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Support policy• POLYTEDA is ready to provide offline (email) technical support based on
additional Support and Maintenance Agreement (available).
• In urgent cases a hot fix version may be sent to the customer as soon as the issue is solved.
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