Low Cost, Transportable Power Platform and Flexible Interface for Multiple Hardware Protocols

Adrian Torres, Pradeep Batra, Brian Tsang, and Tsunwai Gary Yip

{atorres, batra, btsang, gyip @ rambus.com} 

Rambus Inc.  Sunnyvale, California  94089  USA1Silicon Valley Test Conference 2010

Outline of Presentation

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• Overview of LabStation environment

• Architecture of LabStation Interface Module

• Architecture of Power Platform

• Illustrations of Power Module capability

LabStation Characterization Environment

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Test Platform

PowerPlatform

LabStationInterfaceModule

LabStationApplication

1

2

LabStation Characterization Environment

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• Common environment for testing systems with different IO cells (e.g. DDR2, DDR3, XDRTM, Mobile XDR

TM& SERDES)

• Adaptation through software update without redesign

• Flexible and reusable LIM and Power Platform

• Ease of transport for worldwide deployment

• Supports development, characterization & production

• Shorten time‐to‐market

• Proven successful  ( PS3, HDTV, Projector ) 

LabStation Interface ModuleCommand Translator

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Power Control Test Control

LIM

App. Specific Control

LabStation Commands

in USB Packets

LabStation Command TranslationScalable Architecture

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LabStation sends commands in packet format under USB Protocol

USB-to-Parallel Interface ConversionRoute packets to FIFO queues

MPC sorts packets and enables corresponding protocol engineProtocol engine executes command

Commands received by power modules, peripherals and test chip

New protocols are easily added

LabStation Packet StructureScalable Architecture

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• Packets are concatenated to fill a USB packet – maximize throughput• Header consists of architected fields:

• To specify which protocol to employ for data transfer• To invoke embedded functions (timing adjustments, reset)

• Reserved fields allow for future expansion

LabStation Port AvailabilityIndependent Command Ports

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• Ports are independently clocked so protocols may operate at different rates• Number of ports may scale beyond the default of two

FIFO Queues

Port 0 Port 1

500 kHz- 16 MHz

500 kHz- 16 MHz

LabStation Power PlatformReusable and Reconfigurable

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• Power Platform - 12 power module, 6 ADC/DAC pairs, 4 clock chips• FPGA for application specific test and control• Programmable power modules with voltage and current sensing

PowerPlatform

Power PlatformPower Distribution Scheme

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12 Power Module Slots:• Programmable Power• Voltage Sensing• Current Sensing

Fixed Voltage Rails

12V INPUT

DC/DC Step Down

ProgrammableModule

Desired Output

Power PlatformClock Distribution Scheme

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2 Banks of 8 Clock Signals• 3 single-ended clock ( under 100 MHz )• 1 differential programmable clock ( 100 – 600 MHz )• 4 differential programmable clock ( 100 – 800 MHz )

Standard PC ClockSynthesizers

XDR ClockGenerators

100 – 800 MHz

Programmable Power Module

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Low cost component allows design to be transferred to production system

Stable Output Achieved by Custom Circuit

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Stable Vout as load varies

Skillful design maximizes performance of low cost voltage regulator

Voltage Output Adjustment

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Two-step Voltage Output Adjustment:• Digital potentiometer for course adjustment• 12-bit DAC for fine adjustment – good linearity

Accuracy of Current Sensing

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Programmable Power Module providesstable output current below 2V

Conclusion

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• LabStation Interface Module– Versatile translator for multiple hardware protocols– Ease of transport for worldwide deployment– Easy to add features for new protocols– Useful for debugging during production phase

• LabStation Power Platform– Highly stable and accurate power delivery system– Programmable & configurable for different test platforms

• Key elements for shortening time‐to‐market