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1

Power Distribution Network Design for High-Speed Printed Circuit

Boards

Jun Fan

NCR Corporation

April 3, 2007

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Outline

• Overview of PDN design in multi-layer PCBs

• Interconnect Inductance

• Individual Capacitor Values

• Capacitor Location

• Power/Ground Plane Pair

• Summary

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PDN in a Multi-Layer PCB

GND

VCC

DC/DC converter

(Power source)

GNDVCC

IC load

VCCGND

SMT capacitors

VCC

GND

IC driver VCC

GND

electrolyticcapacitor

VCC

GND

GND

IC driver

VDC

switch

Z0, vp

IC load

CL

VCC

RSP-MOS

N-MOS PCB trace

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Device Switching

IC driver

VCC

RS

shoot-through current GND

Z0, vp

IC load

VCC

charge

logic 0→1

IC driver

Z0, vp

IC load

0 V

discharge

VCC

RS

shoot-through current GND logic 1→0

Current drawn from power

J. L Knighten, B. Archambeault, J. Fan, et. al., “PDN Design Strategies: IV. Sources of PDN Noise,” IEEE EMC Society Newsletter, Winter 2007, Issue No. 212, pp. 66-76.

Shoot-through

current only

Shoot-through + load charging

current

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Current Supply and Power Bus Noise

VN

VCC

d

IC driver

GND

EMI

EMI

I/O line or cableVnoiseVCC

IC 2

GND

I am Mr. Charge!

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PDN Design Objectives

1. Ensure charge supply for logic transitions• Enough capacitance to store

charge • Enough charge readily

available for short transitions2. Minimize noise voltage

distribution on the VCC/GND plane pair• Low power bus impedance

over frequency• Noise decoupling• Noise isolation

IC driver

VCC

RS

shoot-through current GND

Z0, vp

IC load

VCC

charge

logic 0→1

VN

VCCd

IC driver

GND

EMI

EMI

I/O line or cableVnoiseVCC

IC 2GND

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PDN Design Issues in PCB• Capacitor interconnects; • Individual capacitor values and packaging forms;• Number of capacitors needed; • Capacitor placement;• PCB stack-up;• Power/ground plane pair geometry;• Segmentation and isolation

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PDN Charging/Discharging Hierarchy

The planes can be regarded as a C only @ low frequencies

VDC

Lbulk

Cbulk

Lvia

CSMT

Cplanes

Connectors and wiring Capacitor leads

Electrolytic capacitors

Interconnect

SMT capacitors

VCC/GND planeUltimate Charge Source 100’s uF 0.01-100’s uF pF’s-100 nFVRM (DC/DC converter)

Pin interconnect

BGA packagedIC pins

Speed of charge delivery

Amount of charge available for delivery

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PDN Impedance Profile

10-4

10-2

100

-50

-40

-30

-20

-10

0

10

20

F req uency [G Hz]

Z 21 [d

BΩ]

Power plane distributed behavior

Global decoupling

Bulk cap

Local decoupling

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Outline

Interconnect Inductance- shall be minimized in any situation

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Effect of Inductance

IC loadCLdecoupling capacitor

GNDVCC

Inductance associated with the capacitor: package parasitics, bonding pads, board traces, and vias

Inductance – impedes the flow of current (charge) to the load that will charge it to achieve a logic 1

CjLjRZ

ωω 1++=

LCf res π2

1=

L

C

t=0

v(0)=VS

i(t)

R

)sin()0(LCt

LCVti S=≥

L

C

L

C

R

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Minimizing Interconnect Inductance

SMT Decoupling Capacitor ESL

Loop 1 Lvia

Loop 2 Labove

The “Good”

The “Bad”

The “Ugly”Really “Ugly”

The “Better” The “Best”

Via

Capacitor Pads

SMT Capacitor

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Outline

Individual Capacitor Values- multiple values or maximum value? May not matter

LCf res π2

1=

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Two Common SMT Decoupling Strategies

● Use an array of capacitor values: – This may be the best known approach and is very popular in the

signal integrity design community (SI-LIST).– Rationale: to maintain a flat impedance profile below a target

impedance over a wide frequency range– Typically a logarithmically spaced (10, 22, 47, 100, 220, 470nF,

etc.) array of 3 values per decade.

● Use the largest capacitor value in the package size– This is less well-known, but a popular approach in the EMI

design community– Rationale: to keep impedance as low as possible, less emphasis

on a target impedance and a flat profile

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-20 dB/dec

+20 dB/dec

decoupling capacitors

distributed behavior

Different Approaches : ComparisonApproach A : values of decoupling capacitors logarithmically spaced, i.e. 3 values per decade : 10, 22, 47, 100, etc.

Approach B : largest values of decoupling available in two package sizes, i.e., 0603 and 0402

Approach B1 : largest values of decoupling available in one package size, i.e., 0402.

Target Impedance

Both approaches can meet the design specs relative to the target impedance

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Outline

Capacitor Location- could be important due to PCB geometry

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Background

• Does capacitor location matter?

• How close is close?• What if capacitors can’t

be placed close enough to the IC pwr/gnd pins?

• Is it worth sacrificing routing or using costly new technology in order to get capacitors closer?

• Need a way to facilitate engineering judgment

GND 1.5V 3.3V

decoupling caps

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Location Affects Interconnect Inductance

Interconnect inductance is reduced when the cap is moved closer to the IC ⇒ The capacitor becomes more effective

CjLjRZ

ωω 1++=

LCf res π2

1=

L

C

t=0

v(0)=VS

i(t)

R

)sin()0(LCt

LCVti S=≥

CAP IC

Lbelow

i(t)

P

G

Labove Labove

CAPS

S

L

C

L

C

R

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Equivalent Circuit Model

AB

CD

1L2L

2V1V

k

1IParallel Plate

Geometry

Port 1 Port 2

+ +

decCNI3 3L L ESL′= +

J. Fan, et. al., ``Quantifying SMT decoupling capacitor placement in DC power bus design for multi-layer PCBs,’’ IEEE Transactions on Electromagnetic Compatibility, Vol. 43, No. 4, pp. 588-599, November 2001.

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AB

CD

1L2L

2V1V

k

1IParallel Plate

Geometry

Port 1 Port 2

+ +

decCNI3 3L L ESL′= +

Local Decoupling Effect – Frequency-Domain

' 221

1

VZI

=

2

3

2

3

1132

321

21

21

1

)1(

)()(

LL

LLk

ZLLjMLLj

II

ZZ

N +

+−≈

′++−+==

′ ωω

Equivalent circuit at high frequencies2

21N

VZI

=

' 111

1

VZI

=AB

CD

1L M−

2V1V

1IParallel Plate

Geometry

Port 1 Port 2

+ +

NI

2 3L L M+ −

M

decC

AB

CD

1L M−

2V1V

1IParallel Plate

Geometry

Port 1 Port 2

+ +

NI

2 3L L M+ −

M

01 →decCω

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Local Decoupling Effect – Frequency-Domain

cfΔ

ZΔ

ZΔ

ZΔ

• Increasing series resonant frequency of decoupling capacitor

• Reducing impedance uniformly in a frequency-independent manner (approximately) for frequencies higher than the series resonant frequency

VCC

GND

VCC IC

VCC

VCC GND

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Local Decoupling Effect – Time-Domain

M

L2+L3-M

L1-M

iN(t)

i1(t)

i2(t)dt

tdiMLLdt

tdiM )()()( 232

1 −+≈

Equivalent circuit at early time (t≈0)

)()(32

321 ti

LLMLLti N+

−+=

)(1

)1(

2

3

2

3

ti

LL

LLk

N

+

+−≈1L M−

2V1V

1IParallel Plate

Geometry

Port 1 Port 2

+ +

NI

2 3L L M+ −

M

decC

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Local Decoupling Effect – Time Domain

Reducing initial noise voltage generated in the power bus due to logic transitions.

Time (ns)

Port

2 vo

ltage

(mV

)

VCC

GND

VCC IC

VCC

VCC GND

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Local Decoupling Effect – Charge Delivery

0 1 2 3 4 5 62

2.2

2.4

2.6

2.8

3

3.2

3.4

time [ns]

Vpl

ane

[V]

50 mils400 mils5000 milsNo decap

0 1 2 3 4 5 62

2.2

2.4

2.6

2.8

3

3.2

3.4

time [ns]

Vpl

ane

[V]

50 mils400 mils5000 milsNo decap

35 mil thick 10 mil thick

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Estimating Local Decoupling Effect

02 ln 0.75

2equivRdL Hr

μπ

⎡ ⎤⎛ ⎞= −⎢ ⎥⎜ ⎟

⎝ ⎠⎣ ⎦

ln 0 .75

ln 0 .75

equiv

equiv

Rs r

kR

r

⎛ ⎞−⎜ ⎟+⎝ ⎠≈

⎛ ⎞−⎜ ⎟

⎝ ⎠

4equiva bR +≈For a rectangular power bus,

s – spacing between two vias

d – PWR/GND plane pair spacing r – via radiusRequiv – equivalent radius of power bus

Closed-form expressions derived from the radial transmission-line theory :

assumption: vias are located close to the center of the planes

accounting for fringing effect

⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢

⎣

⎡

+

+−≈Δ

2

3

2

3

1021

1

)1(log20)(||

LL

LLk

dBZ

J. Fan, et. al., “Estimating the noise mitigation effect of local decoupling in printed circuit boards,” IEEE Transactions on Advanced Packaging, Vol. 25, No. 2, pp. 154-165, May 2002.

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220 ln 1 1

2s s

ps ss s

h h l lM hl l h h

μπ

⎧ ⎫⎡ ⎤ ⎛ ⎞⎪ ⎪⎛ ⎞⎢ ⎥= + + + − +⎨ ⎬⎜ ⎟⎜ ⎟⎢ ⎥⎝ ⎠ ⎝ ⎠⎪ ⎪⎣ ⎦⎩ ⎭

220 ln 1 1

2s s

ps ss s

h h r rL hr r h h

μπ

⎧ ⎫⎡ ⎤ ⎛ ⎞⎪ ⎪⎛ ⎞⎢ ⎥= + + + − +⎨ ⎬⎜ ⎟⎜ ⎟⎢ ⎥⎝ ⎠ ⎝ ⎠⎪ ⎪⎣ ⎦⎩ ⎭

( )2via ps psL L M= −

( )

( )

( )

( )

2 2 2 2 2 2

2 2 22 2

2 2 2

2 2 2 2

2 2 272

2 2 2 2

1

2 2 2

2 2 2 2

2 2 32

2 2

2 23

ln

2 23

10 ln

4 tan

2 23

4ln3

t

w p l w p l

l w p ll w p

l w p l

w p w p

w w p lM l w

w w w p l

wlwplp w p l

l p l p

l l p pp ll l p

−

−

⎡⎢− − + + +⎢⎢

⎛ ⎞⎢ + + +⎜ ⎟+ −⎜ ⎟− + + +⎝ ⎠

+ − +

⎛ ⎞+ + +⎜ ⎟= +⎜ ⎟− + + +⎝ ⎠

⎛ ⎞⎜ ⎟− ⋅⎜ ⎟+ +⎝ ⎠

+ − +

⎛ ⎞+ +⎜ ⎟+ +⎜ ⎟− + +⎝ ⎠⎣

⎤⎥⎥⎥⎥

⎢ ⎥⎢ ⎥⎢ ⎥⎢ ⎥⎢ ⎥⎢ ⎥⎢ ⎥⎢ ⎥⎢ ⎥⎢ ⎥⎢ ⎥⎢ ⎥⎢ ⎥⎢ ⎥⎢ ⎥⎢ ⎥⎢ ⎥⎢ ⎥⎢ ⎥⎦

( )

2 2 2 22 2

7

23/ 22 2 3 3

3 ln 3 ln2 10 3t

l w l w w lw l l ww lL

ww l l w

−

⎡ ⎤⎛ ⎞ ⎛ ⎞+ + + +⎢ ⎥+⎜ ⎟ ⎜ ⎟× ⎜ ⎟ ⎜ ⎟⎢ ⎥= ⎝ ⎠ ⎝ ⎠⎢ ⎥⎢ ⎥− + + +⎣ ⎦

trace t tL L M= −3 via traceL L L′ = + where and

l: separation between two via; hs: height of the capacitor from the nearest power

or ground plane ;w: width of the trace connecting two vias, or width

of the capacitor package if no trace ;r: radius of the via ; and p = 2hs.

Estimating Local Decoupling Effect

C. Wang, et. al., “An efficient approach for power delivery network design with closed-form expressions for parasitic interconnect inductances,” IEEE Transactions on Advanced Packaging, Vol. 29, No. 2, pp. 320-334, May 2006.

Validated with

CEMPIE

cap

pad

via

trace

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ICCAP

GNDPWR

IC

CAP

GNDPWR

Dos Don’ts

Design Implications

J. L Knighten, B. Archambeault, J. Fan, et. al., “PDN Design Strategies: II. Ceramic SMT Decoupling Capacitors – Does Location Matter?,” IEEE EMC Society Newsletter, Issue No. 207, Winter 2006, pp. 56-67.

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Design ImplicationsThe ratio of L3/L2• A good indicator of the ability of a power bus to support local decoupling • The lower, the better• Can be greatly increased by even very short trace length from via to pad

PWR/GND pair

thickness L3' (nH)

L3/L2with no

trace

L3/L2 w/extra 100 mil trace

length

L3/L2 w/extra 200 mil trace

length

L3/L2 w/extra 300 mil trace

length10 mils 1.66 6.75 9.13 11.50 13.8835 mils 0.92 1.29 1.98 2.67 3.36

Tabulated values for • Centered power bus in a 62-mil PCB

stack-up• 10 mil via diameter• 0603 SMT capacitor package

cap

pad

via

trace

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Design Implications

SMT de-cap Placement L3' (nH) L3/L2

Obverse 0.45 2.96875

Reverse 2.56 9.5625

The placement of de-cap (obverse or reverse), can be highly dependent on the position of power bus in PCB stack-up.

Always LEAST above-plane inductance!

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Power/Ground Plane Pair- thin is always better

Outline

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Pi Pj

Impedance of the Power/Ground Plane Pair

dZij ∝)(ωC. Wang, et. al., “An efficient approach for power delivery network design with closed-form expressions for parasitic interconnect inductances,” IEEE Transactions on Advanced Packaging, Vol. 29, No. 2, pp. 320-334, May 2006.

( ) ( ) ( ) ( )⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡+

−+=

≠== =∑∑ HM

ijyjyixjxi

nm

M

mjiji

N

n nm

mn

planeij LjLLLLpyyxxf

abkkdj

CjZ ωεεωμ

ωω ,,,,,,1

00 0

22

22

Location Port Dimensions

Higher order mode L

Resonant frequency contributions

Low frequency capacitive term

exists only when i = j

Based on the cavity method:

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Power Bus Thickness Effects on Decoupling

1 10 100 1000 5000-50

-40

-30

-20

-10

0

10

20

30

40

Frequency (MHz)

|Z11

| (dB

Ω)

d = 1 mild = 5 milsd = 10 milsd = 40 mils

1 10 100 1000 5000-80

-60

-40

-20

0

20

40

Frequency (MHz)

|Z21

| (dB

Ω)

d = 1 mild = 5 milsd = 10 milsd = 40 mils

Frequency domain: impedance

a = 12 in

b = 10 in Port 2

Port 1(3 in, 2 in)

(7 in, 4 in)d

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a = 12 in

b = 10 in Port 2

Port 1(3 in, 2 in)

(7 in, 4 in)d

Power Bus Thickness Effects on Decoupling

0 0.5 1 1.5 2 2.5 3-100

0

100

200

300

400

500

Time (ns)

Port

2 vo

ltage

(mV

)

d = 1 mild = 5 milsd = 10 milsd = 40 mils

0 0.5 1 1.5 2 2.5 3-4000

-3000

-2000

-1000

0

1000

2000

3000

4000

Time (ns)

Port

1 vo

ltage

(mV

)

d = 1 mild = 5 milsd = 10 milsd = 40 mils

Time domain: port voltages

0 0.2 0.4 0.6 0.8 10

0.2

0.4

0.6

0.8

1

Time (ns)

Cur

rent

(A)

port 1 current

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0 1 2 3 4 5 62

2.2

2.4

2.6

2.8

3

3.2

3.4

time [ns]

Vpl

ane

[V]

L3 0 .5nHL3 1nHL3 2nHL3 3nHNo decap

0 1 2 3 4 5 62

2.2

2.4

2.6

2.8

3

3.2

3.4

time [ns]

Vpl

ane

[V]

L3 0.5nHL3 1nHL3 2nHL3 3nHNo decap

Power Bus Thickness Effects on Decoupling

35 mil thick 10 mil thick

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Effect of Typical Laminates on Decoupling

Dk Loss Tangent

Thick-ness, d

Comment

4.4 0.02 4, 10, 35 mils

better quality fiberglass/ epoxy resin material

4 0.02 2 mils patented thin FR4 core, widely used.

16 0.006 16 microns (0.63 mils)

ultra-thin material commercially available

20 0.015 0.2 mils ultra-thin material from [7, 8].

10 100 1000 5000-60

-50

-40

-30

-20

-10

0

10

20

30

40

Frequency (MHz)

|Z11

| (dB

Ω)

εr = 4.4, tanδ = 0.02, d = 4 milsεr = 4.4, tanδ = 0.02, d = 10 milsεr = 4.4, tanδ = 0.02, d = 35 milsεr = 4, tanδ = 0.018, d = 2 milsεr = 16, tanδ = 0.006, d = 0.63 milsεr = 20, tanδ = 0.015, d = 0.2 mils

Embedded capacitance (thin laminate) has superior electrical performance

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Summary

Interconnect inductance shall be minimized in any situation: inductance limits the effectiveness of decoupling

Individual capacitor values may not matter: using an array of capacitor values or the largest value in a package size meetsdesign specifications

Capacitor location could be important due to PCB geometry: thin power bus structures (< 10 mils) usually result in a larger L3/L2 value; thus capacitor location is relatively unimportant. Thick power bus structures usually result in a smaller (L3/L2) value, and capacitor placement can be an important design factor

Thin power/ground plane pair is always better: low impedance and high charge availability