Poster Number 126 Digital Atlas V Electronics - DAVE - Modulemp/ATLAS-SCT_DAVE/TWEPP-2011_ATL… ·...
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Cavendish Laboratory, Department of Physics, University of Cambridge Maurice GOODRICK <[email protected]>, Richard Shaw <sha[email protected]>, Dave Robinson <[email protected].uk> Department of Physics and Astronomy, University College London Martin Postranecky <[email protected]k>, Matthew Warren <[email protected]> Poster Number 126 Topical Workshop on Electronics for Particle Physics ( TWEPP-2011 ) Vienna, Austria 26 to 30 Sept. 2011 D igital A tlas V me E lectronics - DAVE - Module DAVE Module ATLAS-SCT has developed a new ATLAS trigger card, 'Digital Atlas Vme Electronics' ( "DAVE" ) Originally designed to replace the NIM electronics used by ATLAS-SCT in USA15 to provide the trigger and veto logic needed in stand-alone physics runs by a 6U VME card, the design quickly grew to incorporate many more generic features. One significant enhancement was to adopt all ATLAS CTP functions to exactly duplicate ATLAS running conditions, whilst incorporating much generic functionality. This evolved the DAVE card into a powerful and flexible logic module, potentially useful to all ATLAS subsystems as well as for other non-ATLAS users. Firmware is developed in a modular fashion allowing code contributions from interested users. Initially the core SCT requirements ( vetoing trigger generation around a BCR ) will be implemented. Further development will aim to provide other CTP functionality, with random trigger generator up to 100kHz, simple and complex dead-time, busy gating, ECR, BCR, etc. generation to give exact same conditions in standalone as experienced in combined runs. USB MCU JTAG Ext. +5V / 3A Power Conn. CLK-IN<1-0> 2x LEMOs 00 Global Reset Switch ( FPGA, MCU ) 4-pin USB AUX. DIL 16x I/Os FPGA JTAG Prog. MODE Hex Switch. 3x STATUS LEDs ( Programmable ) 3x4 LEDs ( Programm.) Programm. Reset Switch CLK-OUT<1-0> 2x LEMOs 00 DATA-IN<7-0> 8x LEMOs 00 DATA-OUT<7-0> 8x LEMOs 00 40-pin DIL HEADER VME J1 VME J2 Red LED – FPGA Prog. Xilinx PROM Prog. FPGA Switch GSI 18x4Mb SRAM Ext. 5V/3A Conn. Spartan3E FPGA Clock MUX/PL L VME Base Address A<31-28> A<27-24> 7x Supply Monitor Red LED 3x Supply OK 80.15733MH z XTAL Osc. VME J2 Clk+4 Delay Lines VME J1 Blue LED 4x Supply OK Set Serial No. SER<7-4> SER<3-0> SIL JTAG for FPGA USB Reset Switch IN<7-0> TTL/NIM Sel. Set Mod. Record MR<7-4> MR<3-0> CLK-IN<1-0> ECL/NIM Sel. CLK-OUT<1-0> ECL/NIM Sel. OUT<7-0> TTL/NIM Sel. DIL JTAG for USB MCU 40-pin DIL HEADER
Transcript of Poster Number 126 Digital Atlas V Electronics - DAVE - Modulemp/ATLAS-SCT_DAVE/TWEPP-2011_ATL… ·...
Cavendish Laboratory, Department of Physics, University of CambridgeMaurice GOODRICK <[email protected]>, Richard Shaw <[email protected]>, Dave Robinson <[email protected]>
Department of Physics and Astronomy, University College LondonMartin Postranecky <[email protected]>, Matthew Warren <[email protected]>
Poster Number126
Topical Workshopon Electronics forParticle Physics( TWEPP-2011 )Vienna, Austria
26 to 30 Sept. 2011
Digital Atlas Vme Electronics - DAVE - Module
DAVE Module
ATLAS-SCT has developed a new ATLAS trigger card,'Digital Atlas Vme Electronics' ( "DAVE" )
Originally designed to replace the NIM electronics used byATLAS-SCT in USA15 to provide the trigger and veto logicneeded in stand-alone physics runs by a 6U VME card, thedesign quickly grew to incorporate many more genericfeatures.
One significant enhancement was to adopt all ATLAS CTPfunctions to exactly duplicate ATLAS running conditions,whilst incorporating much generic functionality.
This evolved the DAVE card into a powerful and flexiblelogic module, potentially useful to all ATLAS subsystems aswell as for other non-ATLAS users.
Firmware is developed in a modular fashion allowing codecontributions from interested users. Initially the core SCTrequirements ( vetoing trigger generation around a BCR )will be implemented.
Further development will aim to provide other CTPfunctionality, with random trigger generator up to 100kHz,simple and complex dead-time, busy gating, ECR, BCR,etc. generation to give exact same conditions instandalone as expe rie nced i n co mbined runs.
USB MCUJTAG
Ext. +5V / 3APower Conn.
CLK-IN<1-0>2x LEMOs 00
Global ResetSwitch( FPGA, MCU )
4-pin USBAUX. DIL16x I/Os
FPGA JTAG
Prog. MODEHex Switch.
3x STATUS LEDs( Programmable )
3x4 LEDs( Programm. )
Programm.ResetSwitch
CLK-OUT<1-0>2x LEMOs 00
DATA-IN<7-0>8x LEMOs 00
DATA-OUT<7-0>8x LEMOs 00
40-pin DILHEADER
VME J1 VME J2
Red LED –FPGAProg.
XilinxPROM
Prog.FPGASwitch
GSI18x4MbSRAM
Ext.5V/3AConn.
Spartan3EFPGA
ClockMUX/PLL
VME Base AddressA<31-28> A<27-24>
7x SupplyMonitor
Red LED3x Supply OK
80.15733MHz XTAL Osc.
VME J2
Clk+4DelayLines
VME J1
Blue LED4x Supply OK
SetSerial No.
SER<7-4>
SER<3-0>
SIL JTAGfor FPGA
USBResetSwitch
IN<7-0>TTL/NIM Sel.
SetMod. Record
MR<7-4>
MR<3-0>
CLK-IN<1-0>ECL/NIM Sel.
CLK-OUT<1-0>ECL/NIM Sel.
OUT<7-0>TTL/NIM Sel.
DIL JTAGfor USBMCU
40-pin DILHEADER
