Portable Heart Attack Detector (PHAD) Final Presentation
description
Transcript of Portable Heart Attack Detector (PHAD) Final Presentation
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Portable HeartPortable HeartAttack DetectorAttack Detector
(PHAD)(PHAD)Final PresentationFinal Presentation
Nov 27, 2005Nov 27, 2005
Technion - Israel Institute of TechnologyDepartment of Electrical Engineering
High-Speed Digital Systems Lab
SupervisorSupervisorDaniel AlkalayDaniel Alkalay
System architecturesSystem architecturesNir GluzmanNir GluzmanAlexei IolinAlexei Iolin
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AGENDAAGENDAProject objectiveSystem block diagramECG signal analysis algorithmFirmware block diagramLabVIEW development platformVI blocks and GUISummary and conclusionsSystem demonstration
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Develop a system that detects R characteristic point and measures ST-elevation and QRS duration.
Implement the system on National-Instrument(*) Real-Time FPGA development environment using LabVIEW graphical programming language.
Project objectiveProject objective
(*)(*) website: http://ni.comPXI-7831RPXI-1042Q
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Basic ECG complex
R
P
Q
S
T
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ST Elevation
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System block diagramSystem block diagram
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ECG signal analysis ECG signal analysis algorithmalgorithm
ECG characteristic points are detected with DWT (Discrete Wavelet Transform). DWT is implemented with “Algorithme à trous” (implementation without decimation).
Source: “A wavelet-based ECG delineator: evaluation on standard databases”,IEEE Transaction on biomedical engineering, April 2004.
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Algorithm Algorithm (cont.)(cont.)
The Wavelet transform (WT) is proportional to the derivative of the filtered version of the signal.
Zero-crossing of the WT corresponds to the local maxima or minima of the filtered signal.
Maximum absolute values of the WT are associated with the maximum slopes in the filtered signal.
Why can ECG characteristic points be detected with Wavelet transform?
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Algorithm Algorithm (cont.)(cont.)ECG waves are composed of slopes and local maxima or minima.
Therefore, QRS complex produces an unique pattern (max-min-max).
5.7 5.8 5.9 6 6.1 6.2 6.3 6.4 6.5-400
-300
-200
-100
0
100
200
time [sec]
d4
ECG signalQ
R
S
T
J
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ECG characteristic pointsdetection flow chart
Detection of Q
Detection of R Detection of S
Detection of J
Calculation ofST level
Calculation ofQRS duration
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Q, S detection
Wavelet Decomposition
d4
RMS condition?
ECG sampling
NO
Globalmax. point?
YES
NO
Q characteristic point
Start R search
Globalmin. point?
NO
S characteristic point
YES
Stop R search
YES
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R detectionStart R search
d4 zerocrossing?
R characteristic point
Stop Rsearch?
YES
Next QRS complex
YES
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Firmware block diagramFirmware block diagramAlgorithm has been implemented in VHDL.Firmware includes 3 main blocks:
Wavelet decomposition. d4 signal processing for QRS complex detection and
calculation of QRS duration. ST elevation calculation.
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Firmware Firmware (cont.)(cont.)Top level
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LabVIEW developmentLabVIEW developmentplatformplatform
Graphical programming language with built-in functions for I/O, control, analysis and data presentation.LabVIEW advantages:
Intuitive graphical development similar to flowcharting. Bulit-in tools for design, control, data acquisition and
data presentation.
What is LabVIEW?
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LabVIEW developmentLabVIEW developmentplatform platform (cont.)(cont.)
Platform includes two independent modules: LabVIEW for Windows (Host):
Floating-point calculations. Data presentation. Off-line data acquisition.
LabVIEW for FPGA: Fix-point signal processing. Real-time data acquisition. VHDL integration.
Synchronizationvia
interrupts
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VI blocks and GUIVI blocks and GUI
Data trans-ceiving between FPGA (signal processing) and host (data presentation) is based on synchronization interrupts.FPGA synchronization interrupts demands sequential framing operations:FPGA VI includes three frames:
I/O and signal processing modules (VHDL core). Sampling time delay. IRQ to host.
HDL clock is synthesized from ‘while loop’ index’s LSB.
FPGA
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VI blocks and GUI VI blocks and GUI (cont.)(cont.)FPGA VI
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VI blocks and GUI VI blocks and GUI (cont.)(cont.)Host
Host includes two independent sub VIs: Test mode for system verification (off-line ECG
analyzing). Real-time controlling mode for analyzing on-line ECG
signals.
Host’s GUI graphically presents both sub VIs outputs and controls FPGA module.
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VI blocks and GUI VI blocks and GUI (cont.)(cont.)Test mode VI
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VI blocks and GUI VI blocks and GUI (cont.)(cont.)Real-time controlling mode VI
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VI blocks and GUI VI blocks and GUI (cont.)(cont.)System’s GUI
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Summary and conclusionsSummary and conclusionsProject involves a system development for a medical application.The system is based on a firmware implementation for a sophisticate signal processing algorithm (DWT).ECG real-time DWT analysis is feasible for HW implementation.This project has familiarized us with new development tools and techniques, such as: LabVIEW, HDL designer, ModelSim, Matlab/Simulink. Real-time system development. HW-SW integration.
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Summary and conclusionsSummary and conclusionsSystem performance
Both QRS complex and R characteristic point FP (False Positive = false alarm) rates are very low.QRS complex TP (True Positive) rate is very high (>95%).R characteristic point TP rate is lower than in Matlab/Simulink model, because implemented algorithm doesn’t use d2 and d3 (in addition to d4).
System can be used as STEMI detector, because QRS complex TP rate is high enough to detect irregular ST level variations on time.
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Summary and conclusionsSummary and conclusionsLabVIEW platform advantages
Rapid prototype system.Dedicated hardware and software.I/O easy access.
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Summary and conclusionsSummary and conclusionsLabVIEW platform disadvantages
Development environment is non-conventional - design extraction to other non NI environments is NOT possible.VHDL code is hidden from user.
Lack of debugging tools.
Unfriendly VHDL interface.
Emulator supports FPGA simulations but doesn’t support IRQ simulation (FPGA-Host data trans-ceiving).
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System demonstrationSystem demonstration
The faculty ofmechanical engineering
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Questions?Questions?