Politecnico di Torino - ICT school • B1 Logic families • B2 ... · • B3 Basic sequential...
Transcript of Politecnico di Torino - ICT school • B1 Logic families • B2 ... · • B3 Basic sequential...
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DIGITAL ELECTRONICS
B – DIGITAL CIRCUITS
B.1 – Logic devices
» Static and dynamic parameters
» Interfacing and compatibility
» Power consumption
» BJT and CMOS logic circuits» Examples of data sheets
Politecnico di Torino - ICT school
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Group B: Digital circuits and devices
• B1 Logic families• B2 Combinatorial circuits• B3 Basic sequential circuits• B4 Counters and x-stable circuits
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Lesson B1: logic devices
• Static power consumption• Dynamic power consumption• Pass gates• Bipolar logic families• MOS logic families• Interfacing• Examples of data sheets
– Reference 1: Storey chap 14
– Reference 2:
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Power consumption
• The operation of any module requires some energy– Part is used for internal operations
» Useful
– Part is used for external output signals» Part useful (Shannon theorem !), part wasted (EMI)
– Part becomes heat» Wasted
• The energy comes from the power supply systems– Usually a fixed power supply voltage (Val),
such as 5 V, 3,3 V, 2,5 V, …
– The measure or “power consumption” is the current sink from the power supply system
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Why should we care of power ?
• High currents involve: – Thick wires/tracks (with large size, weight)
– Generation of electromagnetic interferences (EMI)
• Large power supply units– Fixed sets: weight, size, cost
– Portable sets: reduced duration of batteries
• More heat to dissipate in the environment– A major limit for integration density
– Need for special packaging and cooling
• Environment – ecology issues (marginal)
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Static power: P S
• Power used with no state change– Almost constant current from power supply
– Changes with temperature and supply voltage Val
– Modeled as a DC current (Idc) from Val to GND
Idc
OUTIN MODULODIGITALE
VAL
GND
VAL
GND
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Dynamic power: P D
• Power used to get a state change (H�L o L�H)– Current IL , to charge/discharge the output capacitor
– Flows only on state changes
ILOUT
INMODULO DIGITALE
VAL
GND GND
C
VAL VAL
L�H H�L
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Evaluation of dynamic power
• Charge in a capacitor: Q = C*V• Current I = charge moved in 1”
– If the capacitor is charged/discharged F times per second, that corresponds to a current flow I = F*C*V
• Power PD = V*I– Change the voltage V on a capacitor C F time/sec requires a
power
PD = V*I = F*V*V*C
PD = F C V2
depends from V and C (technology !)
OutIn
Val
Gnd
IL
Gnd
C
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Static and dynamic power
• Static power PS depends on device technology and resistive loads
– Low power structures: almost 0 power consumption in static conditions (no state change)
• Dynamic power PD depends mainly on capacitive loads (and, to a smaller exent, on device technology)
• Low power integrated circuits– Mainly static power
• High speed integrated circuits– Mainly dynamic power
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How to reduce power ?
• Power: PD = F C V2
• Reduce switching rate F– Same number of state changes, more time
» No benefit in terms of dynamic power » Actually worse: static power needed for more time
– Algorithms with less logic state changes
• Reduce capacitance C– Technology improvements (smaller devices)
• Reduce the logic excursion VH – VL
– A square term, heavy impact
– Keep noise margins (LV logic families, differential signalling)
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The speed * power product
• An ideal logic circuit:– No power dissipation: PD = 0
– No delay: TP = 0
• A real logic circuit:– Power and delay as low as possible
• PD and TP depends on parasitic capacitance C and on the charge/discharge currents of capacitors
– C depends on technology
– I is a designer’s choice» High currents: high speed, high power
» Low currents: low speed, low power
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PD x TP and technology
• For a given technology – PD * TP product (of a single gate) is fixed
» Hyperbole in the (PD, TP) diagram
• The actual “quality” parameter for a technology is
power * delay product (PD * TP )
• Improving the technology – Reduced C
– Reduced ∆V (without impact on noise margin)
– Lower power dissipation
– Lower delay
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PD x TP vs technology
HyperbolesTP * PD = K
PD
TP
Fast circuits(low TP)
Slow circuits(high TP)
Slow, low power(low PD)
Fast, high power(high PD)
Technologyimprovements
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Power consumption in R/SW gates
• Static condtitions, no load– H state : SW open �current = 0, power = 0
» Only small leakage current
– L state : current = VAL/RPU, power PS = VAL2/RPU
– Duty cycle 50%» Current flows for 50% of the time
» Average static power PS = VAL2/2RPU
– Duty cycle D (between 0 and 1)» Average static power PS = D VAL
2/2RPU
• Total power consumption PT = PS + PD
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Power consumption in CMOS gates
• Static conditions, no load– H state, L state : current = 0, power = 0
» Real devices have small leakage currents
• Dinamic conditions PD = C F VAL2
• Simple circuits: most of the power consumption comes from switching � dynamic power
– Dynamic power can be limited by blocking the clock, or lowering the clock rate
• Complex, last generation circuits: most of the power consumption comes from leakage (static)
– Strictly related to technology
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Power vs switching rate
Clock rate
power
Dynamic power consumption, proportional to clock rate
Total power consumption
Static power; independentfrom clock rate0
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Power consumption trend
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Pass Gate - structure
• Logic functions which use switches in the signal path(not towards GND or Vsu)
• Example: 2-input multiplexer– SWn closed by a 1,
SWp closed by a 0» S U
0 A1 B
– U = A S* + B S
• If B = A*, the logic operation is exclusive OR (XOR)
AU
SWn
SWp
B
S
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• pass gate – 2 MOS
– 1 inverter
– Total 4 MOS
• Standard gate structure– 3 x 2-input NANDs
– 1 inverter
– Total 14 MOS
Multiplexer with Pass Gate
U = A x S + B x S* B
A
S
B
A
SU
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XOR with pass Gate
• Pass gate– 2 MOS
– 2 inverters
– Total 6 MOS
• Standard gate structure– 3 x 2-input NANDs
– 2 inverters
– Total 16 MOS
U = A xor S A
S
A
S
U
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Problems with pass-gate
• Switches use pMOS and nMOS in parallel– Lower and more linear RON
– Doubles the number of devices
• A pass gate does not rebuild the logic levels– Reduced noise margin
– Can be used on a single (or very few) level
• Interleave standard gates to rebuild logic levels
• Allow lower device count for some functions (see previous examples)
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Lesson B1: logic devices
• Static power consumption• Dynamic power consumption• Pass gates• Bipolar logic families• MOS logic families• Interfacing• Examples of data sheets
– Reference 1: Storey chap 14
– Reference 2:
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Logic families
� We have seen that different devices use different voltages ranges for their logic levels.
� They also differ in other characteristics.
� In order to assure correct operation when gates are interconnected they are produced in families .
� We will look briefly at a range of logic families, then concentrate on the most important ones, namely TTLand CMOS.
14.3
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Logic families
• The switches are built with MOS or BJT devices
• Logic circuits are grouped in families– ICs within a family has same/compatible electrical
parameters
• Current technology focused on C-MOS families:– High speed HC
– Low voltage LV
– TTL compatible HCT ACT BCT LVT
• Bipolar families (LS, F, …) are becoming obsolete
• Mix of technologies in BiCMOS for highest speed
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74/54 logic families
• COTS SSI … MSI functions
• Label structure74 XX NNN or54 XX NNN
– 74 XX NNN standard temperature range (0 - 85 C, office and consumer applications)
– 54 XX NNN extended temperature range (-55 - 125 C, automotive and space applications)
XX identifies sub-family (LS, F, C, ...)
NNN identifies the function(OR, NAND, register, …)
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Examples of 74’ devices
• 74F00– TTL Fast family, 4 x 2-in NAND gates
• 54LS04– TTL-Lowpower Shottky, 6 x inverters, extented temperature
range
• 74ACT245– C-MOS Advanced Cmos Ttl compatible, 8 x bidirectional
buffer,
• 74F245– Fast family, same functions and pinout as above,
Elettronica II - Dante Del Corso - Gruppo B - 7 n. ## - //
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Examples of logic device pin-outs
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CMOS families
� Standard CMOS (4000B)– oldest form of CMOS – now largely obsolete– Slow, Vdd 3-18, Very high noise immunity
� CMOS with TTL pin-out (74C/HC/HCT/AC/ACT/LV/ALVC/…)– High-speed CMOS (74HC) / TTL compatible inputs
(74HCT)– Low-voltage CMOS (74LV)– Advanced, low-voltage CMOS (74ALVC)
� supply voltages between 1.65 and 3.6 V� considerable speed advantage compared to the 74LV series
– BiCMOS (74BCT), low-voltage BiCMOS (74LVT)
14.5.4
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� CMOS gate protection circuitry– CMOS inputs
must not be left unconnected
– unused inputs should be tied to ground (logic 0) or to the positive supply rail (logic 1)� unused inputs to an AND or NAND gate should be tied high� unused inputs to an OR or NOR gate should be tied low.
CMOS inputs
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CMOS input threshold
• Input threshold depends on – W/L of input MOS transistors
– Supply voltage
• Two different devices (nMOS, pMOS)
– Different processing steps
– Difficult to get precise parameters
– Wide spreading of thresholds
• To get precise threshold– Differential inputs
GND
VAL
VI
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NAND CMOS structure
• nMOS switches in series towards GND– Output = 0 � all SWn closed
» Both inputs = 1
• pMOS switches // towards VAL
– Output = 1 one SWp closed » At least one input = 0
• Logic function: NAND
I1 I2 U0 0 10 1 11 0 11 1 0
I1
I2 SWN2
VAL
U
SWN1
SWP2SWP1
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Complex logic
• Get the logic function
OUT = ( A* · B* ) + C* + D*
• Apply De Morgan’s
OUT* = (A + B) · C · D
– Closed SW bring OUT to 0
– OR (+) � parallel connection
– AND (·) � series connection
H = closed
ABC
OUT
VAL
D C
A B
D
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CMOS
� CMOS– part of a typical
CMOS data sheet
14.5
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A comparison of CMOS families
400474LVTXXLow-voltage BiCMOS
6003.574BCTXXBiCMOS
50374ALVCXXAdvanced, low-voltage
50974LVXXLow-voltage
25674ACTXXAdvanced, TTL compatible
25474ACXXAdvanced
50
25
25
50
8
12
74CXX
74HCXX
74HCTXX
Standard, TTL pin-out
High-speed
High-speed, TTL compatible
50754000BStandard
Static power per gate ( µµµµW)
TPD (ns)DescriptorFamily
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Diode logic family
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Diode-transistor logic family
� A DTL NAND gate
Add an activeelement toDiod Logic
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� Replacing the diodes of a DTL gate with transistors
Transistor-transistor logic family
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TTL two-input NAND gate
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TTL data sheet
� Standard TTL– part of a typical
TTL data sheet
14.4
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TTL input threshold
• Which input voltage to turn ON T4 ?
– Follow the path from Va to GND
– How many junction drops ?
EB(T1)+BC(T1)+BE(T2)+BE(T4)
total 3 – 1 = 2 junctions
• ON if Va > 1.2 V
– Independent from supply voltage
– Small spreading
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– noise immunity in logic 1 (high) VNIH = VOH(min) - VIH(min) = 2.4 – 2.0 = 0.4 V
– noise immunity in logic 0 (low) VNIL = VIL(max) - VOL(max) = 0.8 – 0.4 = 0.4 V
—3.62.4VOH
0.40.2—VOL
——2.0VIH
0.8——VIL
MaximumTypicalMinimum
TTL noise immunity
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– use of an open collector gate with an external load
TTL Open Collector output
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Low-power TTL (74L)
� a 74L00 two-input NAND gate
14.4.5
Same structure asstandard TTL, buthigher resistor values
� lower currents� lower power cons.� lower speed
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� 74H00 two-input NAND gate
High-speed TTL (74H)
Same structure asstandard TTL, butlower resistor values
� higher currents� higher power cons.� higher speed
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� Fast diodes and transistors, with low drop (.3 V)
Schottky diodes and transistors
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� 74S00 two-input NAND gate
Schottky TTL (74S)
Same structure asstandard TTL, butuses Schottky devices
� faster switching
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� 74LS00 two-input NAND gate
Low-power Schottky TTL (74LS)
Same structure asstandard TTL, butcombines Schottkydevices with high value resistors
� low currents� low power cons.� fast switching
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A comparison of TTL families
42.774FXXFAST
1474ALSXXAdvanced low-power Schottky
29.574LSXXLow-power Schottky
8.51.574ASXXAdvanced Schottky
19374SXXSchottky
22674HXXHigh-speed
13374LXXLow-power
10974XXStandard
Power per gate (mW)
TPD (ns)DescriptorFamily
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TTL vs C-MOS
• Input currents:– Practically 0 for MOS / CMOS circuits (only leakage; < µA)
– Not 0 and asymmetric for bipolar/TTL
• Output stage:– Symmetric for CMOS
– Asymmetric for TTL
• Power consumption:– Mainly dynamic for CMOS circuits
(depends on switching frequency)
– Dynamic + static for TTL
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Interfacing TTL and CMOS14.6
The pullup resistor provides the proper High level
Same technique for any interface with different VH
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• Unused TTL inputs left unconnected float to logical 1– If left floating, they are then very susceptible to noise
– Unused inputs should be tied to ground (logic 0) or to the positive supply rail (logic 1), depending on the logic function
– To limit input current, connect to Vcc through a resistor
• Unused CMOS inputs left unconnected pick static E-field, and can float to unknown state
– Input voltages in the transition region may damage CMOS devices (both transistors go in almost-ON state � high current)
– Even if within correct range, the logic state is undefined
– Never leave CMOS inputs floating
– Tie unused inputs to 0V or Vdd, depending on the logic function
TTL inputs vs CMOS inputs
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� A non-saturating logic gate.
Emitter Coupled Logic (ECL)
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� three-input ECL OR/NOR gate
ECL gate
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A comparison of logic families
1.5 – 2001 – 41.5 – 33TPD (ns)
ExcellentGoodVery goodNoise immunity
1@1 MHz4 – 551 – 22Power per gate (mW)
>502510Fan-out
NAND-NOROR/NORNANDBasic gate
CMOSECLTTLParameter
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1011 – 1013Tera-scale integration (TSI)
109 – 1011Giga-scale integration (GSI)
107 – 109Ultra large scale integration (ULSI)
105 – 107Very large scale integration (VLSI)
103 - 105Large scale integration (LSI)
30 - 103Medium scale integration (MSI)
2–30Small scale integration (SSI)
1Zero scale integration (ZSI)
Number of transistorsIntegration level
Integration glossary
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Lesson B1: final test
• Describe static power dissipation in logic circuits.
• Discuss how a high speed clock can reduce power consumption.
• Explain the meaning of “logic family”
• Which parameters influence the threshold of CMOS logic circuits?
• Which parameters influence the threshold of BJT logic circuits?
• Which are the differences between TTL and CMOS families?