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A Robust Multi-Objective Controller of VSC-

Based DC-Voltage Power Port in Hybrid

AC/DC Multiterminal Grids Masoud Davari and Yasser A.-R. I. Mohamed

davari@ualberta.ca and yasser2@ualberta.ca

Electrical and Computer Engineering Department, University of Alberta, Edmonton, Canada, T6G 2V4

SYSTEM CONFIGURATION AND MODELING

PROPOSED CONTROLLER

ABSTRACT

Conclusion

Figure 1. Hybrid network system under study.

Figure 4. The structure employed to design a controller which is robust against operating point variations

LOGO

Hybrid ac/dc multi-terminal grids are gaining high momentum under the

smart grid paradigm to integrate renewable and clean energy resources

either in the transmission or distribution systems. This poster presents a

robust multi-objective controller for the voltage-source-converter (VSC)-

based dc-voltage power-port in hybrid ac/dc networks.

Objective:

Excellent Tracking Performance, Robust Disturbance Rejection, and Robust

Stability against Operating Point and Parameter Variation with a Simple

Fixed-parameter Low-order Controller.

Method:

A two-degree-of-freedom control structure is proposed, where feed-forward

tracking and base-line robust disturbance rejection controllers are employed

to decouple disturbance rejection and tracking objectives. A disturbance

rejection controller is designed, based on the singular-values (µ) synthesis

approach, to achieve robustness against variation in converter operation

point. Further, the effect of parametric uncertainty in the effective dc-link

capacitance is mitigated by modifying the robust disturbance rejection

controller, via the polynomial method, to ensure that the closed-loop poles

are allocated in the pre-defined region in the complex plane.

A robust controller with a simple fixed-parameter low-order structure has been

proposed for the dc-energy-pool-based ac/dc multi-terminal micro-grids. The

salient features of the proposed controller are 1) robust disturbance rejection

performance under wide range of large and fast dynamic changes in the

converter operating points and large-signal disturbances (e.g. power reversal at

rated and over-load (contingency) conditions; low-impedance unsymmetrical

fault conditions; and connection/disconnection of loads/sources in the dc-energy

pool); 2) the controller eliminates the need of using external power disturbance

feed-forward control, which improves the reliability and cost measures by

creating a dc-power (or dc-current) sensor-less robust disturbance rejection

controller; 3) robust control performance under possible variation in the

equivalent dc-link capacitance due to connection/disconnection of dc loads

and/or sources in the dc-energy pool; and 4) simple fixed-parameter low-order

linear control structure with robust performance in spite of the highly nonlinear

dc-link voltage control dynamics. With these features, the proposed controller

remarkably contributes to the stability and reliability of multi-terminal ac/dc

networks. Theoretical analysis as well as simulation and experimental results

have been provided.

SIMULATION AND EXPERIMENTAL RESULTS

Figure 2. DG unit hierarchical control interface.

Complete model:

Figure 6. Response of the closed-loop system employing a) PI-lead controller. b) proposed controller. c) d-component of the VSC-m current using proposed controller.

When the energy stored in the

interface reactors is considered, the

power balance equation becomes:

If the energy stored in the

interface reactors is ignored, then

the power balance equation can

be written as:

After linearization around an

operating point, one reaches:

Figure 3. (a) Frequency response of the complete dynamics at

different operating modes. (b) Pole-zero map of the closed-loop

system with PI controller and variable Ceq (12.5mF to 100mF) at

rated power in inversion mode. c) at rated power in the

rectification mode.

Average

Model of

Ideal

Three

Phase VSC

Vnull

PLL

abc to dq ρ ρ

Vsq

Vsd

R+ron ia

ib

ic

L

L

L

R+ron

R+ron

+Vsa-

iqid

ia ib icmcmbma

Vta

Vtb

Vtc

iLoss C

iDCiext

-

VD

C

+

PextPDC

Pt Ps and Qs

+Vsb-

+Vsc-

VSC-m

Average

Model of

Ideal

Three

Phase VSC

Vnull_2

PLL

abc to dq

ρNVsq

Vsd

R+ron ia

ib

ic

L

L

L

R+ron

R+ron

+Vsa-

iqid

ia ib icmcmbma

Vta

Vtb

Vtc

iLoss

iDC

-

VD

C

+

Ps and Qs

+Vsb-

+Vsc-

VSC-PQ

K (s)+-

Id _ ref V DC2

_ ref

++

G-1

i (s)

P f (s ) G N -i (s)e(t)

(.)2

V DC _ ref

(.)2

V DC _ ref

Id _ ref +-

PI

Controller

I d

V sd

Iq _ ref PI

Controller

I q

V sq

+-

-2 / Vdc

2 / Vdc

m d

m q

K (s)+-

V DC2

_ ref

++

G-1

i (s)

P f (s ) G N -i (s)e(t)

(.)2

V DC _ ref

(.)2

V DC _ ref

Ps

Id _ ref +-

PI

Controller

I d

V sd

Iq _ ref PI

Controller

I q

V sq

+-

-2 / Vdc

2 / Vdc

m d

m q

dq to abc

m qm d

m cm bm a

Sequence Analyzer

and

Phase - Locked - Loop ( PLL )

V sa V sb V sc V ta V tb V tc

V sd+ V sd

- V sq+ V sq

- V td+ V td

- V tq+ V tq

-

Dual - Sequence Current -

Command Generator

Id- Iq

+ Iq-

Qs _ ref

Proposed DC -Voltage Control System

Zone I: VSC-m: DC-Voltage Power Port connected to Grid1

L1

CLVL

S1

S2

iL1iESS

Average

Model of

Ideal

Three

Phase VSC

abc to dq ρ

ron

ron

ron

iqid

ia ib icmcmbma

CW

PMSG

CH

Zone II: PQ VSC

connected to grid 2

Zone IV: DC Micro-grid with

Energy Storage System (ESS)

Id_ref

+-Current

Controller

Id ωLs

Σ

Vsd

Iq_ref Current

Controller

Iq ωLs

Σ

Vsq

+-

-2/Vdc

2/Vdc

md

mq

Wind Turbine Current Controller:

VL

VL_Ref+-

PI

ControllerPWM

S2

iL1

iL_Ref+-

PI

ControllerPWM

S1

S1=0

S2=0

Bidirectional DC-DC Converter:

Voltage Controller; buck mode

Current Controller; boost mode

Ccable

Grid 1

Grid 2

PDCPt

DC Energy

Pool

Main

Breaker

VCap_Charger

Interlocked

breaker #1

ρωL

ωL

Zone III: Full-Scale Wind Turbine

with AC/DC VSC Positive-sequence

current controller

Dual Sequence Current

Controller

Ps_ref

and

PLL

Vsa Vsb Vsc Vta Vtb Vtc

Vsd+ Vsd

- Vsq+ Vsq

- Vtd+ Vtd

- Vtq+ Vtq

-

Dual-Sequence Reference-

Current Generator

Id+ Id

- Iq+ Iq

-

Qs_ref

Sequence Analyzer

Rcable

Lcable

Rcable

Lcable

Rcable

Lcable

Rcable

Lcable

RDC

Mode 2:

Buck Mode

Mode 1:

Boost Mode

+

VL

-

Σ

Σ

VSC-W

Energy

storage

DC-micro-

grid load

ρN

K(s)+-

Id_ref VDC

2_ref

++

G-1i(s)

Pf(s) GN-i(s)(.)2VDC_ref

(.)2

K(s)+- ++

G-1i(s)

Pf(s) GN-i(s)

e(t)

(.)2

(.)2VDC

VSC-m Control Scheme:

DC-Voltage Power Port

Sequence Analyzer

and

Phase-Locked-Loop (PLL)

Vsa Vsb Vsc Vta Vtb Vtc

Vsd+ Vsd

- Vsq+ Vsq

- Vtd+ Vtd

- Vtq+ Vtq

-

Dual-Sequence Current-

Command Generator

Id- Iq

+ Iq-

Qs_ref

Proposed DC-Voltage Control System

Id-

2(0.5 )eq DC ext DC loss

dC V P P P

dt

2 20.5 ( ) 1.5DC p eq DC p ext p sd d

dV R C V R P R V I

dt

2

0

0

1( )

(0.5 1)

11.5 ( )

(0.5 1)

11.5 ( )

(0.5 1)

DC p ext

p eq

p d sd

p eq

p sd d

p eq

V s R PR C s

R I V sR C s

R V I sR C s

2 2

1.5( )

(3 0.5 | | ) 1.5 | | 1.5

td d tq q

sd d

V I V I

dL I R I V I

dt

2

0

0 0

0 0

0

0 0

( ) ( )0.5 1

12

1.5 ( 2 ) ( )0.5 1

0.5 11.5 3 ( )

0.5 1 0.5 1

P

DC ext

P eq

d

sd d

P sd d d

P eq

P d

sd P q q

P eq P eq

RV s P s

R C s

LIs

V RIR V RI I s

R C s

R I LsRV RR I I s

R C s R C s

After linearization around an

operating point, one reaches:

-100

-50

0

50

100

150

Ma

gn

itu

de

(d

B)

10-2

10-1

100

101

102

103

104

105

106

-90

-45

0

45

90

135

180

Ph

as

e (

de

g)

Bode Diagram

Frequency (rad/s)

Pole-Zero Map

Real Axis

Imagin

ary

Axis

-300 -250 -200 -150 -100 -50 0-150

-100

-50

0

50

100

150

Pole-Zero Map

Real Axis

Imagin

ary

Axis

-200 -150 -100 -50 0 50 100 150 200 250 300

-250

-200

-150

-100

-50

0

50

100

150

200

250

Inversion

Rectification

K(s)id_ref VDC

2 e(t)

++

++

W(s) ∆(s)

Gi(s)+-

Wd(s)

Disturbances of the Main Plant

Wp(s)

Uncertain System

VDC2_ref

0

6

4 12

1 10 1 1

(0.5 ) 1 10 1

p

q

d

p e

R

R Cs

sW

s s

4

1

10p

sW s

0

i

1.5 1

s 10.5 1

p d

p eq

R LIW

s

R Cs

s

STABILITY AND PERFORMANCE ANALYSIS

79.1010389.310894.210842.3

1001.210813.210711.110179.4

)(

)()(

529354

1192734

ssss

sss

sx

sysK

Theorem 1: Given a stable polynomial matrix D(s) of size n and degree d,

referred to as central polynomial, polynomial matrix N(s) is stable if there

is a symmetric matrix of degree d, P=P*, satisfying the following LMI

0 * *D N  N D H P*H(P) (S P) where , is tensor product and Π is matrix of size

with appropriate distribution of the identity and zero matrices.

18 3 15 2 13 12

20 4 17 3 13 2 17

4.9379 1.8506 1.8747 8.3792

1.3586 5.5176 3.2832 5.5176

10 s 10 s 10 s 10K s

10 s 10 s 10 s 10 s

-400

-300

-200

-100

0

100

200

Ma

gn

itu

de

(d

B)

10-6

10-4

10-2

100

102

104

106

-90

0

90

180

270

Ph

as

e (

de

g)

Bode Diagram

Frequency (rad/s)

Figure 5. Disturbance rejection performance with the proposed controller at different operating points.

0.7 0.75 0.8 0.85 0.9 0.95 1 1.05900

1000

1100

1200

1300

1400

1500

1600

Time (Sec)

Vd

c (

V)

with feed-forward

without feed-forward

0.7 0.75 0.8 0.85 0.9 0.95 1 1.051400

1450

1500

1550

1600

Time (Sec)

Vd

c (

V)

0.7 0.75 0.8 0.85 0.9 0.95 1 1.05-4000

-3000

-2000

-1000

0

1000

2000

3000

4000

Time (Sec)

Id

VS

C-m

(A

)

Figure 7. Response of the proposed controller under severe loading, i.e. switching bidirectional dc-dc converter embedded in ESS. a) Vdc b) d-component of the VSC-m

current

2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 31400

1450

1500

1550

1600

1650

Time (Sec)

Vd

c (

V)

2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3-6000

-5000

-4000

-3000

-2000

-1000

0

1000

2000

3000

Time (Sec)

Id

VS

C-m

(A

)

0.8 0.9 1 1.1 1.2 1.31300

1350

1400

1450

1500

1550

1600

1650

Time (Sec)

Vd

c (

V)

0.8 0.9 1 1.1 1.2 1.31470

1480

1490

1500

1510

1520

1530

Time (Sec)

Vd

c (

V)

0.8 0.9 1 1.1 1.2 1.3-500

0

500

Time (Sec)

Ph

ase V

oltag

e o

f G

rid

II (

V)

Figure 8. Response of the closed-loop system under asymmetrical fault in the ac side of Zone-II employing a) PI-lead controller. b) proposed controller. c) Grid 2 voltages.

Figure 9. Experimental results of the PI-lead

controller with a) harsh dynamic dc load b)

moderate dynamic dc load c) changes of dc

link equivalent capacitance d)

aforementioned scenarios with the

proposed controller; all three scenarios have

very similar responses for the proposed

controller.

a) b)

c)

a) b)

a) b)

c)

a)

b) d)

c)