`timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////// Company: // Engineer: // // Create Date: 08:26:01 05/25/2015 // Design Name: // Module Name: pm // Project Name: // Target Devices: // Tool versions: // Description: //// Dependencies: //// Revision: // Revision 0.01 - File Created// Additional Comments: ////////////////////////////////////////////////////////////////////////////////////module piplinedmul(input [3:0]x,y,input clk,output [7:0]p,output [3:0]x_bar,output [1:0]neg,two,one,zero,output [7:0]p0,p1);wire [3:0]z;boothencoder e1(x,y,clk,x_bar,neg,two,one,zero,z);partialproductgenrator b1(x_bar,neg,clk,two,one,zero,z,p0,p1);rca c1(p0,p1,clk,p);endmodule

module partialproductgenrator(input [3:0]x_bar,x,input clk,input [1:0]neg,two,one,zero,output reg [7:0]p0,p1);reg [3:0] naj;initialbeginp0=0;p1=0;endalways@(posedge clk)beginif(neg[0])naj=x_bar;elsenaj=x;if(two[0])beginp0[0]=1'b0;p0[4:1]=naj;p0[7:5]={p0[4],p0[4],p0[4]};endelse if(one[0])beginp0[3:0]=naj;p0[7:4]={p0[3],p0[3],p0[3],p0[3]};endelse if(zero[0])begin p0=0;end

if(neg[1])naj=x_bar;elsenaj=x;if(two[1])beginp1[2]=1'b0;p1[6:3]=naj;p1[7]={p1[6]};

endelse if(one[1])beginp1[5:2]=naj;p1[7:6]={p1[5],p1[5]};endelse if(zero[1])begin p1=0;endendendmodule

module boothencoder(input [3:0]x,y,input clk,output reg [3:0] x_bar,output reg [1:0]neg,two,one,zero,output reg [3:0] z);reg [3:0]x_not;reg cout;reg [1:0]d0;reg [1:0]d1;reg [1:0]d2;always@(posedge clk)begind0={y[1],1'b0};d1={y[2],y[0]};d2={y[3],y[1]};neg=d2;two=(((d1&d0)&(~d2))|((d2&(~d1&~d0))));one=d1^d0;zero=((~d0)&(~d1)&(~d2))|(d0&d1&d2);z=x;x_not=~x;x_bar=x_not+1;endendmodule

module rca(input [7:0] s1,c1,input clk,output [7:0] p);wire [7:0]c;ha h1(s1[0],c1[0],clk,p[0],c[0]);fa f1(s1[1],c1[1],clk,c[0],p[1],c[1]);fa f2(s1[2],c1[2],clk,c[1],p[2],c[2]);fa f3(s1[3],c1[3],clk,c[2],p[3],c[3]);fa f4(s1[4],c1[4],clk,c[3],p[4],c[4]);fa f5(s1[5],c1[5],clk,c[4],p[5],c[5]);fa f6(s1[6],c1[6],clk,c[5],p[6],c[6]);fa f7(s1[7],c1[7],clk,c[6],p[7],c[7]);

endmodule

module ha(input a,b,clk,output reg s,c);always@(posedge clk)begins=a^b;c=a&b;endendmodule

module fa(input a,b,clk,cin,output reg s,c);always@(posedge clk)begin s=a^b^cin; c=(a&b)|(b&cin)|(cin&a); endendmodule