Pld

Programmable Logic Devices (PLD)

04/08/23VLSI SMDP-II 1

Outline

Introduction to PLD

Why CPLD?

Why FPGA?

Comparison of CPLD & FPGA

Gate array Design

Getting started with ISE 7.1i

Different ways of simulation

Flow of Implementation


Introduction to PLD

ASIC (Application Specific Integration Circuit):

- Fixed functionality

- Digital IC 74xx series

Concept of PLD (Programmable Logic Device): It is possible to manufacture chips that contain relatively

large amounts of logic circuitry with a structure that is not fixed means we can modify (to some extent) according to our requirement.

Such chips are introduced in 1970 and are called PROGRAMMABLE LOGIC DEVICES.

Evolution of PLD

- PROM ,PLA ,PAL, CPLD, FPGA04/08/23VLSI SMDP-II 3

Advantages of PLD

Advantage of PLD – Ease of design changes – Flexibility – No ASIC re-spin risk – Easy & faster design Implementation – Shorter time to market


Programmable Logic Devices


Programmable Array Logic


Programmable Array Logic


w= ABC’ + A’B’CD’X= A + BCDY=A’B + CD + B’D’Z= ABC’ + A’B’CD’ + AC’D’ + A’B’C’D = W + AC’D’ + A’B’C’D

Programmable Logic Array


F1= AB’ + AC +A’BCF2= ( AC + BC )’

Outline

Introduction to PLD

Why CPLD?

Why FPGA?

Comparison of CPLD & FPGA

Gate array Design





Why CPLD?

CPLD (Complex Programmable Logic Devices) Features:

Low development cost Faster time to market Reduced PCB area Ease & Simple way to

implement a design04/08/23VLSI SMDP-II 10

Structure of CPLD


CPLD (Complex Programmable Logic Devices)

Advantages :

- Simplified design process.- Mostly standard architecture and easy to use.- Low cost design and development tool- Deterministic, uniform delays and predictable

timing.

Disadvantages :

- Low to moderate density- Low utilization of internal resources- Inflexible architecture.


Outline

Introduction to PLD

Why CPLD?

Why FPGA?

Comparison of FPGA & CPLD

Gate array Design





Why FPGA? FPGA stands for Field Programmable Gate

Array More Gate count to support complex logic CKT It does not contain AND and OR planes. They have - Logic blocks arranged in 2-D. - Routing channels, programmable

switches. Mostly LUT are there to implement logic. LUTs of various sizes can be created, they are

limited by number of inputs.


Structure of FPGA


FPGAAdvantage:----

- Ideal for customized design

- High complexity , density and reliability

- Low cost, power consumption, small physical size

- Fast time to market

Disadvantage:----

- High NRE cost, long delay in design and testing


FPGA (Field Programmable Gate Array)

What are the limitations of FPGA? Existence of programmable switches. Of course they provide programmable

feature to user but, they consume lot of real estate on the chip.

They make reduce the speed of operation.


FPGA Generic Flow Design Entry:– Create your design files using: • schematic editor or • hardware description language

(Verilog, VHDL)

Design “implementation” on FPGA:– Partition, place, and route to create

bit-stream file

Design verification:– Use Simulator to check function,– other software determines max

clock frequency.– Load onto FPGA device (cable

connects PC to development board) check operation at full speed in real

environment.


Outline

Introduction to PLD

Why CPLD?

Why FPGA?

Comparison of FPGA & CPLD

Gate array Design





Comparison Of CPLD & FPGA CPLD Logic gates are less in

number

Number of i/o pins are significantly higher

CPLD does not require any external memory store program

CPLD consume more power than FPGA

CPLD are smaller than FPGA

FPGA Several millions of gates

Number of i/o pins are less than CPLD

It requires one or more PROM depend on the size

FPGA consumes less power than CPLD

FPGA are larger than CPLD


Outline

Introduction of PLD

Why CPLD?

Why FPGA?

Comparison FPGA & CPLD

Gate array Design





Introduction to Gate Array Gate array is a prefabricated silicon chip

circuit.

Gate array is an IC chip on which gates are placed in a matrix form

Gate array contains basic cell as most important element. It contains (either CMOS,NAND,NOR or any other active device).


Gate Array


Gate Array Design

Gate array implementation requires a two step manufacturing process:

- The first phase, which is based on generic (standard) masks, results in an array of uncommitted transistors on each GA chip.

- These uncommitted chips can be stored for later customization, which is completed by defining the metal interconnects between transistors of arrays.


Switching matrix


Configurable Logic Block (CLB) Consist of look up tables

CLB is able to implement logic function of up to 9 variable

We can implement large function

Increases capacity and speed


FPGA Application

In DSP ,software defined radio, defense system, aerospace

Biomedical instruments, speech recognition

Computer hardware simulation Image controller Gate array prototyping Basically register intensive application


CPLD Application

Most common use in industry CPLDs can realize complex designs, such

as graphic controller,LAN Controller. High speed glue logic PAL integration System video controller Bus interfacing


Outline Introduction to PLD.

Why CPLD?

Why FPGA?

Comparison FPGA & CPLD

Gate array Design






Design Specification

Design Entry

Schematic HDL VHDL

Verilog

Finite State Machine

Verification

Gate Net list Creation / Synthesis

Functional Verification

Xilinx Device Implementation

Pld

Technology

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