Platinum Germanosilicide as Source/Drain Contacts in P-Channel Fin Field-Effect Transistors...

1458 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 7, JULY 2009

Platinum Germanosilicide as Source/Drain Contactsin P-Channel Fin Field-Effect Transistors (FinFETs)

Rinus Tek Po Lee, Student Member, IEEE, Dong Zhi Chi, and Yee-Chia Yeo, Member, IEEE

Abstract—In this paper, platinum germanosilicide (PtSiGe) wasinvestigated extensively as an alternative to nickel germanosili-cide (NiSiGe) for contact formation on silicon–germanium (SiGe)source/drain (S/D) stressors. We show that PtSiGe has superiorthermal and morphological stability as compared to NiSiGe. Ourresults further show that the formation of PtSiGe yields a low holebarrier height (ΦP

B) of 215 meV in a self-aligned process. Wealso demonstrated the integration of PtSiGe contacts in FinFETdevices. FinFETs with PtSiGe contacts achieve a 27% reductionin external resistance (REXT) compared to FinFETs with NiSiGecontacts. Statistical comparison reveals that the drive currentperformance is enhanced by 21% while maintaining comparablecontrol of short-channel effects. These results illustrate the poten-tial of forming contacts with low Schottky barrier heights usingPtSiGe in strained transistors with SiGe S/D stressors, therebyreducing REXT and extending transistor performance.

Index Terms—External resistance, FinFET, platinumgermanosilicide, Schottky barrier.

I. INTRODUCTION

P ERFORMANCE boosters such as strain engineering,hybrid-oriented substrates, and high-κ/metal gate are be-

ing actively explored and refined to enable continuous perfor-mance enhancement in future technology generations [1]–[3].Currently, silicon–germanium (Si1−yGey or SiGe) is used inthe source/drain (S/D) regions to strain the transistor chan-nel for enhanced drive current IDsat in p-channel field-effecttransistors (pFETs) [4]–[6]. The concentration of germanium(Ge) in the SiGe S/D stressors can be increased for scaling upcompressive strain level and IDsat enhancement [7]–[9]. Withthe adoption of SiGe S/D technology, nickel germanosilicide(NiSiGe) has been extensively investigated as the contact mate-rial [10]–[16].

The magnitude of IDsat is determined by the series combina-tion of the ON-state channel resistance and S/D resistance (i.e.,external resistance). The combination of these resistance com-ponents constitutes to the total resistance of a transistor givenby RTotal = RCh + REXT, where RTotal is the total resistance,

Manuscript received March 4, 2009; revised April 5, 2009. First publishedMay 29, 2009; current version published June 19, 2009. This work wassupported by the National Research Foundation (NRF), Singapore, through aresearch grant (Award NRF-RF2008-09). The review of this paper was arrangedby Editor V. R. Rao.

R. T. P. Lee and Y.-C. Yeo are with the Silicon Nano Device Laboratory,Department of Electrical and Computer Engineering, National University ofSingapore, Singapore 117576 (e-mail: [email protected]).

D. Z. Chi is with the Institute of Materials Research and Engineering,Singapore 119260.

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2009.2021351

RCh is the channel resistance, and REXT is a lumped com-ponent representing the external resistance (or S/D resistance).With the aggressive downscaling of gate length LG and the in-troduction of strain engineering, RCh has been reduced so dra-matically that REXT begins to dominate the total resistance ofa transistor. It is inevitable that REXT will ultimately limit theIDsat performance of a transistor, if solutions to alleviate the in-creasing dominance of REXT are not found. The major contrib-utors to the REXT in aggressively scaled transistors are the S/Dextension resistance under the sidewall spacer and the contactresistance between the diffusion region and silicide layer [17].

Contact resistance RCON depends on the contact resistivityρc, the sheet resistance Rsd of the S/D region, the width WC

and length LC of the contact hole, and the transfer length LT

(i.e., distance over which current travels from the diffusionregion into the contact) [18]. This is given by

RCON =√

ρcRsd

WC × tanh(

LC

LT

) . (1)

In the case of transistors with doped S/D junctions, the mech-anism for current flow through these ohmic contacts is viatunneling [19], and ρc is then given by

ρc ∝ e

(4π

√εsm∗h

[ΦB√

N

])(2)

where εs is the permittivity of the semiconductor, m∗ is theeffective mass of the semiconductor, h is the Planck’s constant,ΦB is the Schottky barrier height between the silicide andsemiconductor, and N is the active dopant concentration inthe semiconductor. It is intuitive from (2) that a change in ΦB

will result in a significant change in ρc due to the exponentialrelation between ρc and ΦB . Hence, various approaches havebeen proposed to reduce ΦB between the silicide and S/D junc-tion to reduce RCON [20]–[24], giving lower REXT and higherIDsat performance. For this reason, platinum silicide (PtSi) hasbeen widely investigated as S/D contacts to pFETs for its lowhole barrier height (ΦP

B) on p-type Si [25]–[27]. However, veryfew reports on the characteristics and compatibility of PtSiGeas contacts to pFETs with SiGe S/D stressors are currentlyavailable in the literature [28].

In this paper, we focus on the formation and integration ofPtSiGe as contacts to P-channel FinFETs (P-FinFETs) withSiGe S/D stressors. Our results show that PtSiGe has a low ΦP

B

of 215 meV on SiGe and is compatible with the FinFET processflow. We also explored, in detail, the impact of integrating Pt-SiGe contacts on transistor characteristics such as short-channeleffect (SCE) control, REXT, and drive current performance.

0018-9383/$25.00 © 2009 IEEE

LEE et al.: PLATINUM GERMANOSILICIDE AS S/D CONTACTS IN P-CHANNEL FinFETs 1459

Fig. 1. (a) Cross-sectional schematic showing the contact structure fabricatedin this paper for the extraction of Schottky barrier height. (b) Cross-sectionalTEM image revealing the formation of a uniform ∼18–20-nm-thick PtSiGelayer in this paper.

II. STRUCTURES AND PROCESSES FOR MATERIALS AND

ELECTRICAL CHARACTERIZATION

A. Substrate and Contact Structure Fabrication

Epitaxial Si1−yGey films were grown on silicon (Si) byultrahigh vacuum chemical vapor deposition. The Ge concen-tration was determined to be 26% in the as-grown Si1−yGey

(i.e., Si0.74Ge0.26) film by high-resolution X-ray diffraction(HRXRD). The epitaxial Si0.74Ge0.26 layer was grown to athickness of 100 nm on blanket p-type 8-in bulk (100) Si wafersfor material characterization.

In addition, two-terminal Schottky contact structures werefabricated to extract the Schottky barrier height of PtSiGeas shown in Fig. 1(a). The fabrication of the contact struc-tures began with thermal oxidation to form a 400-nm-thickSiO2 on p-type 8-in bulk (100) Si wafers. Photolithographyand wet etching were employed to define 80 μm × 80 μmsquare-shaped contact windows in the SiO2 isolation regions.A cyclic etch-and-growth process was used to selectively growa 100-nm-thick undoped Si0.74Ge0.26 layer in each contactwindow.

B. Metal Germanosilicide Process

The blanket Si0.74Ge0.26 films and contact structures weresubjected to a cleaning step consisting of a hydrofluoric acidsolution HF : H2O [1:100] dip for 60 s to remove native oxideprior to the germanosilicidation process. They were then loadedimmediately into an electron-beam evaporation system operat-ing at a base pressure of 1 × 10−7 torr. Platinum (Pt) films of10 nm thick were evaporated for the formation of PtSiGe. Forcontrol contact structures, a 10-nm-thick nickel (Ni) film wasdeposited for the formation of NiSiGe. The deposited metalfilms were annealed at 450 ◦C for 30 s in nitrogen to completethe germanosilicidation process. Unreacted Pt and Ni filmswere removed with a dilute aqua regia (AR) solution HCl :HNO3 : H2O [3:1:1] and sulphuric-peroxide solution H2SO4 :H2O2 [4:1], respectively. Fig. 1(b) shows a transmission elec-tron microscopy (TEM) image of PtSiGe formed on SiGe.Aluminum with a thickness of ∼200 nm was deposited on thebackside of the wafers as the second contact terminal for thetwo-terminal Schottky contact structures. All measurements inthis paper were performed at the germanosilicide level.

Fig. 2. Sheet resistance curves for NiSiGe and PtSiGe with similar thick-nesses as a function of annealing temperature. Films were annealed under thesame conditions. Interestingly, PtSiGe was also revealed to be more thermallystable than NiSiGe. This is evident from the absence of an abrupt increase inRS for PtSiGe in the temperature range of 600 ◦C–700 ◦C.

III. KEY CHARACTERISTICS OF

PLATINUM GERMANOSILICIDE

A. Sheet Resistance

Fig. 2 shows the sheet resistance (RS) curves for NiSiGe andPtSiGe films formed on undoped Si0.74Ge0.26 as a function ofthe annealing temperature. It is observed that stable RS valuesare achievable for both NiSiGe and PtSiGe in the temperaturerange of 400 ◦C–600 ◦C. This stable and low formation tem-perature range provides a practical germanosilicidation processwindow for device integration. The higher RS obtained forPtSiGe compared to NiSiGe is attributed to the difference inmetal resistivity for Pt and Ni [29]. However, it must be notedthat RCON contributes a larger fraction to REXT comparedto RS in state-of-the-art transistors [17] and therefore a moreimportant criterion in material selection to reduce REXT.

B. Surface Morphology

To further explore the thermal stability of NiSiGe and Pt-SiGe films formed at elevated annealing temperatures, scanningelectron microscopy (SEM) was used to examine the surfacemorphologies of these two films [Fig. 3(a)–(d)]. The SEMmicrographs revealed that surface morphologies for NiSiGe andPtSiGe films formed at 600 ◦C are similar with a continuoussurface layer [Fig. 3(a) and (c)]. This is consistent with RS mea-surements obtained in Fig. 2 at 600 ◦C for NiSiGe and PtSiGe.When the temperature was increased to 700 ◦C, the surfacemorphologies for both films became considerably different. ForNiSiGe formed at 700 ◦C, film coverage is compromised andno longer continuous due to agglomeration [Fig. 3(b)]. In con-trast, a continuous surface was preserved for PtSiGe formed at700 ◦C [Fig. 3(d)]. The combination of RS measurements andSEM imaging in this paper clearly shows that PtSiGe is supe-rior to NiSiGe in terms of thermal and surface morphologicalstability.

The major driving forces for the poor thermal stability ofNiSiGe are Ge outdiffusion from NiSiGe grain boundariesforming regions of SiGe with a higher Ge content [30] andfilm agglomeration. Ge outdiffusion from NiSiGe is driven by


Fig. 3. (a)–(d) Plan-view SEM micrographs showing the superior morpholog-ical stability of PtSiGe compared to NiSiGe when annealed at temperatures of600 ◦C and 700 ◦C.

the more favorable heat of formation for NiSi (−45 kJ/mol)compared to NiGe (−32 kJ/mol) [31]. The low melting pointof NiSiGe is one of the driving forces for the agglomerationof NiSiGe [32]. To understand the origins for the enhancedthermal and morphological stability of PtSiGe, Ge outdiffusionand agglomeration processes for PtSiGe were examined. Froma thermodynamics standpoint, the use of Pt should not influenceGe outdiffusion from a germanosilicide film. This is becausethe heat of formation for PtSi (−112 kJ/mol) [33] is lower thanthat of PtGe (−91 kJ/mol) [34].

The higher melting point of PtSiGe compared to NiSiGe[32] implies a slower dissociation of Pt–Si and Pt–Ge bonds.This reduces the diffusivities of Pt and Ge. As a result, grainboundary and surface/interface diffusions will be retarded andagglomeration is suppressed. This can be understood fromthe perspective of atomic bonding between atoms as a highermelting point is indicative of stronger atomic bonding whichinhibits grain boundary and surface and interface diffusions. Inaddition, the slower diffusivity of Pt compared to Ni also playsa role in the suppression of grain boundary grooving and growth[35]. The combination of these two mechanisms suppresses theagglomeration process, resulting in the superior thermal andmorphological stability of PtSiGe compared to NiSiGe.

C. XRD Analysis

From the results obtained by RS and SEM analysis, weselected PtSiGe formed at 450 ◦C for further analysis to as-sess its suitability for device integration. Phase identificationwas obtained by X-ray diffraction (XRD) analysis with a 2θinterval from 27◦ to 50◦ [Fig. 4(a)]. Several peaks are presentin the spectrum, indicating that the film formed at 450 ◦Cis polycrystalline. The spectrum further revealed that only asingle phase of mono PtSiGe exists at 450 ◦C. The peakswere identified with the PtSi(hkl) notation for simplification.However, it must be noted that Ge forms a solid solution withPtSiGe and SiGe. HRXRD was also used to examine the impact

Fig. 4. (a) XRD spectrum for PtSiGe formed at 450 ◦C for 30 s. Asingle mono PtSiGe phase was obtained. (b) HRXRD spectra for as-grownSi0.74Ge0.26 and PtSiGe/Si0.74Ge0.26 show a similar well-defined SiGesatellite peak indicating that strain and crystalline states were maintained withPt germanosilicidation.

of germanosilicidation on the underlying Si0.74Ge0.26 layer.The similar spectra obtained for the as-grown Si0.74Ge0.26 andthat of PtSiGe/Si0.74Ge0.26 shown in Fig. 4(b) imply that thestrain and crystalline states for Si0.74Ge0.26 remain the same.This implies that Pt germanosilicidation is compatible withSiGe S/D stressor technology.

D. Schottky Barrier Height Extraction

Based on the thermionic-emission theory, thecurrent–voltage (I–V ) characteristics of a Schottky junctioncan be expressed by I = AA∗T 2eq(φB/kT )[e(−qV/nkT ) − 1],where A is the junction area, A∗ is the Richardson constant forthermionic emission, T is the temperature, q is the electroniccharge, k is the Boltzmann’s constant, and n is the idealityfactor. The effective ΦB can be extracted from the slope ofthe Richardson plot with IS = AA∗T 2e(−qφB/kT ). Therefore,to determine ΦP

B for PtSiGe/p-SiGe contacts, temperature-dependent I–V curves were measured on contact structures byvarying the measurement temperature from 233 K to 313 K asshown in Fig. 5(a). ΦP

B was then extracted from the Richardsonplot shown in Fig. 5(b) and determined to be 215 meV. Theextracted ΦP

B for PtSiGe is comparable to the lowest obtainedto date for PtSi and represents a 34% reduction in ΦP

B withrespect to NiSiGe reported to be 326 meV [16].


Fig. 5. (a) Temperature-dependent current–voltage curves measured onPtSiGe/Si0.74Ge0.26 contacts. (b) Richardson plot of forward currents forPtSiGe/Si0.74Ge0.26 contacts at a forward voltage of 0.1 V. Linear line fittingwas performed on the data points to generate the “best fit” trend line to extractthe ΦP

B . Inset shows the contact structure used in the extraction of ΦPB .

Fig. 6. Evolution of PtSiGe sheet resistance values as a function of etchingtime in AR solution. The smooth surface morphology of PtSiGe is maintainedeven after a 5-min etch time in AR solution (inset). This implies that the etchrate of PtSiGe in AR is slower than 3.6 nm/min reported for Pt [36].

E. Selective Etching of Platinum

From a practical standpoint, a self-aligned process is impera-tive for forming contacts in the transistor S/D regions for deviceintegration. Owing to its noble metal properties, Pt is onlysoluble in the AR solution with an etch rate of 3.6 nm/min [36].The solubility of PtSiGe has to be lower (i.e., more stable) thanthat of Pt in the AR solution to achieve a self-aligned process.To check the stability of PtSiGe in the AR solution, sampleswere immersed in the AR solution for different etch times andanalyzed with SEM and RS measurements. Fig. 6 clearly showsthat RS for PtSiGe remains stable for up to 5 min in the ARsolution. An appreciable increase in RS is observed for samplesimmersed for longer than 5 min, suggestive of the onset ofPtSiGe removal (i.e., etching of the PtSiGe film by AR). Thedramatic increase in RS at 12-min etch time shown in Fig. 6indicates the complete removal of PtSiGe. We postulate thatthe surface of PtSiGe is oxidized from residual oxygen in theannealing ambient during germanosilicidation. This protectsthe PtSiGe film from the AR solution during etching. However,a prolong AR etch will ultimately remove the protective oxidelayer and result in the etching and subsequent removal of thePtSiGe film. This is similar to the mechanism reported byRand et al. for PtSi [37]. From these results, we established

Fig. 7. (a) Process flow showing the key steps used in the fabrication of P-FinFETs with NiSiGe and PtSiGe S/D contacts. (b) Plan-view SEM micrographshowing the complete removal of SiN stringers with an optimized overetch step.(c) Cross-sectional schematic view of the transistor structure and contacts usedin this paper.

that PtSiGe is stable in the AR solution when immersed for lessthan or equal to 5 min. This enables the selective removal ofPt to form PtSiGe contacts in a self-aligned process for deviceintegration. It should be noted that a germanidation process wasrecently proposed as an alternative selective etching approachfor Pt-based silicides to overcome the extreme reactivity of theAR solution [38].

IV. INTEGRATION AND CHARACTERISTICS OF P-FinFETsWITH PtSiGe CONTACTS

A. Transistor Fabrication

P-FinFETs were fabricated on 8-in (100) silicon-on-insulator(SOI) wafers in this paper for technology demonstration.Fig. 7(a) shows the process flow used in the fabrication of theP-FinFETs with SiGe S/D. The SOI wafers were first thinneddown to a thickness of ∼45 nm using thermal oxidation. TheSOI thickness determined the fin height Hfin of the P-FinFETs.The SOI layer then received a threshold voltage adjust implantcomprising phosphorus at 20 keV and 1 × 1013 cm−2, whichwas activated at 1000 ◦C for 30 s. A 60-nm-thick SiO2 hard-mask was deposited on the SOI wafers using plasma-enhancedchemical vapor deposition (PECVD). Optical lithography wasused to define resist lines down to 120 nm. A plasma resist-trimming process was then used to trim the resist lines down to∼40 nm, which defines the fin width WFin. These resist lineswere then transferred to the SiO2 hardmask with a reactiveion etch (RIE) process and subsequently transferred to theunderlying SOI with a highly selective RIE Si etching processto define the fins. A gate stack comprising 3-nm SiO2 gatedielectric and 100-nm-thick polycrystalline Si (poly-Si) wasused. The poly-Si gate was implanted with boron difluorideBF2 at an energy of 10 keV and a dose of 2 × 1014 cm−2

and activated at 950 ◦C for 15 s prior to gate patterning. Thegate patterning process involved a similar resist and hardmasktransfer steps to those used in the fin patterning process. S/D


Fig. 8. (a) Three-dimensional schematic view of the FinFET device with epitaxial SiGe and germanosilicide contacts. (b) Plan-view SEM of a FinFET withSi0.74Ge0.26 stressors formed on the S/D regions. The polycrystalline “beads” encompassing the top edge of the gate electrode were formed during the SiGeselective epitaxy process. Gate spacers were recessed with the overetch step while clearing the SiN stringers exposing the gate electrode during selective epitaxy.

extension implant with BF2 at an energy of 8 keV and a doseof 3 × 1013 cm−2 was performed after deposition of a 10-nm-thick PECVD SiO2 liner. A silicon nitride (SiN) spacer for-mation process with an optimized overetch step was used toensure the complete removal of SiN stringers around the S/Dareas [Fig. 7(b)]. This enables SiGe S/D stressors to be formedaround the fin for efficient stress coupling to the channel. RaisedS/D comprising 50-nm-thick epitaxial Si0.74Ge0.26 stressorswas then selectively grown. S/D formation was completed witha 10-keV BF2 implant with a dose of 2 × 1015 cm−2, whichwas activated at 1000 ◦C for 5 s. S/D germanosilicidation wascompleted with the same process used in the formation ofNiSiGe and PtSiGe detailed in Section II-B. Fig. 8(a) shows the3-D schematic for the FinFET device employed in this paper,and Fig. 8(b) shows the SEM plan view of a FinFET devicewith SiGe growth formed around the S/D regions.

B. Device Characterization of P-FinFETs WithPtSiGe Contacts

NiSiGe and PtSiGe contacts were integrated into P-FinFETsfor comparison and to evaluate the advantage(s) of forminglow ΦP

B contacts to P-channel devices. Fig. 9(a) shows theID–VG characteristics of a pair of closely matched devices withnominal LG = 50 nm. It should be noted that LG in this paperrefers to SEM measured values. The devices exhibit comparablesubthreshold swing (SS) of 100 mV/decade, drain-induced bar-rier lowering (DIBL) of 74 mV/V, and OFF-state leakage IOFF

of ∼ 1 × 10−7 A/μm. This implies that PtSiGe contacts formedin the SiGe S/D regions of P-FinFETs do not have a negativeimpact on transistor subthreshold characteristics. The ID–VD

family of curves for the same pair of transistors was measured atgate overdrives (VGS–VT ) of 0–1.2 V in steps of 0.2 V as shownin Fig. 9(b). It is obvious that P-FinFET integrated with PtSiGecontacts exhibits enhanced saturation drive current IDsat overthe control P-FinFET with NiSiGe contacts. To assess theenhancement of IDsat in a statistical manner, we plotted theIOFF–IDsat characteristics for P-FinFETs with NiSiGe andPtSiGe contacts in Fig. 10. It is clearly shown that for a fixedIOFF of 1 × 10−7 A/μm, P-FinFETs with PtSiGe contactsexhibit a 21% IDsat enhancement over P-FinFETs with NiSiGe

Fig. 9. (a) ID–VG characteristics of P-FinFET with NiSiGe and PtSiGecontacts. Comparable SS and DIBL were observed. (b) ID–VD family ofcurves shows substantial IDsat enhancement for FinFET device with PtSiGecontacts over the control FinFET device with NiSiGe contacts.

contacts. The IDsat enhancement in this paper is ascribed to thelower ΦP

B of PtSiGe compared to NiSiGe.We also plotted the distribution of SS and DIBL as a function

of LG for P-FinFETs with NiSiGe and PtSiGe contacts tocompare the SCEs. Fig. 11(a) and (b) shows the dependenceof SS and DIBL, respectively, on LG, where SS and DIBLvalues increase with decreasing LG as expected. The fitted linesserve as visual guides to show that SS and DIBL are not de-graded with the integration of PtSiGe S/D contacts. All devicesintegrated with PtSiGe S/D exhibit well-behaved transistor


Fig. 10. IOFF–IDsat characteristics comparing the drain currents of P-FinFETs with NiSiGe and PtSiGe contacts. A 21% improvement in IDsat at afixed IOFF of 1 × 10−7 A/μm was obtained. Linear line fitting was performedon the data points to generate the “best fit” trend lines. The 50-mV shift inIOFF and IDsat is to compensate for the nonoptimized threshold voltages inour devices.

Fig. 11. (a) Dependence of SS on LG. (b) Dependence of DIBL on LG. Fittedtrend line shows comparable SS and DIBL for the different LG.

characteristics. Even at LG of 40 nm, respectable values of SSand DIBL values were achieved for devices with PtSiGe S/D,which indicates that SCE control is not compromised.

The IDsat enhancement seen in the ID–VD curves andIOFF–IDsat characteristics for P-FinFET with PtSiGe S/D con-tacts is ascribed to the reduction in transistor REXT. We foundthat REXT’s for devices with NiSiGe and PtSiGe contacts are674 and 494 Ω · μm, respectively, as shown in Fig. 12. The27% reduction in device REXT with the use of PtSiGe contactsis attributed to the low ΦP

B of PtSiGe. This is explained from

Fig. 12. Plot of total resistance as a function of LG for P-FinFETs withNiSiGe and PtSiGe contacts. The similar slope (dR/dLG) obtained for theFinFET devices indicates that mobility is unchanged. The REXT for P-FinFETs with NiSiGe contacts as expected is higher than P-FinFETs withPtSiGe contacts. Linear line fitting was performed on the data points to generatethe “best fit” trend lines.

the perspective of ρC given in (2). Linear approximations wereused in the calculation of εs and m∗ values for Si0.74Ge0.26

in this paper. The calculated values for εs and m∗ are 12.966and 0.4354, respectively, for Si0.74Ge0.26. By using these val-ues and taking N = 1 × 1020 cm−3, we obtain ρC values of∼1.95 × 10−7 Ω · cm2 for NiSiGe and ∼3.58 × 10−8 Ω · cm2

for PtSiGe. This improvement in ρC is associated to the 111meV (or 34%) reduction in ΦP

B with the use of PtSiGe as ρC

exhibits an exponential dependence on ΦB . This is a goodapproximation for ρC in the FinFET devices as all other deviceparameters were kept constant in this paper. The improvementin ρC will lead to a proportional reduction in RCON as shownin (1), and RCON has been reported to be a major contributor toREXT. This ultimately results in the 27% reduction in FinFETdevice REXT shown in this paper.

V. CONCLUSION

In this paper, material and electrical characteristics of Pt-SiGe films have been investigated extensively to determine thesuitability of PtSiGe for device integration. It has been foundthat PtSiGe has a low ΦP

B of 215 meV with superior thermaland surface morphological stability compared to conventionalNiSiGe. We have demonstrated that forming low ΦP

B PtSiGecontacts in the S/D regions of FinFET devices achieves asignificant 27% reduction in device REXT. This leads to astatistical 21% enhancement in IDsat. We have further shownthat higher IDsat was achieved for PtSiGe contacts while main-taining comparable SS and DIBL as compared to devices withNiSiGe contacts. This paper illustrates the potential of forminglow ΦB contacts in S/D regions of a transistor to extend deviceperformance for future technology nodes.

REFERENCES

[1] S. Ito, H. Namba, K. Yamaguchi, T. Hirata, K. Ando, S. Koyama,S. Kuroki, N. Ikezawa, T. Suzuki, T. Saitoh, and T. Horiuchi, “Mechan-ical stress effect of etch-stop nitride and its impact on deep submicrontransistor design,” in IEDM Tech. Dig., 2000, pp. 247–250.

[2] M. Yang, V. Chan, S. H. Ku, M. Ieong, L. Shi, K. K. Chan, C. S. Murthy,R. T. Mo, H. S. Yang, E. A. Lehner, Y. Surpris, F. F. Jamin, P. Oldiges,Y. Zhang, B. N. To, J. R. Holt, S. E. Steen, M. P. Chudzik, D. M. Fried,


K. Bernstein, H. Zhu, C. Y. Sung, J. A. Ott, D. C. Boyd, and N. Rovedo,“On the integration of CMOS with hybrid crystal orientations,” in Symp.VLSI Technol., 2004, pp. 160–161.

[3] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost,M. Brazier, M. Buehler, A. Cappellani, R. Chau, C. H. Choi, G. Ding,K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hatttendorf,J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong,S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McIntyre,P. Moon, J. Neirynck, S. Pei, C. Parker, D. Parsons, C. Prasad, L. Pipes,M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Schifren, J. Sebastian,J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger,P. Vandervoorn, S. Williams, and K. Zawadzki, “A 45 nm logic technologywith high-k plus metal gate transistors, strained silicon, 9 Cu interconnectlayers, 193 nm dry patterning, and 100% Pb-free packaging,” in IEDMTech. Dig., 2007, pp. 247–250.

[4] T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass,T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry,A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith,K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume man-ufacturing logic technology featuring novel 45 nm gate length strainedsilicon CMOS transistors,” in IEDM Tech. Dig., 2003, pp. 978–980.

[5] D. Zhang, B. Y. Nguyen, T. White, B. Goolsby, T. Nguyen,V. Dhandapani, J. Hildreth, M. Foisy, V. Adams, Y. Shiho, A. Thean,D. Theodore, M. Canonico, S. Zollner, S. Bagchi, S. Murphy, R. Rai,J. Jiang, M. Jahanbani, R. Noble, M. Zavala, R. Cotton, D. Eades,S. Parsons, P. Montgomery, A. Martinez, B. Winstead, M. Mendicino,J. Cheek, J. Liu, P. Grudowski, N. Ranami, P. Tomasini, C. Arena,C. Werkhoven, H. Kirby, C. H. Chang, C. T. Lin, H. C. Tuan, Y. C. See,S. Venkatesan, V. Kolagunta, N. Cave, and J. Mogab, “Embedded SiGeS/D PMOS on thin body SOI substrate with drive current enhancement,”in Symp. VLSI Technol., 2005, pp. 26–27.

[6] K. M. Tan, T. Y. Liow, R. T. P. Lee, K. M. Hoe, C. H. Tung,N. Balasubramanian, G. S. Samudra, and Y. C. Yeo, “Strained P-channelFinFETs with extended Π-shaped silicon-germanium source and drainstressors,” IEEE Electron Device Lett., vol. 28, no. 10, pp. 905–908,Oct. 2007.

[7] K. J. Chui, K. W. Ang, A. Madan, H. Q. Wang, C. H. Tung,L. Y. Wong, Y. H. Wang, S. F. Choy, N. Balasubramanian, M. F. Li,G. Samudra, and Y. C. Yeo, “Source/drain germanium condensation forP-channel strained ultra-thin body transistors,” in IEDM Tech. Dig., 2005,pp. 499–502.

[8] F. Liu, H. S. Wong, K. W. Ang, M. Zhu, X. Wang, D. M. Y. Lai,P. C. Lim, B. L. H. Tan, S. Tripathy, S. A. Oh, G. S. Samudra,N. Balasubramanian, and Y. C. Yeo, “A new source/drain germanium-enrichment process comprising Ge deposition and laser-induced localmelting and recrystallization for P-FET performance enhancement,” inSymp. VLSI Technol., 2008, pp. 21–22.

[9] Y.-C. Yeo and J. Sun, “Finite element study of strain distribution intransistor with silicon-germanium source and drain regions,” Appl. Phys.Lett., vol. 86, no. 2, p. 023 103, Jan. 2005.

[10] K. L. Pey, W. K. Choi, S. Chattopadhyay, H. B. Zhao,E. A. Fitzgerald, D. A. Antoniadis, and P. S. Lee, “Thermal reaction ofnickel and Si0.75Ge0.25 alloy,” J. Vac. Sci. Technol. A, Vac. Surf. Films,vol. 20, no. 6, pp. 1903–1910, Nov. 2002.

[11] J. Liu and M. C. Ozturk, “Nickel germanosilicide contacts formed onheavily boron doped Si1−xGex source/drain junctions for nanoscaleCMOS,” IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1535–1540,Jul. 2005.

[12] M. C. Ozturk, J. Liu, and H. X. Mo, “Low resisivity nickel ger-manosilicide contacts to ultra-shallow Si1−xGex source/drain junctionsfor nanoscale CMOS,” in IEDM Tech. Dig., 2003, pp. 497–500.

[13] T. Jarmar, J. Seger, F. Ericson, D. Mangelinck, U. Smith, andS. L. Zhang, “Morphological and phase stability of nickel-germanosilicideon Si1−xGex under thermal stress,” J. Appl. Phys., vol. 92, no. 12,pp. 7193–7199, Dec. 2002.

[14] L. J. Jin, K. L. Pey, W. K. Choi, E. A. Fitzgerald, D. A. Antoniadis,A. J. Pitera, M. L. Lee, and C. H. Tung, “Highly oriented Ni(Pd)SiGeformation at 400 ◦C,” J. Appl. Phys., vol. 97, no. 10, p. 104 917,May 2005.

[15] L. J. Jin, K. L. Pey, W. K. Choi, E. A. Fitzgerald, D. A. Antoniadis,A. J. Pitera, M. L. Lee, D. Z. Chi, M. A. Rahman, T. Osipowicz, andC. H. Tung, “Effect of Pt on agglomeration and Ge out diffusion in Ni(Pt)germanosilicide,” J. Appl. Phys., vol. 98, no. 3, p. 033 520, Aug. 2005.

[16] R. T. P. Lee, K. M. Tan, A. E. J. Lim, T. Y. Liow, G. S. Samudra,D. Z. Chi, and Y. C. Yeo, “P-channel tri-gate FinFETs featuring Ni1−yPtySiGe source/drain contacts for enhanced drive current performance,”IEEE Electron Device Lett., vol. 29, no. 5, pp. 438–441, May 2008.

[17] S. D. Kim, C. M. Park, and J. C. S. Woo, “Advanced model and analysis ofseries resistance for CMOS scaling into nanometer regime. II. Quantita-tive analysis,” IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 467–472,Mar. 2002.

[18] D. B. Scott, W. R. Hunter, and H. Schichijo, “A transmission linemodel for silicided diffusions: Impact on the performance of VLSIcircuits,” IEEE Trans. Electron Devices, vol. ED-29, no. 4, pp. 651–661,Apr. 1982.

[19] C. M. Osburn and K. R. Bellur, “Low parasitic resistance contacts forscaled ULSI devices,” Thin Solid Films, vol. 332, no. 1/2, pp. 428–436,Nov. 1998.

[20] A. Kinoshita, Y. Tsuchiya, A. Yagishita, K. Uchida, and J. Koga, “Solutionfor high-performance Schottky-source/drain MOSFETs: Schottky barrierheight engineering with dopant segregation technique,” in Symp. VLSITechnol., 2004, pp. 168–169.

[21] R. T. P. Lee, T. Y. Liow, K. M. Tan, A. E. J. Lim, H. S. Wong, P. C. Lim,D. M. Y. Lai, G. Q. Lo, C. H. Tung, G. Samudra, D. Z. Chi, and Y. C. Yeo,“Novel nickel-alloy silicides for source/drain contact resistance reductionin N-channel multiple-gate transistors with sub-35 nm gate length,” inIEDM Tech. Dig., 2006, pp. 602–605.

[22] H. S. Wong, L. Chan, G. Samudra, and Y. C. Yeo, “Effective Schottkybarrier height reduction using sulfur or selenium at the NiSi/n-Si(100)interface for low resistance contacts,” IEEE Electron Device Lett., vol. 28,no. 12, pp. 1102–1104, Dec. 2007.

[23] R. T. P. Lee, A. T. Y. Koh, F. Y. Liu, W. W. Fang, T. Y. Liow, K. M.Tan, P. C. Lim, A. E. Lim, M. Zhu, K. M. Hoe, C. H. Tung, G. Q. Lo,X. Wang, D. K. Y. Low, G. S. Samudra, D. Z. Chi, and Y. C. Yeo, “Routeto low parasitic resistance in MuGFETs with silicon-carbon source/drain:Integration of novel low barrier Ni(M)Si:C metal silicides and pulsed laserannealing,” in IEDM Tech. Dig., 2007, pp. 685–688.

[24] Y. Nishi, Y. Tsuchiya, A. Kinoshita, T. Yamauchi, and J. Koga, “Interfacialsegregation of metal at NiSi/Si junction for novel dual silicide technol-ogy,” in IEDM Tech. Dig., 2007, pp. 135–138.

[25] S. Zollner, P. Grudowski, A. Thean, D. Jawarani, G. Karve, T. White,S. Bolton, H. Desjardins, M. Chowdhury, K. Chang, M. Jahanbani,R. Noble, L. Lovejoy, M. Rossow, D. Denning, D. Goedeke, S. Filipiak,R. Garcia, M. Raymond, V. Dhandapani, D. Zhang, L. Kang, P. Crabtree,X. Zhu, M. L. Kottke, R. Gregory, P. Fejes, X. D. Wang, D. Theodore,W. J. Taylor, and B. Y. Nguyen, “Dual silicide SOI CMOS integrationwith low-resistance PtSi PMOS contacts,” in Proc. Int. SOI Conf., 2007,pp. 65–66.

[26] G. Larrieu, E. Dubois, R. Valentin, N. Breil, F. Danneville, G. Dambrine,J. P. Raskin, and J. C. Pesant, “Low temperature implementation ofdopant-segregated band-edge metallic S/D junctions in thin-body SOI p-MOSFETs,” in IEDM Tech. Dig., 2007, pp. 147–150.

[27] Z. J. Qiu, Z. Zhang, M. Ostling, and S. L. Zhang, “A comparative studyof two different schemes to dopant segregation at NiSi/Si and PtSi/Siinterfaces for Schottky barrier height lowering,” IEEE Trans. ElectronDevice, vol. 55, no. 1, pp. 396–403, Jan. 2008.

[28] C. Demeurisse, P. Verheyen, K. Opsomer, C. Vrancken, P. Absil, andA. Lauwers, “Thermal stability of NiPt- and Pt-silicide contacts onSiGe source/drain,” Microelectron. Eng., vol. 84, no. 11, pp. 2547–2551,Nov. 2007.

[29] D. R. Lide, Handbook of Chemistry and Physics, 84th ed. Boca Raton,FL: CRC Press, 2003.

[30] H. B. Yao, M. Bouville, D. Z. Chi, H. P. Sun, X. Q. Pan, D. J. Srolovitz,and D. Mangelinck, “Interplay between grain boundary grooving, stress,and dealloying in the agglomeration of NiSi1−xGex films,” Electrochem.Solid-State Lett., vol. 10, no. 2, pp. H53–H55, Dec. 2007.

[31] F. R. Deboer, R. Boon, W. C. Mattens, A. R. Miedema, and A. K. Niessen,Cohesion in Metals: Transition Metal Alloys. Amsterdam,The Netherlands: North Holland, 1988.

[32] S. L. Zhang, “Nickel-based contact metallization for SiGe MOSFETs:Progress and challenges,” Microelectron. Eng., vol. 70, no. 2–4, pp. 174–185, Nov. 2003.

[33] R. Pretorius, “Prediction of silicide formation and stability usingheats of formation,” Thin Solid Films, vol. 290/291, pp. 477–484,Dec. 1996.

[34] W. G. Jung and O. J. Kleppa, “Standard polar enthalpies of formation ofHf3Ge2, MeGe (Me = Ir, Pt) and Pt2Ge,” J. Alloy Compounds, vol. 176,pp. 301–308, 1991.

[35] M. Bouville, D. Z. Chi, and D. J. Srolovitz, “Grain-boundary groovingand agglomeration of alloy thin films with a slow-diffusing species,” Phys.Rev. Lett., vol. 98, no. 8, p. 085 503, Feb. 2007.

[36] K. R. William, K. Gupta, and M. Wasilik, “Etch rates for micromachiningprocessing: Part II,” J. Microelectromech. Syst., vol. 12, no. 6, pp. 761–778, Dec. 2003.


[37] M. J. Rand and J. F. Roberts, “Observations on the formation and etch-ing of platinum silicide,” Appl. Phys. Lett., vol. 24, no. 2, pp. 49–51,Feb. 1974.

[38] N. Breil, E. Dubois, A. Halimaoui, A. Pouydebasque, A. Laszcz,J. Ratakcak, G. Larrieu, and T. Skotnicki, “Integration of PtSi in p-typeMOSFETs using a sacrificial low-temperature germanidation process,”IEEE Electron Device Lett., vol. 29, no. 2, pp. 152–154, Feb. 2008.

Rinus Tek Po Lee (S’06) received the B.S. degree inelectrical engineering and the M.S. degree in appliedphysics from the National University of Singapore(NUS), Singapore, where he is currently workingtoward the Ph.D. degree in electrical engineering,with research focus on parasitic resistance scaling inmultiple-gate nanoscale transistors, with Prof. Y.-C.Yeo and Dr. D. Z. Chi.

He was with the Agency of Science Technologyand Research, Institute of Materials Research andEngineering, Singapore, where he worked on the

development of advanced process technologies for contact metallization. Since2005, he has been with the Silicon Nano Device Laboratory, Departmentof Electrical and Computer Engineering, NUS. His current research interestsinclude device physics and process technology integration for the multiple-gatetransistor architecture. After receiving his Ph.D.degree, he will join the BOSCHAsia Pacific Research and Technology Center, Singapore.

Mr. Lee received the Marubun Research Promotion Foundation Grant forthe 2006 Solid State Devices and Materials Conference, Yokohama, Japan. In2007, he received the gold award at the Taiwan Semiconductor ManufacturingCompany (TSMC) Outstanding Student Research Award Ceremony. He wasthe recipient of the first prize for outstanding performance in the 2008 TSMCinternship program.

Dong Zhi Chi received the B.S. degree fromJilin University, Changchun, China, in 1984, theM.S. degree in inorganic nonmetallic materials fromShanghai Institute of Ceramics, Chinese Academyof Science, Beijing, China, in 1987, and the Ph.D.degree from The Pennsylvania State University,University Park, in 1998.

From 1987 to 1992, he was with Shanghai Instituteof Ceramics, working on amorphous semiconductorthin films and their applications in photovoltaic de-vices and laser printers. From 1990 to 1991, he was

a Visiting Scholar with the James Franck Institute, University of Chicago,Chicago, Illinois. After obtaining the Ph.D. degree, he joined the Institute ofMaterials Research and Engineering (IMRE), under the Agency for Science,Technology, and Research (A∗STAR), Singapore. Currently, he is a SeniorScientist and Head of materials growth group in IMRE, carrying out researchon various electronic thin films and their applications to nanoscale devices,including silicides/germanides for CMOS application, ultralow-k dielectricsthin films and their integration, thin film thermodynamics and kinetics, sili-con/germanium and silicide/germanide nanowires and devices, and semicon-ducting silicides for Si-based optoelectronics and solar cells. On these topics,he has authored/coauthored more than 100 publications in international journalsand over 60 proceeding-papers/presentations at international conferences.

Yee-Chia Yeo (S’98–M’02) received the B.Eng.(first class honors) and M. Eng. degrees in elec-trical engineering from the National University ofSingapore (NUS), Singapore, and the M.S. and Ph.D.degrees in electrical engineering and computer sci-ences from the University of California, Berkeley.

He was with the British Telecommunications Lab-oratories, U.K., working on optoelectronic devices,and with Berkeley, working on CMOS technology.From 2001 to 2003, he was with Taiwan Semicon-ductor Manufacturing Company (TSMC), working

on exploratory transistor technologies. He is currently an Assistant Professorof electrical and computer engineering with NUS and a Research ProgramManager with the Agency for Science, Technology, and Research (A∗STAR),Singapore. His research interests include strained-channel transistors, high-mobility devices, contact resistance reduction technologies, and devices withreduced subthreshold swing. He has authored or coauthored 300 journals andconference papers, and a book chapter. He is the holder of 76 U.S. patents.

Dr. Yeo served on the IEDM Sub-Committee on CMOS Devices from 2005to 2006. He received the 1995 IEE Prize from the Institution of ElectricalEngineers, U.K., the 1996 Lee Kuan Yew Gold Medal, the 1996 Institutionof Engineers Singapore Gold Medal, 1997–2001 NUS Overseas GraduateScholarship Award, the 2001 IEEE Electron Devices Society Graduate StudentFellowship Award, the 2002 IEEE Paul Rappaport Award, and 2003 TSMC In-vention Awards. In 2006, he received the Singapore Young Scientist Award andthe Singapore Youth Award in Science and Technology. In 2008, he receiveda National Research Foundation Fellowship and a NUS Young ResearcherAward.

Platinum Germanosilicide as Source/Drain Contacts in P-Channel Fin Field-Effect Transistors...

Documents

Transcript of Platinum Germanosilicide as Source/Drain Contacts in P-Channel Fin Field-Effect Transistors...