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Product Description

Ordering Information

Typical Applications

Features

Functional Block Diagram RF Micro Devices, Inc.7625 Thorndike RoadGreensboro, NC 27409, USA

Tel (336) 664 1233Fax (336) 664 0454

http://www.rfmd.com

Optimum Technology Matching® AppliedSi BJT GaAs MESFETGaAs HBT

Si Bi-CMOS SiGe HBT Si CMOS

2018 23

Prescaler128/129 or

64/65

PhaseDetector &

Charge Pump

24

14

12

15

RE

SN

TR

+

LOO

PF

LT

OSC SEL

RE

SN

TR

-

8TX OUT

13

GainControl

167 13 2

Ref.Select

OS

CB

1

OS

CE

OS

CB

2

VR

EF

P

PRESCL OUT

MOD CTRL

DIV CTRL

MO

DIN

LVL

AD

J

RF2512UHF TRANSMITTER

• Single- or Dual-Channel LO Source

• FM/FSK Transmitter

• Wireless Data Transmitters

• 433/868/915MHz ISM Band Systems

• Wireless Security Systems

The RF2512 is a monolithic integrated circuit intended foruse as a low-cost frequency synthesizer and transmitter.The device is provided in a 24 pin SSOP package and isdesigned to provide a phased locked frequency sourcefor use in local oscillator or transmitter applications. Thechip can be used in FM or FSK applications in the U.S.915MHz ISM band and European 433MHz or 868MHzISM band. The integrated VCO, dual-modulus/dual-divide(128/129 or 64/65) prescaler, and reference oscillatorrequire only the addition of an external crystal to providea complete phase-locked oscillator. A second referenceoscillator is available to support two channel applications.

• Fully Integrated PLL Circuit

• 15mW Output Power at 433MHz

• 2.7V to 5.0V Supply Voltage

• Low Current and Power Down Capability

• 300MHz to 1000MHz Frequency Range

• Narrowband and Wideband FM

RF2512 UHF TransmitterRF2512 PCBA-L Fully Assembled Evaluation Board, 433MHzRF2512 PCBA-M Fully Assembled Evaluation Board, 868MHzRF2512 PCBA-H Fully Assembled Evaluation Board, 915MHz

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1

0.0500.016

0.00980.0075

0.24400.2284

0.025

0.0120.008

0.06880.0532

0.1570.150 0.0098

0.0040

0.3440.337

Package Style: SSOP-24

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Absolute Maximum RatingsParameter Rating Unit

Supply Voltage -0.5 to +5.5 VDC

Power Down Voltage (VPD) -0.5 to VCC V

Operating Ambient Temperature -40 to +85 °CStorage Temperature -40 to +150 °C

ParameterSpecification

Unit ConditionMin. Typ. Max.

Overall T=25 °C, VCC=3.6V, Freq=915MHz

Frequency Range 300 to 1000 MHzModulation FM/FSKModulation Frequency 2 MHzMaximum FM Deviation 200 kHz Dependent upon Supply VoltagePLL and PrescalerPrescaler Divide Ratio 64/65 or 128/129PLL Lock TIme 4/PLL BW ms The PLL lock time, from power up, is set

externally by the bandwidth of the loop filter.PLL Phase Noise -80 dBc/Hz 10kHz Offset, 10kHz loop bandwidth

-100 dBc/Hz 100kHz Offset, 10kHz loop bandwidthReference Frequency 17 MHzMax Crystal RS TBD 100 ΩCharge Pump Current -40 +40 µATransmit SectionMaximum Power Level +7 +12 dBm Freq=433MHz

+6 dBm Freq=915MHzPower Control Range 15 dBPower Control Sensitivity 10 dB/VAntenna Port Impedance 50 Ω TX ENABL=“1”Antenna Port VSWR 1.5:1 TX ModeModulation Input Impedance 4 kΩHarmonics -23 dBcSpurious dBc Compliant to Part 15.249 and I-ETS 300 220Power Down ControlLogic Controls “ON” 2.0 V Voltage supplied to the input; device is “ON”Logic Controls “OFF” 1.0 V Voltage supplied to the input; device is “OFF”Control Input Impedance 25 kΩTurn On Time 5+4/PLL

BWms From Change in OSC SEL,7.075MHz XTAL

Turn Off Time TBD ms From Change in OSC SEL,7.075MHz XTALPower SupplyVoltage 3.6 V Specifications

2.7 to 5.0 V Operating limitsCurrent Consumption 28 mA TX Mode, LVL ADJ=3.6V

10 mA TX Mode, LVL ADJ=0V8 mA PLL Only

1 µA LVL ADJ=0V, PLL ENABL=0V,TX ENABL=0V, OSC SEL=0V

Caution! ESD sensitive device.

RF Micro Devices believes the furnished information is correct and accurateat the time of this printing. However, RF Micro Devices reserves the right tomake changes to its products without notice. RF Micro Devices does notassume responsibility for the use of the described product(s).

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Pin Function Description Interface Schematic1 OSC B2 This pin is connected directly to the reference oscillator transistor base.

The intended reference oscillator configuration is a modified Colpitts.An appropriate capacitor as chosen by the customer should be con-nected between pin 1 and pin 2.

2 OSC E This pin is connected directly to the emitter of the reference oscillatortransistor. An appropriate capacitor as chosen by the customer shouldbe connected from this pin to ground.

See pin 1.

3 OSC B1 This pin is connected directly to the reference oscillator transistor base.The intended reference oscillator configuration is a modified Colpitts.An appropriate capacitor as chosen by the customer should be con-nected between pin 3 and pin 2.

See pin 1.

4 PLL ENABL This pin is used to power up or down the VCO and PLL. A logic high(PLL ENABL>2.0V) powers up the VCO and PLL electronics. A logiclow (PLL ENABL<1.0V) powers down the PLL and VCO.

5 GND1 Ground connection for the PA buffer amp. Keep traces physically shortand connect immediately to ground plane for best performance.

6 VCC3 This pin is used to supply DC bias to the transmitter PA. A RF bypasscapacitor should be connected directly to this pin and returned toground. A 100pF capacitor is recommended for 915MHz applications.A 220pF capacitor is recommended for 433MHz applications.

7 LVL ADJ This pin is used to vary the transmitter output power. An output leveladjustment range greater than 12dB is provided through analog volt-age control of this pin. DC current of the transmitter power amp ia alsoreduced with output power. This pin MUST be low when the transmitteris disabled.

8 TX OUT RF output pin for the transmitter electronics. TX OUT output impedanceis a low impedance when the transmitter is enabled. TX OUT is a highimpedance when the transmitter is disabled.

9 GND2 Ground connection for the Tx PA functions. Keep traces physicallyshort and connect immediately to ground plane for best performance.

10 VCC1 This pin is used to supply DC bias to the PA buffer amp. A RF bypasscapacitor should be connected directly to this pin and returned toground. A 100pF capacitor is recommended for 915MHz applications.A 220pF capacitor is recommended for 433MHz applications.

11 TX ENABL Enables the transmitter circuits. TX ENABL>2.0V powers up all trans-mitter functions. TX ENABL<1.0V turns off all transmitter functionsexcept the PLL functions.

12 PRESCLOUT

Dual-modulus/Dual-divide prescaler output. The output can be inter-faced to an external PLL IC for additional flexibility in frequency pro-gramming.

13 VREF P Bias voltage reference pin for bypassing the prescaler and phasedetector. The bypass capacitor should be of appropriate size to providefiltering of the reference crystal frequency and be connected directly tothis pin.

OSC E

OSC B1 OSC B2

50 kΩPLL ENABL

400 4 kΩ

LVL ADJ40 kΩ

TX OUT

20

VCC

40 kΩ

20 kΩTX ENABL

PRESCLOUT

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Pin Function Description Interface Schematic14 MOD CTRL This pin is used to select the prescaler modulus. A logic “high” selects

64 or 128 for the prescaler divisor. A logic “low” selects 65 or 129 forthe prescaler divisor.

15 DIV CTRL This pin is used to select the desired prescaler divisor. A logic “high”selects the 64/65 divisor. A logic low selects the 128/129 divisor.

16 MOD IN FM analog or digital modulation can be imparted to the VCO throughthis pin. The VCO varies in accordance to the voltage level presentedto this pin. To set the deviation to a desired level, a voltage divider refer-enced to Vcc is the recommended. Because the modulation varactorsare part of the resonator tank, the deviation is slightly dependent uponthe components used in the external tank.

See pin 18.

17 VCC2 This pin is used to is supply DC bias to the VCO, prescaler, and PLL.

18 RESNTR- The RESNTR pins are used to supply DC voltage to the VCO, as wellas to tune the center frequency of the VCO. Equal value inductorsshould be connected to this pin and pin 20.

19 NC Not internally connected.

20 RESNTR+ See pin 18. See pin 18.

21 GND3 GND is the ground shared on chip by the VCO, prescaler, and PLLelectronics. Keep traces physically short and connect immediately toground plane for best performance.

22 NC Not internally connected.

23 LOOP FLT Output of the charge pump. An RC network from this pin to ground isused to establish the PLL bandwidth.

24 OSC SEL A logic high (OSC SEL>2.0V) applied to this pin powers on referenceoscillator 2 and powers down reference oscillator 1. A logic low (OSCSEL<1.0V) applied to this pin powers on reference oscillator 1 andpowers down reference oscillator 2.

ESD This diode structure is used to provide electrostatic discharge protec-tion to 3kV using the Human body model. The following pins are pro-tected: 1-3, 9, 10, 12-15, 17, 21, 23.

MOD CTL

DIV CTL

RESNTR-RESNTR+

4 kΩMOD IN

LOOP FLT

VCC

VCC

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RF2512 Theory of Operation

IntroductionThe RF2512 is a low cost FM/FSK UHF transmitterdesigned for applications operating within the fre-quency range of 300MHz to 1000MHz. In particular, itis intended for 315/433/868MHz band systems, remotekeyless entry systems, and FCC Part 15.231 periodictransmitters. It can also be used as a single- or dual-channel local oscillator signal source. The integratedVCO, phase detector, prescaler, and reference oscilla-tor require only the addition of an external crystal toprovide a complete phase-locked loop.

The RF2512 is provided in a 24-pin SSOP-24 packageand is designed to operate from a supply voltage rang-ing from 2.2V to 5.0V, accommodating designs usingthree NiCd battery cells, two AAA flashlight cells, or alithium button battery. The device is capable of provid-ing up to 15mW output power into a 50Ω load(+11.8dBm) and is intended to comply with FCCrequirements for unlicensed remote control transmit-ters.

RF2512 Functional BlocksA PLL consists of a reference oscillator, a phase detec-tor, a loop filter, a voltage controlled oscillator (VCO),and a programmable divider in the feedback path. TheRF2512 includes all of these internally except for theloop filter and the reference oscillator's crystal and twofeedback capacitors.

The reference oscillators are Colpitts type oscillators.Pin 1 (OSC B2), pin 2 (OSC E), and pin 3 (OSC B1)provide connections to the internal transistors that areused as the reference oscillators. The Colpitts configu-ration is a low parts count topology with reliable perfor-mance and reasonable phase noise. Alternatively, anexternal signal could be injected into the base of eithertransistor. The drive level should, in either case, bearound 500mVPP. This level prevents overdriving thedevice and keeps the phase noise and reference spursto a minimum.

The user sets which oscillator is operational by settingpin 24 (OSC SEL) either high or low. This allows theimplementation of two channel systems.

The prescaler divides the Voltage Controlled Oscilla-tor (VCO) frequency down by either 64/65 or 128/129,using a series of flip-flops, depending upon the logiclevel present at pin 15 (DIV CTRL). A high logic levelwill select the 64/65 divisor. A low logic level will selectthe 128/129 divisor. This divided signal is then fed into

the phase detector where it is compared with the refer-ence frequency.

In addition to the DIV CTRL setting, one also sets theprescaler modulus by setting pin 14 (MOD CTRL)either high or low. A high logic level will select the 64/128 divisor. A low logic level will select the 65/129 divi-sor.

Pin 12 (PRESCL OUT) provides access to the pres-caler output. This is used for interfacing to an externalPLL IC.

The RF2512 contains an onboard phase detector andcharge pump. The phase detector compares thephase of the reference oscillator to the phase of theVCO. The phase detector is implemented using flip-flops in a topology referred to as either "digital phase/frequency detector" or "digital tri-state comparator".The circuit consists of two D flip-flops whose outputsare combined with a NAND gate which is then tied tothe reset on each flip-flop. The outputs of the flip-flopsare also connected to the charge pump. Each flip-flopoutput signal is a series of pulses whose frequency isrelated to the flip-flop input frequency.

When both inputs of the flip-flops are identical, the sig-nals are both frequency and phase locked. If they aredifferent, they will provide signals to the charge pumpwhich will either charge or discharge the loop filter orenter into a high impedance state. This is where thename "tri-state comparator" comes from.

The main benefit of this type of detector it's ability tocorrect for errors in both phase and frequency. Whenlocked, the detector uses phase error for correction.When unlocked, it will use the frequency error for cor-rection. This type of detector will lock under all condi-tions.

The prescaler and the phase detector bias voltage isbrought out through pin 13 (VREF P). This allowsbypassing of the of these two circuits to filter the refer-ence crystal frequency.

The charge pump consists of two transistors, one forcharging the loop filter and the other for dischargingthe loop filter. It's inputs are the outputs of the phasedetector flip-flops. Since there are two flip-flops, thereare four possible states. If both amplifier inputs are low,then the amplifier pair goes into a high impedancestate, maintaining the charge on the loop filter. The

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state where both inputs are high will not occur. Theother states are either charging or discharging the loopfilter. The loop filter integrates the pulses coming fromthe charge pump to create a control voltage for thevoltage controlled oscillator.

The voltage controlled oscillator (VCO) is a tuneddifferential amplifier with the bases and collectorscross coupled to provide positive feedback and a 360°phase shift. The tuned circuit is located in the collec-tors. It is comprised an external varactor, a capacitorand external inductors. The designer selects the induc-tors for the desired frequency of operation. Theseinductors also provide DC bias for the VCO. The outputof the VCO is buffered and applied to the prescaler cir-cuit, where it is divided down and compared to the ref-erence oscillator frequency.

The PLL and VCO circuitry can be enabled by settingapplying a "high" logic level to pin 4 (PLL ENABL).Conversely, the PLL and VCO circuitry will be turnedoff if the level is tied "low".

The transmit amplifier is a two stage amplifier con-sisting of a driver and an open collector final stage. It iscapable of providing 12dBm of output power into a50Ω load while operating from a 3.6V power supply.

The output power is adjustable by the setting of pin 7(LVL ADJ). This analog input allows the designer a12dB range of output power. As the LVL ADJ voltage isreduced, the output power and current consumptionare reduced. LVL ADJ must be low when the transmit-ter is disabled.

Additionally, the transmitter circuitry can be disabledentirely by applying a "low" logic level to pin 11 (TXENABL). During transmission, this pin should be tied"high". This pin controls all circuitry except for the PLLcircuitry.

During transmission the transmitter is enabled and theimpedance of the output pin, pin 8 (TX OUT), is low.When the transmitter is not enabled, the impedancebecomes high.

The RF2512 contains onboard band gap referencevoltage circuitry which provides a stable DC bias overvarying temperature and supply voltages.

Designing with the RF2512The reference oscillator is built around the onboardtransistor at pins 1, 2 and 3. The intended topology isof a Colpitts oscillator. The Colpitts oscillator is quitecommon and requires few external components, mak-

ing it ideal for low cost solutions. The topology of thistype of oscillator is as seen in the following figure.

This type of oscillator is a parallel resonant circuit for afundamental mode crystal. The transistor amplifier isan emitter follower and the voltage gain is developedby the tapped capacitor impedance transformer. Theseries combination of C1 and C2 act in parallel with theinput capacitance of the transistor to capacitively loadthe crystal.

The nominal capacitor values can be calculated withthe following equations.

and

The load capacitance is usually 32pF. The variable freqis the oscillator frequency in MHz. The frequency canbe adjusted by either changing C2 or by placing a vari-

able capacitor in series with the crystal. As an exam-ple, assume a desired frequency of 14MHz and a loadcapacitance of 32pF. C1=137.1pF and C2=41.7pF.

These capacitor values provide a starting point. Thedrive level of the oscillator should be checked by look-ing at the signal at pin 2 (OSC E). It has been foundthat the level at this pin should generally be around500mVPP or less. This will reduce the reference spur

levels and reduce noise from distortion. If this level ishigher than 500mVPP then decrease the value of C1.

The values of these capacitors are usually tweakedduring design to meet performance goals, such asminimizing the start-up time.

Additionally, by placing a variable capacitor in serieswith the crystal, one is able to adjust the frequency.This will also alter the drive level, so it should bechecked again.

An important part of the overall design is the voltagecontrolled oscillator. The VCO is configured as a dif-ferential amplifier. The VCO is tuned via the externalinductors, capacitor, and varactor. The varactor capaci-

VCC

C2

C1X1

C1

60 Cload⋅freqMHz

------------------------= C21

1Cload------------- 1

C1------–

--------------------------=

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tance is set by the loop filter output voltage through a4kΩ resistor.

To tune the VCO the designer only needs to calculatethe value of the inductors connected to pins 18 and 20(RESNTR- and RESNTR+). The inductor value isdetermined by the following equation.

In this equation, f is the desired operating frequencyand L is the value of the inductor required. The value Cis the amount of capacitance presented by the varac-tor, capacitor and parasitics. The factor of one-half isdue to the inductors being in each leg.

The setup of the VCO can be summarized as follows.First, open the loop. Next, get the VCO to run on thedesired frequency by selecting the proper inductor andcapacitor values. The capacitor value will need toinclude the varactor and circuit parasitics. After theVCO is running at the desired frequency, then set theVCO sensitivity.

The sensitivity is determined by connecting the controlvoltage input point to ground and noting the frequency.Then connect the same point to the supply and againnote the frequency. The difference between these twofrequencies divided by the supply voltage is the VCOsensitivity expressed in Hz/V. Increasing the inductorvalue while decreasing the capacitor value willincrease the sensitivity. Decreasing the inductor valuewhile increasing the capacitor value will lower the sen-sitivity.

When increasing or decreasing component values,make sure that the center frequency remains constant.Finally, close the loop.

External to the part, the designer needs to implement aloop filter to complete the PLL. The loop filter convertsthe output of the charge pump into a voltage that isused to control the VCO. Internally, the VCO is con-nected to the charge pump output through a 4kΩ resis-tor. The loop filter is then connected in parallel to thispoint at pin 23 (LOOP FLT). This limits the loop filtertopology to a second order filter usually consisting of ashunt capacitor and a shunt series RC. A passive filteris most common, as it is a low cost and low noisedesign. An additional pole could be used for reducingthe reference spurs, however there is not a way to addthe series resistor. This should not be a reason for con-cern however.

The schematic of the loop filter is

The transfer function is

where the time constants are defined as

and

The frequency at which unity gain occurs is given by

This is also the loop bandwidth.

If the phase margin (PM) and the loop bandwidth(ωLBW) are known, it is possible to calculate the time

constants. These are found using the equations

and

RESNTR-RESNTR+

LOOPFLT 4 kΩ

L L

L1

2 π f⋅ ⋅----------------

2

1

C---- 1

2---⋅ ⋅=

VCC

R2

C2

C1

VCOLoop Filter

Charge Pump

F s( ) R2

s τ2 1+⋅s τ2 s τ1 1+⋅( )⋅ ⋅------------------------------------------⋅=

τ2 R2 C2⋅= τ1 R2

C1 C2⋅C1 C2+-------------------⋅=

ωLBW1

τ1 τ2⋅-------------------=

τ1PM( )sec PM( )tan–

ωLBW--------------------------------------------------= τ2

1ω2

LBW τ1⋅--------------------------=

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With these known, it is then possible to determine thevalues of the filter components.

As an example, consider a loop bandwidth of 50kHz, aphase margin of 45°, a divide ratio of 64, a KVCO of

20MHz/V, and a KPD of 0.01592mA/2πrad. Time con-

stant τ1 is 1.31848µs, time constant τ2 is 7.68468µs,C1 is 131.15pF, C2 is 633.26pF, and R2 is 12.14kΩ.

In order to perform these calculations, one will need toknow the value of two constants, KVCO and KPD. KPD is

calculated by dividing the charge pump current by 2π.For the RF2512, the charge pump current is 40µA.KVCO is best found empirically as it will change with

frequency and board parasitics. By briefly connectingpin 23 (LOOP FLT) to VCC and then to ground, the fre-quency tuning range of the VCO can be seen. Dividingthe difference between these two frequencies by thedifference in the voltage gives KVCO in MHz/V.

The control lines provide an interface for connectingthe device to a microcontroller or other signal generat-ing mechanism. The designer can treat pin 16 (MODIN), pin 15 (DIV CTRL), pin 14 (MOD CTRL) and pin 7(LVL ADJ) as control pins whose voltage level can beset.

General RF bypassing techniques must be observedto get the best performance. Choose capacitors suchthat they are series resonant near the frequency ofoperation.

Board layout is always an area in which great caremust be taken. The board material and thickness areused in calculating the RF line widths. The use of viasfor connection to the ground plane allows one to con-nect to ground as close as possible to ground pins.When laying out the traces around the VCO, it is desir-able to keep the parasitics equal between the two legs.This will allow equal valued inductors to be used.

Pre-compliance testing should be performed duringthe design process. This can be done with a GTEM cellor at a compliance testing laboratory. It is recom-mended that pre-compliance testing be performed sothat there are no surprises during final compliancetesting. This will help keep the product developmentand release on schedule.

Working with a laboratory offers the benefit of years ofcompliance testing experience and familiarity with theregulatory issues. Also, the laboratory can often pro-vide feedback that will help the designer make theproduct compliant.

On the other hand, having a GTEM cell or an open airtest site locally offers the designer the ability to rapidlydetermine whether or not design changes impact theproduct's compliance. Set-up of an open air test siteand the associated calibration is not trivial. An alterna-tive is to use a GTEM test cell.

After the design has been completed and passes com-pliance testing, application will need to be made withthe respective regulatory bodies for the geographicregion in which the product will be operated to obtainfinal certifications.

ConclusionsThe RF2512 is an FM/FSK UHF transmitter that fea-tures a phase-locked output. This device is suitable foruse in a CFR Part 15.231 compliant product as well asa local oscillator signal source. Further, the RF2512 ispackaged in a low cost SSOP-24 plastic package andrequires few external parts, thus making it suitable forlow cost designs.

C1

τ1

τ2-----

KPD KVCO⋅

ω2LBW N⋅

-----------------------------1 ωLBW τ2⋅( )2

+

1 ωLBW τ1⋅( )2+

----------------------------------------⋅ ⋅=

C2 C1

τ2

τ1----- 1– ⋅=

R2

τ2

C2------=

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Pin Out1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

OSC B2

OSC E

OSC B1

PLL ENABL

GND1

VCC3

LVL ADJ

TX OUT

GND2

VCC1

TX ENABL

PRESCL OUT

OSC SEL

LOOP FLT

NC

GND3

RESNTR+

NC

RESNTR-

VCC2

MOD IN

DIV CTRL

MOD CTRL

VREF P

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Evaluation Board SchematicH (915MHz) and M (868MHz) Boards

(Download Bill of Materials from www.rfmd.com.)

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

PhaseDetector/

Charge Pump

Prescaler

RefSelect

GainControl

C3100 pF

C1100 pF

C2*100 pF

X1X2*

R5*0 Ω

PLL ON

C8100 pF

C74 pF

L18.2 nH

C64 pF

C180.1 uF

50 Ω µstripJ1RF OUT

VCC

LVL ADJ

C410 nF

C522 pF

VCC

C910 nF

C1022 pF

TX EN

R3*TBD

PRESC OUT

D1SMV

1233-011

C153 pF

L26.8 nH

L36.8 nH

L456 nH

R24.3 kΩ

C1210 nF

C1322 pF

C144.7 µF

C1647 nF

C174.7 nF

R1

OSC SEL

MOD CTL

DIV 64

50 Ω µstrip J2MOD IN

C110.1 µF

2512401A, 402B

M (868MHz)

H (915MHz)

Board

13.57734

7.15909

X1 (MHz)

13.41015

7.07549

X2 (MHz)

6.8

4.7

L2 (nH)

1.2

2.2

R1 (kΩ)

6.8

4.7

L3 (nH)

1

2

3

P4

CON3

P4-1 DIV 64

GND

P4-3 MOD CTL

P2-1 PRESC OUT

GND

P2-3 TX EN

1

2

3

P2

CON3

P1

1

2

3

CON3

P1-3 PLL ON

GND

P1-1 LVL ADJ

D2*D3*

R7*0 Ω

AUDIO

P3-1 AUDIO

GND

P3-3 OSCSLT

GND

P3-5 VCC

1

2

3

4

5

P3

CON5

C203-10 pF

R6*0 Ω

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Evaluation Board SchematicL (433MHz) Board

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

PhaseDetector/

Charge Pump

Prescaler

RefSelect

GainControl

C3100 pF

C1100 pF

C2*100 pF

X16.78 MHz

X2*6.612813

MHz

R5*0 Ω

PLL ON

C8100 pF

C78 pF

L222 nH

L122 nH

C615 pF

C180.1 uF

50 Ω µstripJ1RF OUT

VCC

LVL ADJ

C40.01 uF

C522 pF

C198 pF

VCC

C910 nF

C1022 pF

TX EN

R3*TBD

PRESC OUT

D1SMV

1233-011

C155 pF

L327 nH

L427 nH

L5220 nH

R24.3 kΩ

C1210 nF

C1322 pF

C144.7 µF

C1647 nF

C174.7 nF

R12 kΩ

OSC SEL

MOD CTL

DIV 64

50 Ω µstrip J2MOD IN

C110.1 µF

2512400A

P1

1

2

3

CON3

P1-3 PLL ON

GND

P1-1 LVL ADJ

P2-3 TX EN

GND

P2-1 PRESC OUT1

2

3

CON3

P2

P4-1 DIV 64

GND

P4-3 MOD CTL

1

2

3

CON3

P4

1

2

3

4

5

P3

CON5

P3-1 AUDIO

P3-3 OSCSLT

GND

P3-5 VCC

GNDR6*0 Ω

C203-10 pF

D2*D3*

R7*0 Ω

AUDIO

*Denotes optional. These parts are not normally populated.

11-22

RF2512

Rev B9 010509

11

TR

AN

SC

EIV

ER

S

Evaluation Board Layout 433MHzBoard Size 1.5” x 1.5”

Evaluation Board Layout 868MHzBoard Size 1.5” x 1.5”

Evaluation Board Layout 915MHzBoard Size 1.5” x 1.5”

11-23

RF2512

Rev B9 010509

11

TR

AN

SC

EIV

ER

S

TX Power versus VCC

Level Adjust = VCC, 915 MHZ

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10.0

11.0

2.5 3.0 3.5 4.0 4.5 5.0

VCC (V)

TX

Pow

er(d

Bm

)

-40°C-15°C+10°C+35°C+60°C+85°C

ICC versus VCC

Level Adjust = VCC, 915 MHz

15.0

20.0

25.0

30.0

35.0

40.0

45.0

2.5 3.0 3.5 4.0 4.5 5.0

VCC (V)

I CC

(mA

)

-40°C-15°C+10°C+35°C+60°C+85°C

11-24

RF2512

Rev B9 010509

11

TR

AN

SC

EIV

ER

S