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Transcript of PIC24FJXXXGA1/GB1 Families Flash Programming …rf3 ra9 ra10 av dd rb8 rb9 rb10 rb11 v...
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2007-2014 Microchip Technology Inc. DS30009907C-page 1
PIC24FJXXXGA1/GB1 FAMILIES
1.0 DEVICE OVERVIEWThis document defines the programming specificationfor the PIC24FJXXXGA1/GB1 families of 16-bitmicrocontroller devices. This programming specificationis required only for those developing programmingsupport for the PIC24FJXXXGA1/GB1 families.Customers using only one of these devices should usedevelopment tools that already provide support fordevice programming.
This specification includes programming specificationsfor the following devices:
2.0 PROGRAMMING OVERVIEW OF THE PIC24FJXXXGA1/GB1 FAMILIES
There are two methods of programming thePIC24FJXXXGA1/GB1 families of devices discussed inthis programming specification. They are:
• In-Circuit Serial Programming™ (ICSP™)• Enhanced In-Circuit Serial Programming
(Enhanced ICSP)
The ICSP programming method is the most directmethod to program the device; however, it is also theslower of the two methods. It provides native, low-levelprogramming capability to erase, program and verifythe chip.
The Enhanced In-Circuit Serial Programming(Enhanced ICSP) protocol uses a faster method thattakes advantage of the Programming Executive (PE),as illustrated in Figure 2-1. The Programming Execu-tive provides all the necessary functionality to erase,program and verify the chip through a small commandset. The command set allows the programmer toprogram the PIC24FJXXXGA1/GB1 devices withouthaving to deal with the low-level programmingprotocols of the chip.
FIGURE 2-1: PROGRAMMING SYSTEM OVERVIEW FOR ENHANCED ICSP™
This specification is divided into major sections thatdescribe the programming methods independently.Section 4.0 “Device Programming – EnhancedICSP” describes the Enhanced In-Circuit Serial Pro-gramming (Enhanced ICSP) method. Section 3.0“Device Programming – ICSP” describes the In-CircuitSerial Programming method.
• PIC24FJ256GA106 • PIC24FJ256GB106• PIC24FJ256GA108 • PIC24FJ256GB108• PIC24FJ256GA110 • PIC24FJ256GB110• PIC24FJ192GA106 • PIC24FJ192GB106• PIC24FJ192GA108 • PIC24FJ192GB108• PIC24FJ192GA110 • PIC24FJ192GB110• PIC24FJ128GA106 • PIC24FJ128GB106• PIC24FJ128GA108 • PIC24FJ128GB108• PIC24FJ128GA110 • PIC24FJ128GB110• PIC24FJ64GA106 • PIC24FJ64GB106• PIC24FJ64GA108 • PIC24FJ64GB108• PIC24FJ64GA110 • PIC24FJ64GB110
PIC24FJXXXGA1/GB1
Programmer ProgrammingExecutive
On-Chip Memory
PIC24FJXXXGA1/GB1 Families Flash Programming Specification
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PIC24FJXXXGA1/GB1 FAMILIES
DS30009907C-page 2 2007-2014 Microchip Technology Inc.
2.1 Power RequirementsAll devices in the PIC24FJXXXGA1/GB1 families aredual voltage supply designs: one supply for the coreand peripherals, and another for the I/O pins. A regula-tor is provided on-chip to alleviate the need for twoexternal voltage supplies.
All PIC24FJXXXGA1/GB1 devices power their coredigital logic at a nominal 2.5V. To simplify systemdesign, all devices in the PIC24FJXXXGA1/GB1 fami-lies incorporate an on-chip regulator that allows thedevice to run its core logic from VDD.
The regulator provides power to the core from the otherVDD pins. A low-ESR capacitor (such as tantalum) mustbe connected to the VDDCORE pin (Table 2-1 andFigure 2-2). This helps to maintain the stability of theregulator. The specifications for core voltage and capac-itance are listed in Section 7.0 “AC/DC Characteristicsand Timing Requirements”.
2.2 Program Memory Write/Erase Requirements
The Flash program memory on PIC24FJXXXGA1/GB1devices has a specific write/erase requirement thatmust be adhered to for proper device operation. Therule is that any given word in memory must not be writ-ten more than twice before erasing the page in which itis located. Thus, the easiest way to conform to this ruleis to write all the data in a programming block withinone write cycle. The programming methods specified inthis specification comply with this requirement.
2.3 Pin DiagramsThe pin diagrams for the PIC24FJXXXGA1/GB1 fami-lies are shown in the following figures. The pins that arerequired for programming are listed in Table 2-1 andare shown in bold letters in the figures. Refer to theappropriate device data sheet for complete pindescriptions.
2.3.1 PGCx AND PGDx PIN PAIRSAll of the devices in the PIC24FJXXXGA1/GB1 fam-ilies have three separate pairs of programming pins,labeled as PGEC1/PGED1, PGEC2/PGED2 andPGEC3/PGED3. Any one of these pin pairs may beused for device programming by either ICSP orEnhanced ICSP. Unlike voltage supply and groundpins, it is not necessary to connect all three pin pairs toprogram the device. However, the programmingmethod must use both pins of the same pair.
FIGURE 2-2: CONNECTIONS FOR THE ON-CHIP REGULATOR
Note: Writing to a location multiple times withouterasing is not recommended.
VDDENVREG
VDDCORE/VCAP
VSS
PIC24FJXXXGA1/GB1
CEFC
3.3V
Regulator Enabled (ENVREG tied to VDD):
(10 F typ)
Note 1: These are typical operating voltages. Refer to Section 7.0 “AC/DC Characteristics and Timing Requirements” for the full operating ranges of VDD and VDDCORE.
VDDENVREG
VDDCORE/VCAP
VSS
PIC24FJXXXGA1/GB13.3V(1)2.5V(1)
Regulator Disabled (ENVREG tied to ground):
VDDENVREG
VDDCORE/VCAP
VSS
PIC24FJXXXGA1/GB12.5V(1)
Regulator Disabled (VDD tied to VDDCORE):
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PIC24FJXXXGA1/GB1 FAMILIES
TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING)
FIGURE 2-3: PIN DIAGRAMS
Pin NameDuring Programming
Pin Name Pin Type Pin Description
MCLR MCLR P Programming EnableENVREG ENVREG I Enable for On-Chip Voltage RegulatorVDD and AVDD(1) VDD P Power SupplyVSS and AVSS(1) VSS P GroundVDDCORE VDDCORE P Regulated Power Supply for CorePGECx PGCx I Programming Pin Pairs 1, 2 and 3: Serial Clock PGEDx PGDX I/O Programming Pin Pairs 1, 2 and 3: Serial Data Legend: I = Input, O = Output, P = PowerNote 1: All power supply and ground pins must be connected, including analog supplies (AVDD) and ground
(AVSS).
2345678910111213141516
4847
22
44
24 25 26 27 28 29 30 31 32
PIC24FJXXXGA106
1
4645
23
4342414039
RD
6R
D5
RD
4R
D3
RD
2R
D1
RE
4R
E3
RE
2R
E1
RF0
VCA
P/VD
DC
OR
E
RC13RD0
RD9RD8
RC15RC12VDDRG2
RF6RF2RF3
RG3
AVD
D
RB
8R
B9
RB
10R
B11
V DD
PGEC
2/A
N6/
RP6
/CN
24/R
B6
PGED
2/A
N7/
RP7
/CN
25/R
B7
RF5
RF4
RE5RE6RE7RG6
VDDPGEC3/AN5/RP18/C1INA/CN7/RB5PGED3/AN4/RP28/C1INB/CN6/RB4
RB3RB2
RG7RG8
PGEC1/AN1/RP1/VREF-/CN3/RB1PGED1/AN0/RP0/PMA6/VREF+/
RG9MCLR
RB
12R
B13
RB
14R
B15
RE
0R
F1
RD
7
VSS
VSS
VSS
ENVR
EG
63 62 61 5960 58 57 56 5455 53 52 51 4950
3837
34
3635
33
17 19 20 2118
AVSS
64
RC14
CN2/RB0
RD10RD11
64-Pin TQFP
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DS30009907C-page 4 2007-2014 Microchip Technology Inc.
FIGURE 2-4: PIN DIAGRAMS (CONTINUED)
80 79 78
20
23456789101112
1314
1516
6059
26
56
403928 29 30 31 32 33 34 35 36 37 38
PIC24FJXXXGA108
171819
1
7677
5857
27
5554535251
RD
5R
D4
RD
13R
D12
RD
3R
D2
RD
1
RE
2R
E1
RE
0R
G0
RE
4R
E3
RF0
VCA
P/VD
DC
OR
E
RC13RD0
RD9RD8RA15RA14
RC15RC12VDDRG2
RF6RF7RF8
RG3
RF2RF3
RA
10R
A9
AVD
D
RB
8R
B9
RB
10R
B11
VDD
RD
14R
D15
PGEC
2/A
N6/
RP6
/CN
24/R
B6
PGED
2/A
N7/
RP7
/CN
25/R
B7
RF5
RF4
RE5RE6RE7RC1RC3RG6
VDDCN66/RE8CN67/RE9
PGEC3/AN5/RP18/PGED3/AN4/RP28/
RB3RB2
RG7RG8
PGEC1/AN1/RP1/CN3/RB1PGED1/AN0/RP0/CN2/RB0
RG9MCLR
RB
12R
B13
RB
14R
B15
RG
1R
F1
RD
7R
D6
VSSVS
S
VSSEN
VREG
75 74 73 7172 70 69 68 6667 65 64 63 6162
5049
46
4847
4544434241
21 23 24 2522
AVSS
C1INA/CN7/RB5C1INB/CN6/RB4
RC14
RD10RD11
80-Pin TQFP
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PIC24FJXXXGA1/GB1 FAMILIES
FIGURE 2-5: PIN DIAGRAMS (CONTINUED)
100-Pin TQFP
9294 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78
20
2345678910111213141516
65646362616059
26
56
4544434241403928 29 30 31 32 33 34 35 36 37 38
PIC24FJXXXGA110
171819
2122
95
1
7677
72717069686766
757473
5857
2423
25
9698 979927 46 47 48 49 50
5554535251
100
RD
5R
D4
RD
13R
D12
RD
3R
D2
RD
1
RA
7R
A6
RE
2R
G13
RG
12R
G14
RE
1R
E0
RG
0
RE
4R
E3
RF0 VC
AP/
VDD
CO
RE
RC13RD0
RD9RD8RA15RA14
RC15RC12VDD
RG2
RF6RF7RF8
RG3
RF2RF3
VSS
RA
10R
A9
AVD
DAV
SSR
B8
RB
9R
B10
RB1
1
V DD
RF1
2R
F13
VSS
VDD
RD
15R
D14
PGEC
2/A
N6/
RP6
/CN
24/R
B6
PGED
2/A
N7/
RP7
/RC
V/C
N25
/RB
7
RF5
RF4
RE5RE6RE7RC1RC2RC3RC4RG6
VDDRA0RE8RE9
RB3RB2
RG7RG8
PGEC1/AN1/RP1/CN3/RB1PGED1/AN0/RP0/CN2/RB0
RG15VDD
RG9MCLR
RB
12R
B13
RB
14R
B15
RG
1R
F1
RD
7R
D6
RA5
RA3RA2
VSSVS
S
VSS
ENVR
EG
RA4R
A1
RC14
RD10RD11
PGEC3/AN5/RP18/VBUSON/C1INA/CN7/RB5PGED3/AN4/RP28/USBOEN/C1INB/CN6/RB4
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DS30009907C-page 6 2007-2014 Microchip Technology Inc.
FIGURE 2-6: PIN DIAGRAMS (CONTINUED)
2345678910111213141516
4847
22
44
24 25 26 27 28 29 30 31 32
PIC24FJXXXGB106
1
4645
23
4342414039
RD
6R
D5
RD
4R
D3
RD
2R
D1
RE
4R
E3
RE
2R
E1
RF0
VCA
P/VD
DC
OR
E
RC13RD0
RD9RD8
RC15RC12VDDD+/RG2
VUSBVBUSRF3
D-/RG3
AVD
D
RB
8R
B9
RB1
0R
B11
V DD
PGEC
2/A
N6/
RP6
/CN
24/R
B6
PGED
2/A
N7/
RP7
/RC
V/C
N25
/RB
7
RF5
RF4
RE5RE6RE7RG6
VDDPGEC3/AN5/RP18/VBUSON/C1INA/CN7/RB5PGED3/AN4/RP28/USBOEN/C1INB/CN6/RB4
RB3RB2
RG7RG8
PGEC1/AN1/RP1/VREF-/CN3/RB1PGED1/AN0/RP0/PMA6/VREF+/
RG9MCLR
RB1
2R
B13
RB1
4R
B15
RE
0R
F1
RD
7
VSS
VSS
VSS
ENVR
EG
63 62 61 5960 58 57 56 5455 53 52 51 4950
3837
34
3635
33
17 19 20 2118
AVSS
64
RC14
CN2/RB0
RD10RD11
64-Pin TQFP
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PIC24FJXXXGA1/GB1 FAMILIES
FIGURE 2-7: PIN DIAGRAMS (CONTINUED)
80 79 78
20
23456789101112
1314
1516
6059
26
56
403928 29 30 31 32 33 34 35 36 37 38
PIC24FJXXXGB108
171819
1
7677
5857
27
5554535251
RD
5R
D4
RD
13R
D12
RD
3R
D2
RD
1
RE
2R
E1
RE
0R
G0
RE
4R
E3
RF0
VCA
P/VD
DC
OR
E
RC13RD0
RD9RD8RA15RA14
RC15RC12VDDD+/RG2
VUSBVBUSRF8
D-/RG3
RF2RF3
RA
10R
A9
AVD
D
RB
8R
B9
RB
10R
B11
VDD
RD
14R
D15
PGEC
2/A
N6/
RP6
/CN
24/R
B6
PGED
2/A
N7/
RP7
/RC
V/C
N25
/RB
7
RF5
RF4
RE5RE6RE7RC1RC3RG6
VDDCN66/RE8CN67/RE9
PGEC3/AN5/RP18/VBUSON/PGED3/AN4/RP28/USBOEN/
RB3RB2
RG7RG8
PGEC1/AN1/RP1/CN3/RB1PGED1/AN0/RP0/CN2/RB0
RG9MCLR
RB
12R
B13
RB
14R
B15
RG
1R
F1
RD
7R
D6
VSS
VSS
VSS
ENVR
EG
75 74 73 7172 70 69 68 6667 65 64 63 6162
5049
46
4847
4544434241
21 23 24 2522
AVSS
C1INA/CN7/RB5C1INB/CN6/RB4
RC14
RD10RD11
80-Pin TQFP
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PIC24FJXXXGA1/GB1 FAMILIES
DS30009907C-page 8 2007-2014 Microchip Technology Inc.
FIGURE 2-8: PIN DIAGRAMS (CONTINUED)
9294 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78
20
2345678910111213141516
65646362616059
26
564544434241403928 29 30 31 32 33 34 35 36 37 38
PIC24FJXXXGB110
171819
2122
95
1
7677
72717069686766
757473
5857
2423
25
9698 979927 46 47 48 49 50
5554535251
100
RD
5R
D4
RD
13R
D12
RD
3R
D2
RD
1
RA7
RA6
RE2
RG
13R
G12
RG
14R
E1R
E0
RG
0
RE4
RE3
RF0 VC
AP/
VDD
CO
RE
RC13RD0
RD9RD8RA15RA14
RC15RC12VDD
D+/RG2
VUSBVBUSRF8
D-/RG3
RF2RF3
VSS
RA
10R
A9
AVD
DAV
SSR
B8
RB
9R
B10
RB
11
V DD
RF1
2R
F13
VSS
VDD
RD
15R
D14
PGEC
2/A
N6/
RP6
/CN
24/R
B6
PGED
2/A
N7/
RP7
/RC
V/C
N25
/RB
7
RF5
RF4
RE5RE6RE7RC1RC2RC3RC4RG6
VDDRA0RE8RE9
RB3RB2
RG7RG8
PGEC1/AN1/RP1/CN3/RB1PGED1/AN0/RP0/CN2/RB0
RG15VDD
RG9MCLR
RB
12R
B13
RB
14R
B15
RG
1R
F1
RD
7R
D6
RA5
RA3RA2
VSS
VSS
VSS
ENVR
EGRA4
RA
1
RC14
RD10RD11
PGEC3/AN5/RP18/VBUSON/C1INA/CN7/RB5PGED3/AN4/RP28/USBOEN/C1INB/CN6/RB4
100-Pin TQFP
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PIC24FJXXXGA1/GB1 FAMILIES
2.4 Memory MapThe program memory map extends from 000000h toFFFFFEh. Code storage is located at the base of thememory map and supports up to 87K instruction words(about 256 Kbytes). Table 2-2 shows the programmemory size, and number of erase and program blockspresent in each device variant. Each erase block, orpage, contains 512 instructions, and each programblock, or row, contains 64 instructions.
Locations, 800000h through 8007FEh, are reserved forexecutive code memory. This region stores the Pro-gramming Executive and the Debugging Executive.The Programming Executive is used for deviceprogramming and the Debugging Executive is used forin-circuit debugging. This region of memory can not beused to store user code.
The last three implemented program memory locationsare reserved for the Flash Configuration Words. Thereserved addresses are shown in Table 2-2.
Locations, FF0000h and FF0002h, are reserved for theDevice ID registers. These bits can be used by theprogrammer to identify what device type is beingprogrammed. They are described in Section 6.1“Device ID”. The Device ID registers read outnormally, even after code protection is applied.
Figure 2-9 shows the memory map for thePIC24FJXXXGA1/GB1 family variants.
TABLE 2-2: CODE MEMORY SIZE AND FLASH CONFIGURATION WORD LOCATIONS FOR PIC24FJXXXGA1/GB1 DEVICES
DeviceUser MemoryAddress Limit
(Instruction Words)
Write Blocks
Erase Blocks
Configuration Word Addresses
1 2 3
PIC24FJ64GA1XX00ABFEh (22K) 344 43 00ABFEh 00ABFCh 00ABFAh
PIC24FJ64GB1XXPIC24FJ128GA1XX
0157FEh (44K) 688 86 0157FEh 0157FCh 0157FAhPIC24FJ128GB1XXPIC24FJ192GA1XX
020BFEh (67K) 1048 131 020BFEh 020BFCh 020BFAPIC24FJ192GB1XXPIC24FJ256GA1XX
02ABFEh (87K) 1368 171 02ABFEh 02ABFCh 02ABFAPIC24FJ256GB1XX
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DS30009907C-page 10 2007-2014 Microchip Technology Inc.
FIGURE 2-9: PROGRAM MEMORY MAP
Use
r Mem
ory
Spac
e
000000h
Flash Configuration Words
Code Memory(1)
0XXX00h(1)0XXXFEh(1)
Con
figur
atio
n M
emor
ySp
ace
800000h
Device IDFEFFFEhFF0000h
FFFFFEh
Reserved
Reserved
8007FAh
800800h
Executive Code Memory
7FFFFEh
FF0002hFF0004hReserved
(2 x 16-bit)
Note 1: The size and address boundaries for user Flash code memory are device dependent. See Table 2-2 for details.
User Flash
(1024 x 24-bit)
8007F0hDiagnostic and Calibration Words
(8 x 24-bit)
0XXXFAh(1)0XXXF7h(1)
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PIC24FJXXXGA1/GB1 FAMILIES
3.0 DEVICE PROGRAMMING – ICSPICSP mode is a special programming protocol thatallows you to read and write to the memory of thePIC24FJXXXGA1/GB1 devices. The ICSP mode is themost direct method used to program the device; note,however, that Enhanced ICSP is faster. ICSP modealso has the ability to read the contents of executivememory to determine if the Programming Executive ispresent. This capability is accomplished by applyingcontrol codes and instructions, serially to the device,using pins, PGCx and PGDx.
In ICSP mode, the system clock is taken from thePGCx pin, regardless of the device’s Oscillator Config-uration bits. All instructions are shifted serially into aninternal buffer, then loaded into the Instruction Register(IR) and executed. No program fetching occurs frominternal memory. Instructions are fed in 24 bits at atime. PGDx is used to shift data in, and PGCx is usedas both the serial shift clock and the CPU executionclock.
3.1 Overview of the Programming Process
Figure 3-1 shows the high-level overview of theprogramming process. After entering ICSP mode, thefirst action is to Chip Erase the device. Next, the codememory is programmed, followed by the deviceConfiguration registers. Code memory (including theConfiguration registers) is then verified to ensure thatprogramming was successful. Then, program thecode-protect Configuration bits, if required.
FIGURE 3-1: HIGH-LEVEL ICSP™ PROGRAMMING FLOW
3.2 ICSP OperationUpon entry into ICSP mode, the CPU is Idle. Executionof the CPU is governed by an internal state machine. A4-bit control code is clocked in using PGCx and PGDx,and this control code is used to command the CPU (seeTable 3-1).
The SIX control code is used to send instructions to theCPU for execution and the REGOUT control code isused to read data out of the device via the VISI register.
TABLE 3-1: CPU CONTROL CODES IN ICSP™ MODE
Note: During ICSP operation, the operatingfrequency of PGCx must not exceed10 MHz.
4-Bit Control Code Mnemonic Description
0000b SIX Shift in 24-bit instruction and execute.
0001b REGOUT Shift out the VISI (0784h) register.
0010b-1111b N/A Reserved.
Start
Perform ChipErase
Program Memory
Verify Program
Done
Enter ICSP™
Program Configuration Bits
Verify Configuration Bits
Exit ICSP
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DS30009907C-page 12 2007-2014 Microchip Technology Inc.
3.2.1 SIX SERIAL INSTRUCTION EXECUTION
The SIX control code allows execution of PIC24F familyassembly instructions. When the SIX code is received,the CPU is suspended for 24 clock cycles, as the instruc-tion is then clocked into the internal buffer. Once theinstruction is shifted in, the state machine allows it to beexecuted over the next four PGC clock cycles. While thereceived instruction is executed, the state machinesimultaneously shifts in the next 4-bit command (seeFigure 3-2).
Coming out of Reset, the first 4-bit control code isalways forced to SIX and a forced NOP instruction isexecuted by the CPU. Five additional PGCx clocks areneeded on start-up, resulting in a 9-bit SIX commandinstead of the normal 4-bit SIX command.After the forced SIX is clocked in, ICSP operationresumes as normal. That is, the next 24 clock cyclesload the first instruction word to the CPU.
FIGURE 3-2: SIX SERIAL EXECUTION
3.2.1.1 Differences Between Execution of SIX and Normal Instructions
There are some differences between executing instruc-tions normally and using the SIX ICSP command. As aresult, the code examples in this specification may notmatch those for performing the same functions duringnormal device operation.
The important differences are:
• Two-word instructions require two SIX operations to clock in all the necessary data.
Examples of two-word instructions are GOTO andCALL.
• Two-cycle instructions require two SIX operations.The first SIX operation shifts in the instruction andbegins to execute it. A second SIX operation, whichshould shift in a NOP to avoid losing data, providesthe CPU clocks required to finish executing theinstruction.
Examples of two-cycle instructions are Table Readand Table Write instructions.
• The CPU does not automatically stall to account for pipeline changes.
A CPU stall occurs when an instruction modifies aregister that is used for Indirect Addressing by thefollowing instruction.
During normal operation, the CPU will automaticallyforce a NOP while the new data is read. When usingICSP, there is no automatic stall, so any indirect ref-erences to a recently modified register should bepreceded by a NOP.For example, the instructions, MOV #0x0,W0 andMOV [W0],W1, must have a NOP inserted betweenthem.
If a two-cycle instruction modifies a register that isused indirectly, it will require two following NOPs: oneto execute the second half of the instruction and asecond to stall the CPU to correct the pipeline.
Instructions, such as TBLWTL [W0++],[W1],should be followed by two NOPs.
• The device Program Counter (PC) continues to automatically increment during ICSP instruction execution, even though the Flash memory is not being used.
As a result, the PC may be incremented to point toinvalid memory locations. Invalid memory spacesinclude unimplemented Flash addresses and thevector space (locations 0x0 to 0x1FF).
If the PC points to these locations, the device willreset, possibly interrupting the ICSP operation. Toprevent this, instructions should be periodicallyexecuted to reset the PC to a safe space. The opti-mal method to accomplish this is to perform aGOTO 0x200.
Note: To account for this forced NOP, all examplecode in this specification begins with aNOP to ensure that no data is lost.
P4
2 3 1 2 3 23 24 1 2 3 4P1
PGCxP4A
PGDx
24-Bit Instruction FetchExecute PC – 1,
1 6
0 0 0 0
Fetch SIX
4 5 6 7 8 18 19 20 21 2217
LSB X X X X X X X X X X X X X X MSB
PGDx = Input
P2
P3P1B
P1A
7 8 9
0 0 0 00 0 0
Only forProgram
Memory Entry
Control Code
4 5
Execute 24-BitInstruction, FetchNext Control Code
0 0
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3.2.2 REGOUT SERIAL INSTRUCTION EXECUTION
The REGOUT control code allows for data to be extractedfrom the device in ICSP mode. It is used to clock the con-tents of the VISI register, out of the device, over thePGDx pin. After the REGOUT control code is received, theCPU is held Idle for 8 cycles. After these 8 cycles, anadditional 16 cycles are required to clock the data out(see Figure 3-3).
The REGOUT code is unique because the PGDx pin isan input when the control code is transmitted to thedevice. However, after the control code is processed,the PGDx pin becomes an output as the VISI register isshifted out.
FIGURE 3-3: REGOUT SERIAL EXECUTION
Note 1: After the contents of VISI are shifted out,the PIC24FJXXXGA1/GB1 devices main-tain PGDx as an output until the firstrising edge of the next clock is received.
2: Data changes on the falling edge andlatches on the rising edge of PGCx. Forall data transmissions, the LeastSignificant bit (LSb) is transmitted first.
1 2 3 4 1 2 7 8PGCx
P4
PGDx
PGDx = Input
Execute Previous Instruction, CPU Held in Idle Shift Out VISI Register
P5
PGDx = Output
1 2 3 1 2 3 4
P4A
11 13 15 161412
No Execution Takes Place,Fetch Next Control Code
0 0 0 0 0
PGDx = Input
MSb1 2 3 41
4 5 6
LSb 141312... 11100
Fetch REGOUT Control Code
0
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3.3 Entering ICSP ModeAs shown in Figure 3-4, entering ICSP Program/Verifymode requires three steps:
1. MCLR is briefly driven high, then low.2. A 32-bit key sequence is clocked into PGDx.3. MCLR is then driven high within a specified
period of time and held.
The programming voltage applied to MCLR is VIH, whichis essentially VDD in the case of PIC24FJXXXGA1/GB1devices. There is no minimum time requirement for hold-ing at VIH. After VIH is removed, an interval of at least P18must elapse before presenting the key sequence onPGDx.
The key sequence is a specific 32-bit pattern:‘0100 1101 0100 0011 0100 1000 0101 0001’(more easily remembered as 4D434851h in hexa-decimal). The device will enter Program/Verify mode onlyif the sequence is valid. The Most Significant bit (MSb) ofthe most significant nibble must be shifted in first.
Once the key sequence is complete, VIH must beapplied to MCLR and held at that level for as long asProgram/Verify mode is to be maintained. An interval ofat least time, P19 and P7, must elapse before present-ing data on PGDx. Signals appearing on PGCx beforeP7 has elapsed will not be interpreted as valid.
On successful entry, the program memory can beaccessed and programmed in serial fashion. While inICSP mode, all unused I/Os are placed in thehigh-impedance state.
FIGURE 3-4: ENTERING ICSP™ MODE
MCLR
PGDx
PGCx
VDD
P6P14
b31 b30 b29 b28 b27 b2 b1 b0b3...
Program/Verify Entry Code = 4D434851h
P1AP1B
P18
P19
0 1 0 0 0 0
P7VIH VIH
101
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3.4 Flash Memory Programming in ICSP Mode
3.4.1 PROGRAMMING OPERATIONSFlash memory write and erase operations are controlledby the NVMCON register. Programming is performed bysetting NVMCON to select the type of erase operation(Table 3-2) or write operation (Table 3-3) and initiatingthe programming by setting the WR control bit(NVMCON).
In ICSP mode, all programming operations areself-timed. There is an internal delay between the usersetting the WR control bit and the automatic clearingof the WR control bit when the programming operationis complete. Please refer to Section 7.0 “AC/DCCharacteristics and Timing Requirements” forinformation about the delays associated with variousprogramming operations.
TABLE 3-2: NVMCON ERASE OPERATIONS
TABLE 3-3: NVMCON WRITE OPERATIONS
3.4.2 STARTING AND STOPPING A PROGRAMMING CYCLE
The WR bit (NVMCON) is used to start an erase orwrite cycle. Setting the WR bit initiates the programmingcycle.
All erase and write cycles are self-timed. The WR bitshould be polled to determine if the erase or write cyclehas been completed. Starting a programming cycle isperformed as follows:
3.5 Erasing Program MemoryThe procedure for erasing program memory (all of codememory, data memory, executive memory andcode-protect bits) consists of setting NVMCON to404Fh and executing the programming cycle.
A Chip Erase can erase all of user memory or all of boththe user and configuration memory. A Table Writeinstruction should be executed prior to performing theChip Erase to select which sections are erased.
When this Table Write instruction is executed:
• If the TBLPAG register points to user space (is less than 0x80), the Chip Erase will erase only user memory.
• If TBLPAG points to configuration memory space (is greater than or equal to 0x80), the Chip Erase will erase both user and configuration memory.
If configuration memory space is erased, theinternal oscillator Calibration Word, located at0x807FE, will be erased. This location should bestored prior to performing a whole Chip Erase andrestored afterward to prevent internal oscillatorsfrom becoming uncalibrated.
Figure 3-5 shows the ICSP programming process forperforming a Chip Erase. This process includes theICSP command code, which must be transmitted (foreach instruction), Least Significant bit first, using thePGCx and PGDx pins (see Figure 3-2).
FIGURE 3-5: CHIP ERASE FLOW
NVMCONValue Erase Operation
404Fh Erases all code memory, executive memory and Configuration registers (does not erase Unit ID or Device ID registers).
4042h Erases a page of code memory or executive memory.
NVMCONValue Write Operation
4003h Writes a Configuration Word register.4001h Programs 1 row (64 instruction words) of
code memory or executive memory.
BSET NVMCON, #WR
Note: Program memory must be erased beforewriting any data to program memory.
Start
Done
Set the WR bit to Initiate Erase
Write 404Fh to NVMCON SFR
Delay P11 + P10 Time
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TABLE 3-4: SERIAL INSTRUCTION EXECUTION FOR CHIP ERASECommand
(Binary)Data(Hex) Description
Step 1: Exit the Reset vector.000000000000
000000040200000000
NOPGOTO 0x200NOP
Step 2: Set the NVMCON register to erase all program memory.00000000
2404FA883B0A
MOV #0x404F, W10MOV W10, NVMCON
Step 3: Set TBLPAG and perform dummy Table Write to select what portions of memory are erased.000000000000000000000000
200000880190200000BB0800000000000000
MOV #, W0MOV W0, TBLPAGMOV #0x0000, W0TBLWTL W0,[W0]NOPNOP
Step 4: Initiate the erase cycle.000000000000
A8E761000000000000
BSET NVMCON, #WR NOPNOP
Step 5: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.0000000000000000000000010000
040200000000803B02883C22000000
000000
GOTO 0x200 NOPMOV NVMCON, W2MOV W2, VISINOPClock out contents of the VISI register.NOP
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3.6 Writing Code MemoryThe procedure for writing code memory is the same asthe procedure for writing the Configuration registers,except that 64 instruction words are programmed at atime. To facilitate this operation, Working registers,W0:W5, are used as temporary holding registers for thedata to be programmed.
Table 3-5 shows the ICSP programming details, includ-ing the serial pattern with the ICSP command code,which must be transmitted, Least Significant bit first,using the PGCx and PGDx pins (see Figure 3-2).
In Step 1, the Reset vector is exited. In Step 2, theNVMCON register is initialized for programming a fullrow of code memory. In Step 3, the 24-bit starting des-tination address for programming is loaded into theTBLPAG register and W7 register. (The upper byte ofthe starting destination address is stored in TBLPAGand the lower 16 bits of the destination address arestored in W7.)
To minimize the programming time, a packed instructionformat is used (Figure 3-6).
In Step 4, four packed instruction words are stored inWorking registers, W0:W5, using the MOV instructionand the Read Pointer, W6, is initialized. The contents ofW0:W5 (holding the packed instruction word data) areshown in Figure 3-6.
In Step 5, eight TBLWT instructions are used to copy thedata from W0:W5 to the write latches of code memory.Since code memory is programmed, 64 instructionwords at a time, Steps 4 and 5 are repeated 16 times toload all the write latches (Step 6).
After the write latches are loaded, programming isinitiated by writing to the NVMCON register in Steps 7and 8. In Step 9, the internal PC is reset to 200h. Thisis a precautionary measure to prevent the PC fromincrementing into unimplemented memory when largedevices are being programmed. Lastly, in Step 10,Steps 3-9 are repeated until all of code memory isprogrammed.
FIGURE 3-6: PACKED INSTRUCTION WORDS IN W0:W5
15 8 7 0W0 LSW0W1 MSB1 MSB0W2 LSW1W3 LSW2W4 MSB3 MSB2W5 LSW3
TABLE 3-5: SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORYCommand(Binary)
Data(Hex) Description
Step 1: Exit the Reset vector.000000000000
000000040200000000
NOPGOTO 0x200NOP
Step 2: Set the NVMCON register to program 64 instruction words.00000000
24001A883B0A
MOV #0x4001, W10MOV W10, NVMCON
Step 3: Initialize the Write Pointer (W7) for the TBLWT instruction.000000000000
200xx08801902xxxx7
MOV #, W0MOV W0, TBLPAGMOV #, W7
Step 4: Load W0:W5 with the next 4 instruction words to program.000000000000000000000000
2xxxx02xxxx12xxxx22xxxx32xxxx42xxxx5
MOV #, W0MOV #, W1MOV #, W2MOV #, W3MOV #, W4MOV #, W5
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Step 5: Set the Read Pointer (W6) and load the (next set of) write latches.00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
EB0300000000BB0BB6000000000000BBDBB6000000000000BBEBB6000000000000BB1BB6000000000000BB0BB6000000000000BBDBB6000000000000BBEBB6000000000000BB1BB6000000000000
CLR W6NOPTBLWTL [W6++], [W7] NOPNOPTBLWTH.B [W6++], [W7++] NOPNOPTBLWTH.B [W6++], [++W7] NOPNOPTBLWTL [W6++], [W7++] NOP NOPTBLWTL [W6++], [W7] NOPNOPTBLWTH.B [W6++], [W7++] NOP NOPTBLWTH.B [W6++], [++W7] NOPNOPTBLWTL [W6++], [W7++] NOPNOP
Step 6: Repeat Steps 4 and 5, sixteen times, to load the write latches for 64 instructions. Step 7: Initiate the write cycle.
000000000000
A8E761000000000000
BSET NVMCON, #WR NOPNOP
Step 8: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.0000000000000000000000010000
040200000000803B02883C22000000
000000
GOTO 0x200 NOPMOV NVMCON, W2MOV W2, VISINOPClock out contents of the VISI register.NOP
Step 9: Reset the device internal PC.00000000
040200000000
GOTO 0x200 NOP
Step 10: Repeat Steps 3-9 until all code memory is programmed.
TABLE 3-5: SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY (CONTINUED)Command(Binary)
Data(Hex) Description
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FIGURE 3-7: PROGRAM CODE MEMORY FLOW
Start Write Sequence
Alllocations
done?
No
Done
Start
Yes
Load 2 Bytesto Write
Buffer at
Allbytes
written?No
Yes
and Poll for WR bitto be Cleared
N = 1LoopCount = 0
ConfigureDevice for
Writes
N = 1LoopCount =
LoopCount + 1
N = N + 1
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3.7 Writing Configuration WordsDevice configuration for PIC24FJXXXGA1/GB1 devicesis stored in Flash Configuration Words at the end of theuser space program memory, and in multiple registerConfiguration Words located in the test space. Theseregisters reflect values read at any Reset from programmemory locations. The values for the ConfigurationWords for the default device configurations are listed inTable 3-6.
The values can be changed only by programming thecontent of the corresponding Flash Configuration Wordand resetting the device. The Reset forces an automaticreload of the Flash stored configuration values bysequencing through the dedicated Flash ConfigurationWords and transferring the data into the Configurationregisters.
For the PIC24FJXXXGA1/GB1 families, certain Config-uration bits have default states that must always bemaintained to ensure device functionality, regardless ofthe settings of other Configuration bits. These bits andtheir values are listed in Table 3-7.
To change the values of the Flash Configuration Wordonce it has been programmed, the device must be ChipErased, as described in Section 3.5 “Erasing ProgramMemory”, and reprogrammed to the desired value. It isnot possible to program a ‘0’ to ‘1’, but they may beprogrammed from a ‘1’ to ‘0’ to enable code protection.
TABLE 3-6: DEFAULT CONFIGURATION REGISTER VALUES
TABLE 3-7: RESERVED CONFIGURATION BIT LOCATIONS
Table 3-8 shows the ICSP programming details for pro-gramming the Configuration Word locations, includingthe serial pattern with the ICSP command code whichmust be transmitted, Least Significant bit first, using thePGCx and PGDx pins (see Figure 3-2).
In Step 1, the Reset vector is exited. In Step 2, theNVMCON register is initialized for programming ofcode memory. In Step 3, the 24-bit starting destinationaddress for programming is loaded into the TBLPAGregister and W7 register.
The TBLPAG register must be loaded with thefollowing:
• 64-Kbyte devices: 00h• 128, 192 and 256-Kbyte devices: 01h
To verify the data by reading the Configuration Wordsafter performing the write in order, the code protectionbits initially should be programmed to a ‘1’ to ensurethat the verification can be performed properly. Afterverification is finished, the code protection bits can beprogrammed to a ‘0’ by using a word write to theappropriate Configuration Word.
Address Name Default Value
Last Word CW1 7FFFhLast Word – 2 CW2 F7FFhLast Word – 4 CW3 FFFFh
Bit Location Value
CW1 0CW1 1CW2 0CW2(1) 1Note 1: This bit is implemented as I2C2SEL on
PIC24FJXXXGA110 devices and should be programmed as required.
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TABLE 3-8: SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION REGISTERSCommand
(Binary)Data(Hex) Description
Step 1: Exit the Reset vector.000000000000
000000040200000000
NOPGOTO 0x200NOP
Step 2: Initialize the Write Pointer (W7) for the TBLWT instruction.0000 2xxxx7 MOV , W7
Step 3: Set the NVMCON register to program CW2.00000000
24003A883B0A
MOV #0x4003, W10MOV W10, NVMCON
Step 4: Initialize the TBLPAG register.00000000
200xx0880190
MOV , W0MOV W0, TBLPAG
Step 5: Load the Configuration register data to W6.0000 2xxxx6 MOV #, W6
Step 6: Write the Configuration register data to the write latch and increment the Write Pointer.0000000000000000
000000BB1B86000000000000
NOPTBLWTL W6, [W7++]NOPNOP
Step 7: Initiate the write cycle.000000000000
A8E761000000000000
BSET NVMCON, #WRNOPNOP
Step 8: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.0000000000000000000000010000
040200000000803B02883C22000000
000000
GOTO 0x200NOPMOV NVMCON, W2MOV W2, VISINOPClock out contents of the VISI register.NOP
Step 9: Reset the device internal PC.00000000
040200000000
GOTO 0x200NOP
Step 10: Repeat Steps 5-9 to write CW1.
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3.8 Reading Code MemoryReading from code memory is performed by executinga series of TBLRD instructions and clocking out the datausing the REGOUT command.Table 3-9 shows the ICSP programming details forreading code memory. In Step 1, the Reset vector isexited. In Step 2, the 24-bit starting source address forreading is loaded into the TBLPAG register and W6register. The upper byte of the starting source addressis stored in TBLPAG and the lower 16 bits of the sourceaddress are stored in W6.
To minimize the reading time, the packed instructionword format that was utilized for writing is also used forreading (see Figure 3-6). In Step 3, the Write Pointer,W7, is initialized. In Step 4, two instruction words areread from code memory and clocked out of the device,through the VISI register, using the REGOUT command.Step 4 is repeated until the desired amount of codememory is read.
TABLE 3-9: SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORYCommand
(Binary)Data(Hex) Description
Step 1: Exit the Reset vector.000000000000
000000040200000000
NOPGOTO 0x200NOP
Step 2: Initialize the TBLPAG register and the Read Pointer (W6) for the TBLRD instruction.000000000000
200xx08801902xxxx6
MOV #, W0MOV W0, TBLPAGMOV #, W6
Step 3: Initialize the Write Pointer (W7) to point to the VISI register.00000000
207847000000
MOV #VISI, W7 NOP
Step 4: Read and clock out the contents of the next two locations of code memory, through the VISI register, using the REGOUT command.
000000000000000100000000000000000000000000000001000000000000000000010000
BA0B96000000000000
000000BADBB6000000000000BAD3D6000000000000
000000BA0BB6000000000000
000000
TBLRDL [W6], [W7] NOPNOPClock out contents of VISI registerNOPTBLRDH.B [W6++], [W7++]NOPNOPTBLRDH.B [++W6], [W7--]NOPNOPClock out contents of VISI registerNOPTBLRDL [W6++], [W7]NOPNOPClock out contents of VISI registerNOP
Step 5: Repeat Step 4 until all desired code memory is read. Step 6: Reset the device internal PC.
00000000
040200000000
GOTO 0x200 NOP
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3.9 Reading Configuration WordsThe procedure for reading configuration memory issimilar to the procedure for reading code memory,except that 16-bit data words are read instead of 24-bitwords. Configuration Words are read, one register at atime.
Table 3-10 shows the ICSP programming details forreading the Configuration Words. Note that theTBLPAG register must be loaded with 00h for 64-Kbytedevices, 01h for 128-Kbyte devices, and 02h for192-Kbyte and 256-Kbyte devices (the upper byteaddress of configuration memory), and the ReadPointer, W6, is initialized to the lower 16 bits of theConfiguration Word location.
TABLE 3-10: SERIAL INSTRUCTION EXECUTION FOR READING ALL CONFIGURATION MEMORYCommand
(Binary)Data(Hex) Description
Step 1: Exit the Reset vector.000000000000
000000040200000000
NOPGOTO 0x200NOP
Step 2: Initialize the TBLPAG register, the Read Pointer (W6) and the Write Pointer (W7) for the TBLRD instruction.00000000000000000000
200xx08801902xxxx6207846000000
MOV , W0MOV W0, TBLPAGMOV , W6MOV #VISI, W7NOP
Step 3: Read the Configuration register and write it to the VISI register (located at 784h), and clock out the VISI register using the REGOUT command.
00000000000000010000
BA0BB6000000000000
000000
TBLRDL [W6++], [W7] NOP NOPClock out contents of VISI registerNOP
Step 4: Repeat Step 3 twice to read Configuration Word 2 and Configuration Word 1. Step 5: Reset the device internal PC.
00000000
040200000000
GOTO 0x200 NOP
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3.10 Verify Code Memory and Configuration Word
The verify step involves reading back the code memoryspace and comparing it against the copy held in theprogrammer’s buffer. The Configuration registers areverified with the rest of the code.
The verify process is shown in the flowchart inFigure 3-8. Memory reads occur a single byte at a time,so two bytes must be read to compare against the wordin the programmer’s buffer. Refer to Section 3.8“Reading Code Memory” for implementation detailsof reading code memory.
FIGURE 3-8: VERIFY CODE MEMORY FLOW
3.11 Reading the Application ID WordThe Application ID Word is stored at address,8007F0h, in executive code memory. To read thismemory location, you must use the SIX control code tomove this program memory location to the VISI regis-ter. Then, the REGOUT control code must be used toclock the contents of the VISI register out of the device.The corresponding control and instruction codes thatmust be serially transmitted to the device to performthis operation are shown in Table 3-11.
After the programmer has clocked out the ApplicationID Word, it must be inspected. If the Application ID hasthe value, CBh, the Programming Executive is residentin memory and the device can be programmed usingthe mechanism described in Section 4.0 “DeviceProgramming – Enhanced ICSP”. However, if theApplication ID has any other value, the ProgrammingExecutive is not resident in memory; it must be loadedto memory before the device can be programmed. Theprocedure for loading the Programming Executive tomemory is described in Section 5.4 “Programmingthe Programming Executive to Memory”.
3.12 Exiting ICSP ModeExiting Program/Verify mode is done by removing VIHfrom MCLR, as shown in Figure 3-9. The only require-ment for exit is that an interval, P16, should elapsebetween the last clock and program signals on PGCxand PGDx before removing VIH.
FIGURE 3-9: EXITING ICSP™ MODE
Note: Because the Configuration registersinclude the device code protection bit,code memory should be verified immedi-ately after writing if code protection isenabled. This is because the device willnot be readable or verifiable if a deviceReset occurs after the code-protect bit inCW1 has been cleared.
Read Low Byte
Read High Byte
DoesWord = Expect
Data?
Failure,ReportError
Allcode memory
verified?
No
Yes
No
Set TBLPTR = 0
Start
Yes
Done
with Post-Increment
with Post-Increment
MCLR
P16
PGDx
PGD = Input
PGCx
VDD
VIH
VIH
P17
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TABLE 3-11: SERIAL INSTRUCTION EXECUTION FOR READING THE APPLICATION ID WORDCommand
(Binary)Data(Hex) Description
Step 1: Exit the Reset vector.000000000000
000000040200000000
NOPGOTO 0x200NOP
Step 2: Initialize the TBLPAG register and the Read Pointer (W0) for the TBLRD instruction.00000000000000000000000000000000
200800880190207F00207841000000BA0890000000000000
MOV #0x80, W0 MOV W0, TBLPAGMOV #0x7F0, W0 MOV #VISI, W1 NOP TBLRDL [W0], [W1] NOPNOP
Step 3: Output the VISI register using the REGOUT command.00010000
000000
Clock out contents of the VISI registerNOP
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4.0 DEVICE PROGRAMMING – ENHANCED ICSP
This section discusses programming the devicethrough Enhanced ICSP and the Programming Execu-tive. The Programming Executive resides in executivememory (separate from code memory) and is executedwhen Enhanced ICSP Programming mode is entered.The Programming Executive provides the mechanismfor the programmer (host device) to program and verifythe PIC24FJXXXGA1/GB1 devices using a simplecommand set and communication protocol. There areseveral basic functions provided by the ProgrammingExecutive:
• Read Memory• Erase Memory• Program Memory• Blank Check• Read Executive Firmware Revision
The Programming Executive performs the low-leveltasks required for erasing, programming and verifyinga device. This allows the programmer to program thedevice by issuing the appropriate commands and data.Table 4-1 summarizes the commands. A detaileddescription for each command is provided inSection 5.2 “Programming Executive Commands”.
TABLE 4-1: COMMAND SET SUMMARY
The Programming Executive uses the device’s dataRAM for variable storage and program execution. Afterthe Programming Executive has run, no assumptionsshould be made about the contents of data RAM.
4.1 Overview of the Programming Process
Figure 4-1 shows the high-level overview of theprogramming process. After entering Enhanced ICSPmode, the Programming Executive is verified. Next, thedevice is erased. Then, the code memory isprogrammed, followed by the configuration locations.Code memory (including the Configuration registers) isthen verified to ensure that programming was successful.
After the Programming Executive has been verifiedin memory (or loaded if not present), thePIC24FJXXXGA1/GB1 families can be programmedusing the command set shown in Table 4-1.
FIGURE 4-1: HIGH-LEVEL ENHANCED ICSP™ PROGRAMMING FLOW
4.2 Confirming the Presence of the Programming Executive
Before programming can begin, the programmer mustconfirm that the Programming Executive is stored inexecutive memory. The procedure for this task isshown in Figure 4-2.
First, In-Circuit Serial Programming (ICSP) mode isentered. Then, the unique Application ID Word stored inexecutive memory is read. If the Programming Executiveis resident, the Application ID Word is CBh, which meansprogramming can resume as normal. However, if theApplication ID Word is not CBh, the ProgrammingExecutive must be programmed to executive codememory using the method described in Section 5.4“Programming the Programming Executive toMemory”. Section 3.0 “Device Programming – ICSP” describesthe ICSP programming method. Section 3.11 “Readingthe Application ID Word” describes the procedure forreading the Application ID Word in ICSP mode.
Command Description
SCHECK Sanity CheckREADC Read Device ID RegistersREADP Read Code Memory PROGP Program One Row of Code Memory
and VerifyPROGW Program One Word of Code Memory
and VerifyQBLANK Query if the Code Memory is BlankQVER Query the Software Version
Start
Done
Perform ChipErase
Program Memory
Verify Program
Enter Enhanced ICSP™
Program Configuration Bits
Verify Configuration Bits
Exit Enhanced ICSP
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FIGURE 4-2: CONFIRMING PRESENCE OF PROGRAMMING EXECUTIVE
4.3 Entering Enhanced ICSP ModeAs shown in Figure 4-3, entering Enhanced ICSPProgram/Verify mode requires three steps:
1. The MCLR pin is briefly driven high, then low.2. A 32-bit key sequence is clocked into PGDx.3. MCLR is then driven high within a specified
period of time and held.
The programming voltage applied to MCLR is VIH,which is essentially VDD in the case ofPIC24FJXXXGA1/GB1 devices. There is no minimumtime requirement for holding at VIH. After VIH isremoved, an interval of at least P18 must elapse beforepresenting the key sequence on PGDx.
The key sequence is a specific 32-bit pattern:‘0100 1101 0100 0011 0100 1000 0101 0000’(more easily remembered as 4D434850h in hexa-decimal format). The device will enter Program/Verifymode only if the key sequence is valid. The MostSignificant bit (MSb) of the most significant nibble mustbe shifted in first.
Once the key sequence is complete, VIH must beapplied to MCLR and held at that level for as long asProgram/Verify mode is to be maintained. An interval ofat least time, P19 and P7, must elapse before present-ing data on PGDx. Signals appearing on PGDx beforeP7 has elapsed will not be interpreted as valid.
On successful entry, the program memory can beaccessed and programmed in serial fashion. While inthe Program/Verify mode, all unused I/Os are placed inthe high-impedance state.
FIGURE 4-3: ENTERING ENHANCED ICSP™ MODE
Is
Start
Enter ICSP™ Mode
Application IDCBh?
Resident in Memory
Yes
No
Prog. Executive is
Application IDRead the
be ProgrammedProg. Executive must
from Address807F0h
Finish
MCLR
PGDx
PGCx
VDD
P6P14
b31 b30 b29 b28 b27 b2 b1 b0b3...
Program/Verify Entry Code = 4D434850h
P1AP1B
P18
P19
0 1 0 0 1 0 0 0 0
P7VIH VIH
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4.4 Blank CheckThe term, “Blank Check”, implies verifying that thedevice has been successfully erased and has noprogrammed memory locations. A blank or erasedmemory location is always read as ‘1’. The Device ID registers (FF0002h:FF0000h) can beignored by the Blank Check since this region storesdevice information that cannot be erased. The deviceConfiguration registers are also ignored by the BlankCheck. Additionally, all unimplemented memory spaceshould be ignored by the Blank Check.
The QBLANK command is used for the Blank Check. Itdetermines if the code memory is erased by testingthese memory regions. A ‘BLANK’ or ‘NOT BLANK’response is returned. If it is determined that the deviceis not blank, it must be erased before attempting toprogram the chip.
4.5 Code Memory Programming
4.5.1 PROGRAMMING METHODOLOGYCode memory is programmed with the PROGPcommand. PROGP programs one row of code memory,starting from the memory address specified in thecommand. The number of PROGP commands requiredto program a device depends on the number of writeblocks that must be programmed in the device.
A flowchart for programming the code memory of thePIC24FJXXXGA1/GB1 families is shown in Figure 4-4.In this example, all 87K instruction words of a256-Kbyte device are programmed. First, the numberof commands to send (called, ‘RemainingCmds’, in theflowchart) is set to 1368 and the destination address(called, ‘BaseAddress’) is set to ‘0’. Next, one writeblock in the device is programmed with a PROGPcommand. Each PROGP command contains data forone row of code memory of the device. After the firstcommand is processed successfully, ‘RemainingCmds’is decremented by 1 and compared with 0. Since thereare more PROGP commands to send, ‘BaseAddress’ isincremented by 80h to point to the next row of memory.
On the second PROGP command, the second row isprogrammed. This process is repeated until the entiredevice is programmed. No special handling must beperformed when a panel boundary is crossed.
FIGURE 4-4: FLOWCHART FOR PROGRAMMING CODE MEMORY
4.5.2 PROGRAMMING VERIFICATIONAfter code memory is programmed, the contents ofmemory can be verified to ensure that programmingwas successful. Verification requires code memory tobe read back and compared against the copy held inthe programmer’s buffer.
The READP command can be used to read back all ofthe programmed code memory.
Alternatively, you can have the programmer performthe verification after the entire device is programmedusing a checksum computation.
IsPROGP response
PASS?
AreRemainingCmds
0?
BaseAddress = 00hRemainingCmds = 1368
RemainingCmds =RemainingCmds – 1
BaseAddress =BaseAddress + 80h
No
No
Yes
Yes
Start
FailureReport Error
Send PROGPCommand to Program
BaseAddress
Finish
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4.6 Configuration Bits Programming
4.6.1 OVERVIEWThe PIC24FJXXXGA1/GB1 families have Configurationbits stored in the last three locations of implementedprogram memory (see Table 2-2 for locations). Thesebits can be set or cleared to select various device config-urations. There are three types of Configuration bits:system operation bits, code-protect bits and unit ID bits.The system operation bits determine the power-onsettings for system level components, such as theoscillator and Watchdog Timer. The code-protect bitsprevent program memory from being read and written.
The descriptions for the Configuration bits in the FlashConfiguration Words are shown in Table 4-2.
Note: Although not implemented with a specificfunction, some Configuration bit positionshave default states that must always bemaintained to ensure device functionality,regardless of the settings of other Config-uration bits. Refer to Table 3-7 for a list ofthese bit positions and their default states.
TABLE 4-2: PIC24FJXXXGA1/GB1 FAMILIES CONFIGURATION BITS DESCRIPTIONBit Field Register Description
DEBUG CW1 Background Debug Enable bit1 = Device will reset in User mode0 = Device will reset in Debug mode
DISUVREG(1) CW2 Internal USB 3.3V Regulator Disable bit1 = Regulator is disabled0 = Regulator is enabled
FCKSM CW2 Clock Switching Mode bits1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
FNOSC CW2 Initial Oscillator Source Selection bits111 = Internal Fast RC (FRCDIV) Oscillator with Postscaler110 = Reserved101 = Low-Power RC (LPRC) Oscillator100 = Secondary Oscillator (SOSC)011 = Primary Oscillator with PLL (XTPLL, HSPLL, ECPLL)010 = Primary Oscillator (XT, HS, EC) 001 = Internal Fast RC Oscillator with Postscaler and PLL (FRCPLL)000 = Fast RC (FRC) Oscillator
FWDTEN CW1 Watchdog Timer Enable bit1 = Watchdog Timer is always enabled (LPRC oscillator cannot be disabled;
clearing the SWDTEN bit in the RCON register will have no effect)0 = Watchdog Timer is enabled/disabled by user software (LPRC can be
disabled by clearing the SWDTEN bit in the RCON register)FWPSA CW1 Watchdog Timer Postscaler bit
1 = 1:1280 = 1:32
GCP CW1 General Segment Code-Protect bit1 = User program memory is not code-protected0 = User program memory is code-protected
GWRP CW1 General Segment Write-Protect bit1 = User program memory is not write-protected0 = User program memory is write-protected
Note 1: Available on PIC24FJXXXGB1XX devices only.2: Available on PIC24FJXXXGA110 devices only. On other devices, always maintain this bit as ‘1’.
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I2C2SEL(2) CW2 I2C2 Pin Select bit (PIC24FJXXXGA1XX devices only)1 = Uses SCL2/SDA2 pins for I2C™ Module 20 = Uses ASCL2/ASDA2 pins for I2C Module 2
ICS CW1 ICD Emulator Pin Placement Select bits11 = Emulator functions are shared with PGEC1/PGED110 = Emulator functions are shared with PGEC2/PGED201 = Emulator functions are shared with PGEC3/PGED300 = Reserved; do not use
IESO CW2 Internal External Switchover bit1 = Two-Speed Start-up is enabled0 = Two-Speed Start-up is disabled
IOL1WAY CW2 IOLOCK Bit One-Way Set Enable bit0 = The OSCCON bit can be set and cleared as needed
(provided an unlocking sequence is executed)1 = The OSCCON bit can only be set once (provided an
unlocking sequence is executed); once IOLOCK is set, this prevents anypossible future RP register changes
JTAGEN CW1 JTAG Enable bit1 = JTAG is enabled 0 = JTAG is disabled
OSCIOFNC CW2 OSC2 Pin Function bit (except in XT and HS modes)1 = OSC2 is a clock output0 = OSC2 is a general purpose digital I/O pin
PLLDIV(1) CW2 USB 96 MHz PLL Prescaler Select bits111 = Oscillator input divided by 12 (48 MHz input)110 = Oscillator input divided by 10 (40 MHz input)101 = Oscillator input divided by 6 (24 MHz input)100 = Oscillator input divided by 5 (20 MHz input)011 = Oscillator input divided by 4 (16 MHz input)010 = Oscillator input divided by 3 (12 MHz input)001 = Oscillator input divided by 2 (8 MHz input)000 = Oscillator input is used directly (4 MHz input)
POSCMD CW2 Primary Oscillator Mode Select bits11 = Primary Oscillator mode is disabled10 = HS Crystal Oscillator mode01 = XT Crystal Oscillator mode00 = EC (External Clock) mode
WDTPS CW1 Watchdog Timer Prescaler bits1111 = 1:32,7681110 = 1:16,384 . . .0001 = 1:20000 = 1:1
TABLE 4-2: PIC24FJXXXGA1/GB1 FAMILIES CONFIGURATION BITS DESCRIPTION (CONTINUED)Bit Field Register Description
Note 1: Available on PIC24FJXXXGB1XX devices only.2: Available on PIC24FJXXXGA110 devices only. On other devices, always maintain this bit as ‘1’.
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WINDIS CW1 Windowed WDT bit1 = Watchdog Timer is in Non-Window mode0 = Watchdog Timer is in Window mode; FWDTEN must be ‘1’
WPCFG CW3 Configuration Word Code Page Protection Select bit1 = Last page (at the top of program memory) and Flash Configuration
Words are not protected0 = Last page and Flash Configuration Words are code-protected
WPDIS CW3 Segment Write Protection Disable bit1 = Segmented code protection is disabled0 = Segmented code protection is enabled; protected segment defined by
the WPEND, WPCFG and WPFPx Configuration bitsWPEND CW3 Segment Write Protection End Page Select bit
1 = Protected code segment lower boundary is at the bottom of programmemory (000000h); upper boundary is the code page specified byWPFP
0 = Protected code segment upper boundary is at the last page of programmemory; lower boundary is the code page specified by WPFP
WPFP CW3 Protected Code Segment Boundary Page bitsDesignates the 512 instruction words page boundary of the protected code segment.If WPEND = 1:Specifies the lower page boundary of the code-protected segment; the last page being the last implemented page in the device.If WPEND = 0:Specifies the upper page boundary of the code-protected segment; Page 0 being the lower boundary.
TABLE 4-2: PIC24FJXXXGA1/GB1 FAMILIES CONFIGURATION BITS DESCRIPTION (CONTINUED)Bit Field Register Description
Note 1: Available on PIC24FJXXXGB1XX devices only.2: Available on PIC24FJXXXGA110 devices only. On other devices, always maintain this bit as ‘1’.
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4.6.2 PROGRAMMING METHODOLOGYConfiguration bits may be programmed a single byte ata time using the PROGP command. This commandspecifies the configuration data and Configurationregister address. When Configuration bits areprogrammed, any unimplemented or reserved bitsmust be programmed with a ‘1’.Four PROGW commands are required to program theConfiguration bits. A flowchart for Configuration bitprogramming is shown in Figure 4-5.
4.6.3 PROGRAMMING VERIFICATIONAfter the Configuration bits are programmed, thecontents of memory should be verified to ensure thatthe programming was successful. Verification requiresthe Configuration bits to be read back and comparedagainst the copy held in the programmer’s buffer. TheREADP command reads back the programmedConfiguration bits and verifies that the programmingwas successful.
FIGURE 4-5: CONFIGURATION BIT PROGRAMMING FLOW
Note: If the General Segment Code-Protect bit(GCP) is programmed to ‘0’, code memoryis code-protected and can not be read.Code memory must be verified beforeenabling read protection. See Section 4.6.4“Code-Protect Configuration Bits” formore information about code-protectConfiguration bits.
Send PROGPCommand
ConfigAddress = 0XXXF8h(1)
IsPROGP response
PASS?
No
Yes
No
FailureReport Error
Start
Finish
Yes
IsConfigAddress0XXXFEh?(1)
ConfigAddress =ConfigAddress + 2
Note 1: Refer to Table 2-2 for Flash Configuration Word addresses.
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4.6.4 CODE-PROTECT CONFIGURATION BITS
PIC24FJXXXGA1/GB1 family devices provide twocomplimentary methods to protect application codefrom overwrites and erasures. These also help to pro-tect the device from inadvertent configuration changesduring run time. Additional information is available inthe product data sheet.
4.6.4.1 GENERAL SEGMENT PROTECTION
For all devices in the PIC24FJXXXGA1/GB1 families,the on-chip program memory space is treated as asingle block, known as the General Segment (GS).Code protection for this block is controlled by one Con-figuration bit, GCP. This bit inhibits external reads andwrites to the program memory space. It has no directeffect in normal execution mode.
Write protection is controlled by the GWRP bit in theConfiguration Word. When GWRP is programmed to‘0’, internal write and erase operations to programmemory are blocked.
4.6.4.2 CODE SEGMENT PROTECTIONIn addition to global General Segment protection, aseparate subrange of the program memory space canbe individually protected against writes and erases.This area can be used for many purposes where aseparate block of write and erase-protected code isneeded, such as bootloader applications. Unlikecommon boot block implementations, the specially pro-tected segment in PIC24FJXXXGA1/GB1 devices canbe located by the user anywhere in the program space,and configured in a wide range of sizes.
Code segment protection provides an added level ofprotection to a designated area of program memory bydisabling the NVM safety interlock whenever a write orerase address falls within a specified range. It does notoverride General Segment protection controlled by theGCP or GWRP bit. For example, if GCP and GWRPare enabled, enabling segmented code protection forthe bottom half of program memory does not undoGeneral Segment protection for the top half.
4.7 Exiting Enhanced ICSP ModeExiting Program/Verify mode is done by removing VIHfrom MCLR, as shown in Figure 4-6. The only require-ment for exit is that an interval, P16, should elapsebetween the last clock, and program signals on PGCxand PGDx, before removing VIH.
FIGURE 4-6: EXITING ENHANCED ICSP™ MODE
Note: Bulk Erasing in ICSP mode is the only wayto reprogram code-protect bits from an ONstate (‘0’) to an OFF state (‘1’).
MCLR
P16
PGDx
PGDx = Input
PGCx
VDD
VIH
VIH
P17
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5.0 THE PROGRAMMING EXECUTIVE
5.1 Programming Executive Communication
The programmer and Programming Executive have amaster-slave relationship, where the programmer isthe master programming device and the ProgrammingExecutive is the slave.
All communication is initiated by the programmer in theform of a command. Only one command at a time canbe sent to the Programming Executive. In turn, theProgramming Executive only sends one response tothe programmer after receiving and processing acommand. The Programming Executive command setis described in Section 5.2 “Programming ExecutiveCommands”. The response set is described inSection 5.3 “Programming Executive Responses”.
5.1.1 COMMUNICATION INTERFACE AND PROTOCOL
The Enhanced ICSP interface is a 2-wire SPI,implemented using the PGCx and PGDx pins. ThePGCx pin is used as a clock input pin and the clocksource must be provided by the programmer. ThePGDx pin is used for sending command data to, andreceiving response data from, the ProgrammingExecutive.
Data transmits to the device must change on the risingedge and hold on the falling edge. Data receives fromthe device must change on the falling edge and hold onthe rising edge.
All data transmissions are sent to the Most Significantbit (MSb) first, using 16-bit mode (see Figure 5-1).
FIGURE 5-1: PROGRAMMING EXECUTIVE SERIAL TIMING FOR DATA RECEIVED FROM DEVICE
FIGURE 5-2: PROGRAMMING EXECUTIVE SERIAL TIMING FOR DATA TRANSMITTED TO DEVICE
Since a 2-wire SPI is used, and data transmissions arehalf-duplex, a simple protocol is used to control thedirection of PGDx. When the programmer completes acommand transmission, it releases the PGDx line andallows the Programming Executive to drive this linehigh. The Programming Executive keeps the PGDx linehigh to indicate that it is processing the command.
After the Programming Executive has processed thecommand, it brings PGDx low for 15 s to indicate to theprogrammer that the response is available to be clockedout. The programmer can begin to clock out theresponse, 23 s after PGDx is brought low, and it mustprovide the necessary amount of clock pulses to receivethe entire response from the Programming Executive.
After the entire response is clocked out, the program-mer should terminate the clock on PGCx until it is timeto send another command to the ProgrammingExecutive. This protocol is shown in Figure 5-3.
5.1.2 SPI RATEIn Enhanced ICSP mode, the PIC24FJXXXGA1/GB1devices operate from the Internal Fast RC oscillator(FRCDIV), which has a nominal frequency of 8 MHz.This oscillator frequency yields an effective systemclock frequency of 4 MHz. To ensure that the program-mer does not clock too fast, it is recommended that a4 MHz clock be provided by the programmer.
5.1.3 TIME-OUTSThe Programming Executive uses no Watchdog Timeror time-out for transmitting responses to the program-mer. If the programmer does not follow the flow controlmechanism using PGCx, as described in Section 5.1.1“Communication Interface and Protocol”, it ispossible that the Programming Executive will behaveunexpectedly while trying to send a response to theprogrammer. Since the Programming Executive has notime-out, it is imperative that the programmer correctlyfollow the described communication protocol.
As a safety measure, the programmer should use thecommand time-outs identified in Table 5-1. If the com-mand time-out expires, the programmer should resetthe Programming Executive and start programming thedevice again.
PGCx
PGDx
1 2 3 11 13 15 161412
LSb14 13 12 11
4 5 6
MSb 123... 45
P2
P3
P1
P1BP1A
PGCx
PGDx
1 2 3 11 13 15 161412
LSb14 13 12 11
4 5 6
MSb 123... 45
P2
P3
P1
P1BP1A
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FIGURE 5-3: PROGRAMMING EXECUTIVE – PROGRAMMER COMMUNICATION PROTOCOL
5.2 Programming Executive Commands
The Programming Executive command set is shown inTable 5-1. This table contains the opcode, mnemonic,length, time-out and description for each command.Functional details on each command are provided inSection 5.2.4 “Command Descriptions”.
5.2.1 COMMAND FORMATAll Programming Executive commands have a generalformat consisting of a 16-bit header and any requireddata for the command (see Figure 5-4). The 16-bitheader consists of a 4-bit opcode field, which is used toidentify the command, followed by a 12-bit commandlength field.
FIGURE 5-4: COMMAND FORMAT
The command opcode must match one of those in thecommand set. Any command that is received whichdoes not match the list in Table 5-1 will return a “NACK”response (see Section 5.3.1.1 “Opcode Field”). The command length is represented in 16-bit wordssince the SPI operates in 16-bit mode. The Program-ming Executive uses the command length field todetermine the number of words to read from the SPIport. If the value of this field is incorrect, the commandwill not be properly received by the ProgrammingExecutive.
5.2.2 PACKED DATA FORMATWhen 24-bit instruction words are transferred acrossthe 16-bit SPI interface, they are packed to conservespace using the format shown in Figure 5-5. Thisformat minimizes traffic over the SPI and provides theProgramming Executive with data that is properlyaligned for performing Table Write operations.
FIGURE 5-5: PACKED INSTRUCTION WORD FORMAT
5.2.3 PROGRAMMING EXECUTIVE ERROR HANDLING
The Programming Executive will “NACK” allunsupported commands. Additionally, due to thememory constraints of the Programming Executive, nochecking is performed on the data contained in theprogrammer command. It is the responsibility of theprogrammer to command the Programming Executivewith valid command arguments or the programmingoperation may fail. Additional information on errorhandling is provided in Section 5.3.1.3 “QE_CodeField”.
1 2 15 16 1 2 15 16
PGCx
PGDx
PGCx = Input PGCx = Input (Idle)
Host TransmitsLast Command Word
PGDx = Input PGDx = Output
P8
1 2 15 16
MSB X X X LSB MSB X X X LSB MSB X X X LSB1 0P20
PGCx = InputPGDx = Output
P9
Programming ExecutiveProcesses Command Host Clocks Out Response
P21
15 12 11 0Opcode Length
Command Data First Word (if required)••
Command Data Last Word (if required)
Note: When the number of instruction wordstransferred is odd, MSB2 is zero andLSW2 can not be transmitted.
15 8 7 0LSW1
MSB2 MSB1LSW2
LSWx: Least Significant 16 bits of instruction wordMSBx: Most Significant Bytes of instruction word
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TABLE 5-1: PROGRAMMING EXECUTIVE COMMAND SET
5.2.4 COMMAND DESCRIPTIONSAll commands supported by the Programming Executiveare described in Section 5.2.5 “SCHECK Command”through Section 5.2.12 “QVER Command”.
5.2.5 SCHECK COMMAND
The SCHECK command instructs the ProgrammingExecutive to do nothing but generate a response. Thiscommand is used as a “Sanity Check” to verify that theProgramming Executive is operational.
Expected Response (2 words):1000h0002h
Opcode Mnemonic Length(16-bit words) Time-out Description
0h SCHECK 1 1 ms Sanity check.1h READC 3 1 ms Read an 8-bit word from the specified Device ID register.2h READP 4 1 ms/row Read N 24-bit instruction words of code memory starting from
the specified address.3h RESERVED N/A N/A This command is reserved; it will return a NACK.4h PROGC 4 5 ms Write an 8-bit word to the specified Device ID registers.5h PROGP 99 5 ms Program one row of code memory at the specified address,
then verify.(1)
Dh PROGW 4 5 ms Program one instruction word of code memory at the specified address, then verify.
7h RESERVED N/A N/A This command is reserved; it will return a NACK.8h RESERVED N/A N/A This command is reserved; it will return a NACK.9h RESERVED N/A N/A This command is reserved; it will return a NACK.Ah QBLANK 3 30 ms/Kbyte Query if the code memory is blank.Bh QVER 1 1 ms Query the Programming Executive software version.
Note 1: One row of code memory consists of (64) 24-bit words. Refer to Table 2-2 for device-specific information.
15 12 11 0Opcode Length
Field Description
Opcode 0hLength 1h
Note: This instruction is not required forprogramming but is provided fordevelopment purposes only.
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5.2.6 READC COMMAND
The READC command instructs the Programming Exec-utive to read N or Device ID registers, starting from the24-bit address specified by Addr_MSB and Addr_LS.This command can only be used to read 8-bit or 16-bitdata.
When this command is used to read Device IDregisters, the upper byte in every data word returned bythe Programming Executive is 00h and the lower bytecontains the Device ID register value.
Expected Response (4 + 3 * (N – 1)/2 words for N odd):1100h2 + NDevice ID Register 1... Device ID Register N
5.2.7 READP COMMAND
The READP command instructs the Programming Exec-utive to read N 24-bit words of code memory, includingConfiguration Words, starting from the 24-bit addressspecified by Addr_MSB and Addr_LS. This commandcan only be used to read 24-bit data. All data returned inresponse to this command uses the packed data formatdescribed in Section 5.2.2 “Packed Data Format”.Expected Response (2 + 3 * N/2 words for N even):
1200h2 + 3 * N/2Least Significant Program Memory Word 1... Least Significant Data Word N
Expected Response (4 + 3 * (N – 1)/2 words for N odd):1200h
4 + 3 * (N – 1)/2
Least Significant Program Memory Word 1
...
MSB of Program Memory Word N (zero-padded)
15 12 11 8 7 0Opcode Length
N Addr_MSBAddr_LS
Field Description
Opcode 1hLength 3hN Number of 8-bit Device ID registers to
read (max. of 256)Addr_MSB MSB of 24-bit source addressAddr_LS Least Significant 16 bits of 24-bit
source address
Note: Reading unimplemented memory willcause the Programming Executive toreset. Please ensure that only memorylocations present on a particular deviceare accessed.
15 12 11 8 7 0Opcode Length
NReserved Addr_MSB
Addr_LS
Field Description
Opcode 2hLength 4hN Number of 24-bit instructions to read
(max. of 32768)Reserved 0hAddr_MSB MSB of 24-bit source addressAddr_LS Least Significant 16 bits of 24-bit
source address
Note: Reading unimplemented memory willcause the Programming Executive toreset. Please ensure that only memorylocations present on a particular deviceare accessed.
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5.2.8 PROGC COMMAND
The PROGC command instructs the Programming Exec-utive to program a single Device ID register located atthe specified memory address.
After the specified data word has been programmed tocode memory, the Programming Executive verifies theprogrammed data against the data in the command.
Expected Response (2 words):1400h0002h
5.2.9 PROGP COMMAND
The PROGP command instructs the Programming Exec-utive to program one row of code memory, includingConfiguration Words (64 instruction words), to thespecified memory address. Programming begins withthe row address specified in the command. Thedestination address should be a multiple of 80h.
The data to program to memory, located in commandwords, D_1 through D_96, must be arranged using thepacked instruction word format shown in Figure 5-5.
After all data has been programmed to code memory,the Programming Executive verifies the programmeddata against the data in the command.
Expected Response (2 words):1500h0002h
15 12 11 8 7 0Opcode Length
Reserved Addr_MSBAddr_LS
Data
Field Description
Opcode 4hLength 4hReserved 0hAddr_MSB MSB of 24-bit destination addressAddr_LS Least Significant 16 bits of 24-bit
destination addressData 8-bit data word
15 12 11 8 7 0Opcode Length
Reserved Addr_MSBAddr_LS
D_1D_2...
D_96
Field Description
Opcode 5hLength 63hReserved 0hAddr_MSB MSB of 24-bit destination addressAddr_LS Least Significant 16 bits of 24-bit
destination addressD_1 16-bit Data Word 1D_2 16-bit Data Word 2... 16-bit Data Word 3 through 95D_96 16-bit Data Word 96
Note: Refer to Table 2-2 for code memory sizeinformation.
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5.2.10 PROGW COMMAND
The PROGW command instructs the Programming Exec-utive to program one word of code memory (3 bytes) tothe specific memory address.
After the word has been programmed to code memory,the Programming Executive verifies the programmeddata against the data in the command.
Expected Response (2 words):1D00h0002h
5.2.11 QBLANK COMMAND
The QBLANK command queries the ProgrammingExecutive to determine if the contents of code memoryand code-protect Configuration bits (GCP and GWRP)are blank (contain all ‘1’s). The size of code memory tocheck must be specified in the command.
The Blank Check for code memory begins at 0h andadvances toward larger addresses for the specifiednumber of instruction words.
QBLANK returns a QE_Code of F0h if the specifiedcode memory and code-protect bits are blank;otherwise, QBLANK returns a QE_Code of 0Fh.Expected Response (2 words for blank device):
1AF0h
0002h
Expected Response (2 words for non-blank device):1A0Fh
0002h
15 12 11 8 7 2 1 0Opcode Length
Data_MSB Addr_MSBAddr_LSData_LS
Field Description
Opcode DhLength 4hAddr_MSB MSB of 24-bit destination addressAddr_LS Least Significant 16 bits of 24-bit
destination addressData_MSB MSB of 24-bit dataData_LS Least Significant 16 bits of 24-bit data
15 12 11 0Opcode Length
PSize_MSWPSize_LSW
Field Description
Opcode AhLength 3hPSize Length of program memory to check
in 24-bit words plus one (max. of 49152)
Note: QBLANK does not check the systemoperation Configuration bits, since thesebits are not set to ‘1’ when a Chip Erase isperformed.
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5.2.12 QVER COMMAND
The QVER command queries the version of theProgramming Executive software stored in testmemory. The “version.revision” information is returnedin the response’s QE_Code using a single byte with thefollowing format: main version in upper nibble andrevision in the lower nibble (i.e., 23h means Version 2.3of Programming Executive software).
Expected Response (2 words):1BMNh (where “MN” stands for Version M.N)0002h
5.3 Programming Executive Responses
The Programming Executive sends a response to theprogrammer for each command that it receives. Theresponse indicates if the command was processedcorrectly. It includes any required response data orerror data.
The Programming Executive response set is shown inTable 5-2. This table contains the opcode, mnemonicand description for each response. The response formatis described in Section 5.3.1 “Response Format”.
TABLE 5-2: PROGRAMMING EXECUTIVE RESPONSE OPCODES
5.3.1 RESPONSE FORMATAll Programming Executive responses have a generalformat consisting of a two-word header and anyrequired data for the command.
5.3.1.1 Opcode FieldThe opcode is a 4-bit field in the first word of theresponse. The opcode indicates how the commandwas processed (see Table 5-2). If the command wasprocessed successfully, the response opcode is PASS.If there was an error in processing the command, theresponse opcode is FAIL and the QE_Code indicatesthe reason for the failure. If the command sent tothe Programming Executive is not identified, theProgramming Executive returns a NACK response.
5.3.1.2 Last_Cmd FieldThe Last_Cmd is a 4-bit field in the first word ofthe response and indicates the command that theProgramming Executive processed. Since the Pro-gramming Executive can only process one commandat a time, this field is technically not required. However,it can be used to verify that the Programming Executivecorrectly received the command that the programmertransmitted.
15 12 11 0Opcode Length
Field Description
Opcode BhLength 1h
Opcode Mnemonic Description
1h PASS Command successfully processed
2h FAIL Command unsuccessfully processed
3h NACK Command not known
Field Description
Opcode Response opcodeLast_Cmd Programmer command that
generated the responseQE_Code Query code or error code.Length Response length in 16-bit words
(includes 2 header words)D_1 First 16-bit data word (if applicable)D_N Last 16-bit data word (if applicable)
15 12 11 8 7 0
Opcode Last_Cmd QE_Code
Length
D_1 (if applicable)
...
D_N (if applicable)
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5.3.1.3 QE_Code FieldThe QE_Code is a byte in the first word of theresponse. This byte is used to return data for querycommands and error codes for all other commands.
When the Programming Executive processes one ofthe two query commands (QBLANK or QVER), thereturned opcode is always PASS and the QE_Codeholds the query response data. The format of theQE_Code for both queries is shown in Table 5-3.
TABLE 5-3: QE_Code FOR QUERIES
When the Programming Executive processes anycommand other than a query, the QE_Code representsan error code. Supported error codes are shown inTable 5-4. If a command is successfully processed, thereturned QE_Code is set to 0h, which indicates thatthere was no error in the command processing. If theverify of the programming for the PROGP or PROGCcommand fails, the QE_Code is set to 1h. For all otherProgramming Executive errors, the QE_Code is 2h.
TABLE 5-4: QE_Code FOR NON-QUERY COMMANDS
5.3.1.4 Response LengthThe response length indicates the length of theProgramming Executive’s response in 16-bit words.This field includes the 2 words of the response header.
With the exception of the response for the READPcommand, the length of each response is only 2 words.
The response to the READP command uses the packedinstruction word format described in Section 5.2.2“Packed Data Format”. When reading an odd numberof program memory words (N odd), the response to theREADP command is (3 * (N + 1)/2 + 2) words. Whenreading an even number of program memory words(N even), the response to the READP command is(3 * N/2 + 2) words.
Query QE_Code
QBLANK 0Fh = Code memory is NOT blankF0h = Code memory is blank
QVER 0xMN, where Programming Executive software version = M.N (i.e., 32h means Software Version 3.2)
QE_Code Description
0h No error1h Verify failed2h Other error
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5.4 Programming the Programming Executive to Memory
5.4.1 OVERVIEWIf it is determined that the Programming Executive isnot present in executive memory (as described inSection 4.2 “Confirming the Presence of the Pro-gramming Executive”), it must be programmed intoexecutive memory using ICSP, as described inSection 3.0 “Device Programming – ICSP”.
Storing the Programming Executive to executivememory is similar to normal programming of codememory. Namely, the executive memory must beerased and then the Programming Executive must beprogrammed, 64 words at a time. Erasing the last pageof executive memory will cause the FRC oscillatorcalibration settings, and device diagnostic data in theDiagnostic and Calibration Words, at addresses,8007F0h to 8007FEh, to be erased. In order to retainthis calibration, these memory locations should be readand stored prior to erasing executive memory. Theyshould then be reprogrammed in the last words of pro-gram memory. This control flow is summarized inTable 5-5.
TABLE 5-5: PROGRAMMING THE PROGRAMMING EXECUTIVECommand
(Binary)Data(Hex) Description
Step 1: Exit the Reset vector and erase executive memory.000000000000
000000040200000000
NOPGOTO 0x200NOP
Step 2: Initialize the pointers to read the Diagnostic and Calibration Words for storage in W6-W13.00000000000000000000
200800880190207F012000C2000000
MOV #0x80, W0MOV W0, TBLPAGMOV #0x07F0, W1MOV #0xC, W2NOP
Step 3: Repeat this step 8 times to read the Diagnostic and Calibration Words, storin