PIC18F6585/8585/6680/8680 Data Sheet

2004 Microchip Technology Inc. DS30491C

PIC18F6585/8585/6680/8680Data Sheet

64/68/80-Pin High-Performance,

64-Kbyte Enhanced Flash

Microcontrollers with ECAN Module

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is intended through suggestion onlyand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.No representation or warranty is given and no liability isassumed by Microchip Technology Incorporated with respectto the accuracy or use of such information, or infringement ofpatents or other intellectual property rights arising from suchuse or otherwise. Use of Microchip’s products as criticalcomponents in life support systems is not authorized exceptwith express written approval by Microchip. No licenses areconveyed, implicitly or otherwise, under any intellectualproperty rights.

DS30491C-page ii

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart and rfPIC are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartShunt and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, Select Mode, SmartSensor, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

© 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

2004 Microchip Technology Inc.

Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

PIC18F6585/8585/6680/868064/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash

Microcontrollers with ECAN Module

High-Performance RISC CPU:• Source code compatible with the PIC16 and

PIC17 instruction sets• Linear program memory addressing to 2 Mbytes• Linear data memory addressing to 4096 bytes • 1 Kbyte of data EEPROM• Up to 10 MIPs operation:

- DC – 40 MHz osc./clock input- 4 MHz-10 MHz osc./clock input with PLL active

• 16-bit wide instructions, 8-bit wide data path• Priority levels for interrupts • 31-level, software accessible hardware stack• 8 x 8 Single-Cycle Hardware Multiplier

External Memory Interface(PIC18F8X8X Devices Only):• Address capability of up to 2 Mbytes• 16-bit interface

Peripheral Features:• High current sink/source 25 mA/25 mA• Four external interrupt pins• Timer0 module: 8-bit/16-bit timer/counter • Timer1 module: 16-bit timer/counter • Timer2 module: 8-bit timer/counter • Timer3 module: 16-bit timer/counter • Secondary oscillator clock option – Timer1/Timer3• One Capture/Compare/PWM (CCP) module:

- Capture is 16-bit, max. resolution 6.25 ns (TCY/16)

- Compare is 16-bit, max. resolution 100 ns (TCY)- PWM output: PWM resolution is 1 to 10-bit

• Enhanced Capture/Compare/PWM (ECCP) module:- Same Capture/Compare features as CCP- One, two or four PWM outputs- Selectable polarity- Programmable dead time- Auto-shutdown on external event- Auto-restart

• Master Synchronous Serial Port (MSSP) module with two modes of operation:- 3-wire SPI™ (supports all 4 SPI modes)- I2C™ Master and Slave mode

• Enhanced Addressable USART module:- Supports RS-232, RS-485 and LIN 1.2- Programmable wake-up on Start bit- Auto-baud detect

• Parallel Slave Port (PSP) module

Analog Features:• Up to 16-channel, 10-bit Analog-to-Digital

Converter module (A/D) with:- Fast sampling rate- Programmable acquisition time- Conversion available during Sleep

• Programmable 16-level Low-Voltage Detection (LVD) module:- Supports interrupt on Low-Voltage Detection

• Programmable Brown-out Reset (BOR)• Dual analog comparators:

- Programmable input/output configuration

ECAN Module Features:• Message bit rates up to 1 Mbps• Conforms to CAN 2.0B ACTIVE Specification• Fully backward compatible with PIC18XXX8 CAN

modules• Three modes of operation:

- Legacy, Enhanced Legacy, FIFO• Three dedicated transmit buffers with prioritization• Two dedicated receive buffers• Six programmable receive/transmit buffers• Three full 29-bit acceptance masks• 16 full 29-bit acceptance filters with dynamic association• DeviceNet™ data byte filter support• Automatic remote frame handling• Advanced Error Management features

Special Microcontroller Features:• 100,000 erase/write cycle Enhanced Flash

program memory typical• 1,000,000 erase/write cycle Data EEPROM

memory typical• 1-second programming time• Flash/Data EEPROM Retention: > 40 years• Self-reprogrammable under software control• Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)• Watchdog Timer (WDT) with its own On-Chip

RC Oscillator• Programmable code protection• Power saving Sleep mode• Selectable oscillator options including:

- Software enabled 4x Phase Lock Loop (of primary oscillator)

- Secondary Oscillator (32 kHz) clock input• In-Circuit Serial Programming™ (ICSP™) via two pins• MPLAB® In-Circuit Debug (ICD) via two pins

2004 Microchip Technology Inc. DS30491C-page 1

PIC18F6585/8585/6680/8680

CMOS Technology:• Low-power, high-speed Flash technology• Fully static design• Wide operating voltage range (2.0V to 5.5V) • Industrial and Extended temperature ranges

Device

Program Memory Data Memory

I/O10-bit

A/D (ch)

CCP/ECCP (PWM)

MSSPECAN/

AUSARTTimers

8-bit/16-bitEMA

Bytes# Single-Word Instructions

SRAM (bytes)

EEPROM (bytes)

SPIMaster

I2C

PIC18F6585 48K 24576 3328 1024 53 12 1/1 Y Y Y/Y 2/3 N

PIC18F6680 64K 32768 3328 1024 53 12 1/1 Y Y Y/Y 2/3 N

PIC18F8585 48K 24576 3328 1024 69 16 1/1 Y Y Y/Y 2/3 Y

PIC18F8680 64K 32768 3328 1024 69 16 1/1 Y Y Y/Y 2/3 Y

DS30491C-page 2 2004 Microchip Technology Inc.

PIC18F6585/8585/6680/8680

Pin Diagrams

PIC18F6X8X

1

2

3

4

5

6

7

8

9

10

11

12

13

14

38

37

36

35

34

33

50 49

17 18 19 20 21 22 23 24 25 26

RE

2/C

S

RE

3

RE

4

RE

5/P

1C

RE

6/P

1B

RE

7/C

CP

2(1)

RD

0/P

SP

0

VD

D

VS

S

RD

1/P

SP

1

RD

2/P

SP

2

RD

3/P

SP

3

RD

4/P

SP

4

RD

5/P

SP

5

RD

6/P

SP

6

RD

7/P

SP

7

RE1/WR

RE0/RD

RG0/CANTX1

RG1/CANTX2

RG2/CANRX

RG3

RG5/MCLR/VPP

RG4/P1D

VSS

VDD

RF7/SSRF6/AN11/C1IN-

RF5/AN10/C1IN+/CVREF

RF4/AN9/C2IN-

RF3/AN8/C2IN+

RF2/AN7/C1OUT

RB0/INT0

RB1/INT1

RB2/INT2

RB3/INT3

RB4/KBI0

RB5/KBI1/PGM

RB6/KBI2/PGC

VSS

OSC2/CLKO/RA6

OSC1/CLKI

VDD

RB7/KBI3/PGD

RC4/SDI/SDA

RC3/SCK/SCL

RC2/CCP1/P1A

RF

0/A

N5

RF

1/A

N6/

C2O

UT

AV

DD

AV

SS

RA

3/A

N3/

VR

EF+

RA

2/A

N2/

VR

EF-

RA

1/A

N1

RA

0/A

N0

VS

S

VD

D

RA

4/T

0CK

I

RA

5/A

N4/

LVD

IN

RC

1/T

1OS

I/CC

P2(1

)

RC

0/T

1OS

O/T

13C

KI

RC

7/R

X/D

T

RC

6/T

X/C

K

RC5/SDO

15

16

31

40

39

27 28 29 30 32

48

47

46

45

44

43

42

41

54 53 52 5158 57 56 5560 5964 63 62 61

64-Pin TQFP

Note 1: CCP2 pin placement depends on CCP2MX setting.


PIC18F6585/8585/6680/8680

Pin Diagrams (Continued)

1011121314151617181920212223242526

6059585756555453525150494847464544

9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

2728 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

Top View

RB0/INT0RB1/INT1RB2/INT2RB3/INT3RB4/KBI0RB5/KBI1/PGMRB6/KBI2/PGCVSS

OSC2/CLKO/RA6

OSC1/CLKIVDD

RB7/KBI3/PGD

RC4/SDI/SDARC3/SCK/SCLRC2/CCP1/P1A

RE1/WRRE0/RD

RG0/CANTX1RG1/CANTX2RG2/CANRX

RG3RG5/MCLR/VPP

RG4/P1D

VSS

VDD

RF7/SSRF6/AN11/C1IN-


RF4/AN9/C2IN-RF3/AN8/C2IN+

RF2/AN7/C1OUT

RE

2/C

SR

E3

RE

4R

E5/

P1C

RE

6/P

1BR

E7/

CC

P2(1

)

RD

0/P

SP

0V

DD

VS

S

RD

1/P

SP

1R

D2/

PS

P2

RD

3/P

SP

3R

D4/

PS

P4

RD

5/P

SP

5R

D6/

PS

P6

RD

7/P

SP

7

RF

1/A

N6/

C2O

UT

RF

0/A

N5

AV

DD

AV

SS

RA

3/A

N3/

VR

EF+

RA

2/A

N2/

VR

EF-

RA

1/A

N1

RA

0/A

N0

VD

D

RA

4/T

0CK

IR

A5/

AN

4/LV

DIN

RC

1/T

1OS

I/CC

P2(1

)

RC

0/T

1OS

O/T

13C

KI

RC

7/R

X/D

TR

C6/

TX

/CK

RC5/SDO

N/CN

/CN/C

N/C

VS

SPIC18F6X8X

68-Pin PLCC

Note 1: CCP2 pin placement depends on CCP2MX setting.


PIC18F6585/8585/6680/8680

Pin Diagrams (Continued)

PIC18F8X8X

3

4

5

6

7

8

9

10

11

12

13

14

15

16

48

47

46

45

44

43

42

41

4039

64 63 62 61

21 22 23 24 25 26 27 28 29 30 31 32

RE

2/C

S/A

D10

RE

3/A

D11

RE

4/A

D12

RE

5/A

D13

/P1C

(3)

RE

6/A

D14

/P1B

(3)

RE

7/C

CP

2(2) /A

D15

RD

0/P

SP

0(1) /A

D0

VD

D

VS

S

RD

1/P

SP

1(1) /A

D1

RD

2/P

SP

2(1) /A

D2

RD

3/P

SP

3(1) /A

D3

RD

4/P

SP

4(1) /A

D4

RD

5/P

SP

5(1) /A

D5

RD

6/P

SP

6(1) /A

D6

RD

7/P

SP

7(1) /A

D7

RE1/WR/AD9

RE0/RD/AD8

RG0/CANTX1

RG1/CANTX2

RG2/CANRX

RG3

RG5/MCLR/VPP

RG4/P1D

VSS

VDD

RF7/SS

RB0/INT0

RB1/INT1

RB2/INT2

RB3/INT3/CCP2(2)

RB4/KBI0

RB5/KBI1/PGM

RB6/KBI2/PGC

VSS

OSC2/CLKO/RA6

OSC1/CLKI

VDD

RB7/KBI3/PGD

RC4/SDI/SDA

RC3/SCK/SCL

RC2/CCP1/P1A

RF

0/A

N5

RF

1/A

N6/

C2O

UT

AV

DD

AV

SS

RA

3/A

N3/

VR

EF+

RA

2/A

N2/

VR

EF-

RA

1/A

N1

RA

0/A

N0

VS

S

VD

D

RA

4/T

0CK

I

RA

5/A

N4/

LVD

IN

RC

1/T

1OS

I/CC

P2(2

)

RC

0/T

1OS

O/T

13C

KI

RC

7/R

X/D

T

RC

6/T

X/C

K

RC5/SDO

RJ0

/ALE

RJ1

/OE

RH

1/A

17

RH

0/A

161

2

RH2/A18

RH3/A19

17

18RH7/AN15/P1B(3)

RH6/AN14/P1C(3)

RH

5/A

N13

RH

4/A

N12

RJ5

/CE

RJ4

/BA

0

37

RJ7/UBRJ6/LB

50

49

RJ2/WRL

RJ3/WRH

19

20

33 34 35 36 38

58

57

56

55

54

53

52

51

60

59

68 67 66 6572 71 70 6974 7378 77 76 757980

80-Pin TQFP

Note 1: PSP is available only in Microcontroller mode.

2: CCP2 pin placement depends on CCP2MX and Processor mode settings.

3: P1B and P1C pin placement depends on ECCPMX setting.


RF4/AN9/C2IN-

RF3/AN8/C2IN+

RF2/AN7/C1OUT

RF6/AN11/C1IN-


PIC18F6585/8585/6680/8680

Table of Contents1.0 Device Overview .......................................................................................................................................................................... 92.0 Oscillator Configurations ............................................................................................................................................................ 233.0 Reset .......................................................................................................................................................................................... 334.0 Memory Organization ................................................................................................................................................................. 515.0 Flash Program Memory.............................................................................................................................................................. 836.0 External Memory Interface ......................................................................................................................................................... 937.0 Data EEPROM Memory ........................................................................................................................................................... 1018.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 1079.0 Interrupts .................................................................................................................................................................................. 10910.0 I/O Ports ................................................................................................................................................................................... 12511.0 Timer0 Module ......................................................................................................................................................................... 15512.0 Timer1 Module ......................................................................................................................................................................... 15913.0 Timer2 Module ......................................................................................................................................................................... 16214.0 Timer3 Module ......................................................................................................................................................................... 16415.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 16716.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 17517.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 18918.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (USART).................................................................. 22919.0 10-bit Analog-to-Digital Converter (A/D) Module ...................................................................................................................... 24920.0 Comparator Module.................................................................................................................................................................. 25921.0 Comparator Voltage Reference Module................................................................................................................................... 26522.0 Low-Voltage Detect .................................................................................................................................................................. 26923.0 ECAN Module........................................................................................................................................................................... 27524.0 Special Features of the CPU.................................................................................................................................................... 34525.0 Instruction Set Summary .......................................................................................................................................................... 36526.0 Development Support............................................................................................................................................................... 40727.0 Electrical Characteristics .......................................................................................................................................................... 41328.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 44929.0 Packaging Information.............................................................................................................................................................. 465Appendix A: Revision History............................................................................................................................................................. 469Appendix B: Device Differences......................................................................................................................................................... 469Appendix C: Conversion Considerations ........................................................................................................................................... 470Appendix D: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 470Appendix E: Migration from High-End to Enhanced Devices............................................................................................................. 471Index .................................................................................................................................................................................................. 473On-Line Support................................................................................................................................................................................. 487Systems Information and Upgrade Hot Line ...................................................................................................................................... 487Reader Response .............................................................................................................................................................................. 488PIC18F6585/8585/6680/8680 Product Identification System ............................................................................................................ 489


PIC18F6585/8585/6680/8680

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchipproducts. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department viaE-mail at [email protected] or fax the Reader Response Form in the back of this data sheet to (480) 792-4150.We welcome your feedback.

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ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for currentdevices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revisionof silicon and revision of document to which it applies.

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PIC18F6585/8585/6680/8680

NOTES:


PIC18F6585/8585/6680/8680

1.0 DEVICE OVERVIEW

This document contains device specific information forthe following devices:

PIC18F6X8X devices are available in 64-pin TQFP and68-pin PLCC packages. PIC18F8X8X devices areavailable in the 80-pin TQFP package. They aredifferentiated from each other in four ways:

1. Flash program memory (48 Kbytes for PIC18FX585 devices, 64 Kbytes for PIC18FX680)

2. A/D channels (12 for PIC18F6X8X devices, 16 for PIC18F8X8X)

3. I/O ports (7 on PIC18F6X8X devices, 9 onPIC18F8X8X)

4. External program memory interface (presentonly on PIC18F8X8X devices)

All other features for devices in thePIC18F6585/8585/6680/8680 family are identical.These are summarized in Table 1-1.

Block diagrams of the PIC18F6X8X and PIC18F8X8Xdevices are provided in Figure 1-1 and Figure 1-2,respectively. The pinouts for these device families arelisted in Table 1-2.

TABLE 1-1: PIC18F6585/8585/6680/8680 DEVICE FEATURES

• PIC18F6585 • PIC18F8585• PIC18F6680 • PIC18F8680

Features PIC18F6585 PIC18F6680 PIC18F8585 PIC18F8680

Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHzDC – 25 MHz w/EMA

DC – 40 MHzDC – 25 MHz w/EMA

Program Memory (Bytes) 48K 64K 48K (2 MB EMA) 64K (2 MB EMA)

Program Memory (Instructions) 24576 32768 24576 32768

Data Memory (Bytes) 3328 3328 3328 3328

Data EEPROM Memory (Bytes) 1024 1024 1024 1024

External Memory Interface No No Yes Yes

Interrupt Sources 29 29 29 29

I/O Ports Ports A-G Ports A-G Ports A-H, J Ports A-H, J

Timers 4 4 4 4

Capture/Compare/PWM Module 1 1 1 1

Enhanced Capture/Compare/PWM Module

1 1 1 1

Serial Communications MSSP, Enhanced AUSART,

ECAN

MSSP, Enhanced AUSART,

ECAN


ECAN


ECAN

Parallel Communications PSP PSP PSP(1) PSP(1)

10-bit Analog-to-Digital Module 12 input channels 12 input channels 16 input channels 16 input channels

Resets (and Delays) POR, BOR, RESET Instruction,

Stack Full, Stack Underflow

(PWRT, OST)

POR, BOR, RESET Instruction,


(PWRT, OST)



(PWRT, OST)



(PWRT, OST)

Programmable Low-Voltage Detect Yes Yes Yes Yes

Programmable Brown-out Reset Yes Yes Yes Yes

Instruction Set 75 Instructions 75 Instructions 75 Instructions 75 Instructions

Package 64-pin TQFP, 68-pin PLCC

64-pin TQFP, 68-pin PLCC

80-pin TQFP 80-pin TQFP

Note 1: PSP is only available in Microcontroller mode.


PIC18F6585/8585/6680/8680

FIGURE 1-1: PIC18F6X8X BLOCK DIAGRAM

Power-upTimer

OscillatorStart-up Timer

Power-onReset

WatchdogTimer

InstructionDecode &

Control

OSC1/CLKIOSC2/CLKO/RA6

RG5/ VDD, VSS

PORTA

PORTB

PORTC

RA4/T0CKIRA5/AN4/LVDIN

RB2/INT2:RB0/INT0

RB6/KBI2/PGC

RC0/T1OSO/T13CKIRC1/T1OSI/CCP2(1)

RC2/CCP1/P1ARC3/SCK/SCLRC4/SDI/SDARC5/SDORC6/TX/CKRC7/RX/DT

Brown-outReset

AUSARTComparatorSynchronous

BORTimer1 Timer2

Serial Port

RA3/AN3/VREF+RA2/AN2/VREF-RA1/AN1RA0/AN0

ECAN Module

TimingGeneration

10-bit ADC

RB3/INT3

Data Latch

Data RAM(3328 bytes)

Address Latch

Address<12>

12

Bank0, FBSR FSR0FSR1FSR2

inc/declogicDecode

4 12 4

PCH PCL

PCLATH

8

31 Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

W

8

BITOP88

ALU<8>

8

Test ModeSelect

Address Latch

Program Memory(48 Kbytes)

Data Latch

21

21

16

8

8

8

Table Pointer<21>

inc/dec logic

218

Data Bus<8>

Table Latch

8

IR

12

3

ROM Latch

Timer3

PORTD

RD7/PSP7

CCP2

RB4/KBI0RB5/KBI1/PGM

PCLATU

PCU

Precision

ReferenceBand Gap

PORTE

PORTGRG0/CANTX1RG1/CANTX2RG2/CANRXRG3RG4/P1D

Timer0

RE6/P1BRE7/CCP2(1)

RE5/P1CRE4RE3RE2/CS

RE0/RDRE1/WR

LVD

ECCP1

RB7/KBI3/PGD

:RD0/PSP0

RF6/AN11/C1IN-RF7/SS


RF4/AN9/C2IN-RF3/AN8/C2IN+RF2/AN7/C1OUT

RF0/AN5RF1/AN6/C2OUT

PORTF

RG5/MCLR/VPP

MCLR

OSC2/CLKO/RA6

Data EEPROM

Note 1: The CCP2 pin placement depends on the CCP2MX and Processor mode settings.

PIC18F6585/8585/6680/8680

FIGURE 1-2: PIC18F8X8X BLOCK DIAGRAM

Power-upTimer

OscillatorStart-up Timer

Power-onReset

WatchdogTimer

InstructionDecode &

Control

OSC1/CLKIOSC2/CLKO/RA6

RG5/ VDD, VSS

PORTA

PORTB

PORTC

RA4/T0CKIRA5/AN4/LVDIN

RB2/INT2:RB0/INT0

RB6/KBI2/PGC

RC0/T1OSO/T13CKIRC1/T1OSI/CCP2(1)

RC2/CCP1/P1ARC3/SCK/SCLRC4/SDI/SDARC5/SDORC6/TX/CKRC7/RX/DT

Brown-outReset

AUSARTComparatorSynchronous

BORTimer1 Timer2

Serial Port

RA3/AN3/VREF+RA2/AN2/VREF-RA1/AN1RA0/AN0

ECAN Module

TimingGeneration

10-bit ADC

RB3/INT3/CCP2(1)

Data Latch

Data RAM(3328 bytes)

Address Latch

Address<12>

12

Bank0, FBSR FSR0FSR1FSR2

inc/declogicDecode

4 12 4

PCH PCL

PCLATH

8

31 Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

W

8

BITOP88

ALU<8>

8

Test ModeSelect

Address Latch

Program Memory(64 Kbytes)

Data Latch

21

21

16

8

8

8

Table Pointer<21>

inc/dec logic

218

Data Bus<8>

Table Latch

8

IR

12

3

ROM Latch

Timer3

PORTD

RD7/PSP7

CCP2

RB4/KBI0RB5/KBI1/PGM

PCLATU

PCU

Precision

ReferenceBand Gap

PORTE

PORTGRG0/CANTX1RG1/CANTX2RG2/CANRXRG3RG4/P1D

Timer0

RE6/AD14/P1B(2)

RE7/CCP2(1)/AD15

RE5/AD13/P1C(2)RE4/AD12RE3/AD11RE2/CS/AD10

RE0/RD/AD8RE1/WR/AD9

LVD

ECCP1

RB7/KBI3/PGD

/AD7:

RF6/AN11/C1IN-RF7/SS


RF4/AN9/C2IN-RF3/AN8/C2IN+RF2/AN7/C1OUT

RF0/AN5RF1/AN6/C2OUT

PORTF

PORTJ

RJ6/LBRJ7/UB

RJ5/CERJ4/BA0

RJ3/WRHRJ2/WRL

RJ0/ALERJ1/OE

RG5/MCLR/VPP

MCLR

OSC2/CLKO/RA6

RD0/PSP0/AD0

AD7:AD0

A16, AD15:AD8

Sys

tem

Bus

Inte

rfac

e

Note 1: The CCP2 pin placement depends on the CCP2MX and Processor mode settings.2: P1B and P1C pin placement depends on the ECCPMX setting.

PORTH

RH3/A19:RH0/A16

RH7/AN15/P1B(2)

RH6/AN14/P1C(2)

RH5/AN13RH4/AN12

PIC18F6585/8585/6680/8680

TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS

Pin Name

Pin NumberPin

TypeBufferType

DescriptionPIC18F6X8X PIC18F8X8X

TQFP PLCC TQFP

RG5/MCLR/VPP

RG5MCLR

VPP

7 16 9

II

P

STST

Master Clear (input) or programming voltage (input).

General purpose input pin.Master Clear (Reset) input. This pin is an active-low Reset to the device.Programming voltage input.

OSC1/CLKIOSC1

CLKI

39 50 49I

I

CMOS/ST

CMOS

Oscillator crystal or external clock input.Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; otherwise CMOS.External clock source input. Always associated with pin function OSC1 (see OSC1/CLKI, OSC2/CLKO pins).

OSC2/CLKO/RA6OSC2

CLKO

RA6

40 51 50O

O

I/O

—

—

TTL

Oscillator crystal or clock output.Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode.In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate.General purpose I/O pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD)

Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.2: Default assignment when CCP2MX is set.3: External memory interface functions are only available on PIC18F8X8X devices.

4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.6: PSP is available in Microcontroller mode only.7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX

configuration bit.


PIC18F6585/8585/6680/8680

PORTA is a bidirectional I/O port.

RA0/AN0RA0AN0

24 34 30I/OI

TTLAnalog

Digital I/O.Analog input 0.

RA1/AN1RA1AN1

23 33 29I/OI

TTLAnalog


RA2/AN2/VREF-RA2AN2VREF-

22 32 28I/OII

TTLAnalogAnalog

Digital I/O.Analog input 2.A/D reference voltage (Low) input.

RA3/AN3/VREF+RA3AN3VREF+

21 31 27I/OII

TTLAnalogAnalog

Digital I/O.Analog input 3.A/D reference voltage (High) input.

RA4/T0CKIRA4

T0CKI

28 39 34I/O

I

ST/OD

ST

Digital I/O – Open-drain when configured as output.Timer0 external clock input.

RA5/AN4/LVDINRA5AN4LVDIN

27 38 33I/OII

TTLAnalogAnalog

Digital I/O.Analog input 4.Low-voltage detect input.

RA6 See the OSC2/CLKO/RA6 pin.

TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin NumberPin

TypeBufferType


TQFP PLCC TQFP


Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.2: Default assignment when CCP2MX is set.

3: External memory interface functions are only available on PIC18F8X8X devices.4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is

multiplexed with either RB3 or RC1.5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.6: PSP is available in Microcontroller mode only.

7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX configuration bit.


PIC18F6585/8585/6680/8680

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

RB0/INT0RB0INT0

48 60 58I/OI

TTLST

Digital I/O.External interrupt 0.

RB1/INT1RB1INT1

47 59 57I/OI

TTLST


RB2/INT2RB2INT2

46 58 56I/OI

TTLST


RB3/INT3/CCP2RB3INT3CCP2(1)

45 57 55I/OI/OI/O

TTLSTST

Digital I/O.External interrupt 3.Capture 2 input/Compare 2 output/ PWM 2 output.

RB4/KBI0RB4KBI0

44 56 54I/OI

TTLST

Digital I/O.Interrupt-on-change pin.

RB5/KBI1/PGMRB5KBI1PGM

43 55 53I/OI

I/O

TTLSTST

Digital I/O.Interrupt-on-change pin.Low-Voltage ICSP Programming enable pin.

RB6/KBI2/PGCRB6KBI2PGC

42 54 52I/OI

I/O

TTLSTST

Digital I/O.Interrupt-on-change pin. In-circuit debugger and ICSP programming clock.

RB7/KBI3/PGDRB7KBI3PGD

37 48 47I/OI/O

TTLST

Digital I/O.Interrupt-on-change pin. In-circuit debugger and ICSP programming data.


Pin Name

Pin NumberPin

TypeBufferType


TQFP PLCC TQFP


Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.

2: Default assignment when CCP2MX is set.3: External memory interface functions are only available on PIC18F8X8X devices.4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is

multiplexed with either RB3 or RC1.5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.

6: PSP is available in Microcontroller mode only.7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX

configuration bit.


PIC18F6585/8585/6680/8680

PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKIRC0T1OSOT13CKI

30 41 36I/OOI

ST—ST

Digital I/O.Timer1 oscillator output. Timer1/Timer3 external clock input.

RC1/T1OSI/CCP2RC1T1OSICCP2(1, 4)

29 40 35I/OI

I/O

STCMOS

ST

Digital I/O.Timer1 oscillator input.CCP2 Capture input/Compare output/PWM 2 output.

RC2/CCP1/P1ARC2CCP1P1A

33 44 43I/OI/OI/O

STSTST

Digital I/O.CCP1 Capture input/Compare output.CCP1 PWM output A.

RC3/SCK/SCLRC3SCK

SCL

34 45 44I/OI/O

I/O

STST

ST

Digital I/O.Synchronous serial clock input/output for SPI mode.Synchronous serial clock input/output for I2C mode.

RC4/SDI/SDARC4SDISDA

35 46 45I/OI

I/O

STSTST

Digital I/O.SPI data in.I2C data I/O.

RC5/SDORC5SDO

36 47 46I/OO

ST—

Digital I/O.SPI data out.

RC6/TX/CKRC6TXCK

31 42 37I/OOI/O

ST—ST

Digital I/O.USART asynchronous transmit.USART synchronous clock (see RX/DT).

RC7/RX/DTRC7RXDT

32 43 38I/OI

I/O

STSTST

Digital I/O.USART 1 asynchronous receive.USART 1 synchronous data (see TX/CK).


Pin Name

Pin NumberPin

TypeBufferType


TQFP PLCC TQFP





configuration bit.


PIC18F6585/8585/6680/8680

PORTD is a bidirectional I/O port. These pins have TTL input buffers when external memory is enabled.

RD0/PSP0/AD0RD0PSP0(6)

AD0(3)

58 3 72I/OI/OI/O

STTTLTTL

Digital I/O.Parallel Slave Port data.External memory address/data 0.


AD1(3)

55 67 69I/OI/OI/O

STTTLTTL



AD2(3)

54 66 68I/OI/OI/O

STTTLTTL



AD3(3)

53 65 67I/OI/OI/O

STTTLTTL



AD4(3)

52 64 66I/OI/OI/O

STTTLTTL



AD5(3)

51 63 65I/OI/OI/O

STTTLTTL



AD6(3)

50 62 64I/OI/OI/O

STTTLTTL



AD7(3)

49 61 63I/OI/OI/O

STTTLTTL



Pin Name

Pin NumberPin

TypeBufferType


TQFP PLCC TQFP






configuration bit.


PIC18F6585/8585/6680/8680

PORTE is a bidirectional I/O port.

RE0/RD/AD8RE0RD(6)

AD8(3)

2 11 4I/OI

I/O

STTTL

TTL

Digital I/O.Read control for Parallel Slave Port (see WR and CS pins).External memory address/data 8.

RE1/WR/AD9RE1WR(6)

AD9(3)

1 10 3I/OI

I/O

STTTL

TTL

Digital I/O.Write control for Parallel Slave Port (see CS and RD pins).External memory address/data 9.

RE2/CS/AD10RE2CS(6)

AD10(3)

64 9 78I/OI

I/O

STTTL

TTL

Digital I/O.Chip select control for Parallel Slave Port (see RD and WR).External memory address/data 10.

RE3/AD11RE3AD11(3)

63 8 77I/OI/O

STTTL

Digital I/O.External memory address/data 11.

RE4/AD12RE4AD12(3)

62 7 76I/OI/O

STTTL

Digital I/O.External memory address/data 12.

RE5/AD13/P1CRE5AD13(3)

P1C(7)

61 6 75I/OI/OI/O

STTTLST

Digital I/O.External memory address/data 13.ECCP1 PWM output C.

RE6/AD14/P1BRE6AD14(3)

P1B(7)

60 5 74I/OI/OI/O

STTTLST

Digital I/O.External memory address/data 14.ECCP1 PWM output B.

RE7/CCP2/AD15RE7CCP2(1,4)

AD15(3)

59 4 73I/OI/O

I/O

STST

TTL

Digital I/O.Capture 2 input/Compare 2 output/ PWM 2 output.External memory address/data 15.


Pin Name

Pin NumberPin

TypeBufferType


TQFP PLCC TQFP






configuration bit.


PIC18F6585/8585/6680/8680

PORTF is a bidirectional I/O port.

RF0/AN5RF0AN5

18 28 24I/OI

STAnalog


RF1/AN6/C2OUTRF1AN6C2OUT

17 27 23I/OIO

STAnalog

ST

Digital I/O.Analog input 6.Comparator 2 output.

RF2/AN7/C1OUTRF2AN7C1OUT

16 26 18I/OIO

STAnalog

ST

Digital I/O.Analog input 7.Comparator 1 output.

RF3/AN8/C2IN+RF1AN8C2IN+

15 25 17I/OII

STAnalogAnalog

Digital I/O.Analog input 8.Comparator 2 input (+).

RF4/AN9/C2IN-RF1AN9C2IN-

14 24 16I/OII

STAnalogAnalog

Digital I/O.Analog input 9.Comparator 2 input (-).


RF1AN10C1IN+CVREF

13 23 15

I/OIIO

STAnalogAnalogAnalog

Digital I/O.Analog input 10.Comparator 1 input (+).Comparator VREF output.

RF6/AN11/C1IN-RF6AN11C1IN-

12 22 14I/OII

STAnalogAnalog

Digital I/O.Analog input 11.Comparator 1 input (-)

RF7/SSRF7SS

11 21 13I/OI

STTTL

Digital I/O.SPI slave select input.


Pin Name

Pin NumberPin

TypeBufferType


TQFP PLCC TQFP


Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.2: Default assignment when CCP2MX is set.

3: External memory interface functions are only available on PIC18F8X8X devices.4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is

multiplexed with either RB3 or RC1.5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.6: PSP is available in Microcontroller mode only.

7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX configuration bit.


PIC18F6585/8585/6680/8680

PORTG is a bidirectional I/O port.

RG0/CANTX1RG0CANTX1

3 12 5I/OO

STTTL

Digital I/O.CAN bus transmit 1.

RG1/CANTX2RG1CANTX2

4 13 6I/OO

STTTL

Digital I/O.CAN bus transmit 2.

RG2/CANRXRG2CANRX

5 14 7I/OI

STTTL

Digital I/O.CAN bus receive.

RG3RG3

6 15 8I/O ST Digital I/O.

RG4/P1DRG4P1D

8 17 10I/OO

STTTL

Digital I/O.ECCP1 PWM output D.

RG5 7 16 9 I ST General purpose input pin.


Pin Name

Pin NumberPin

TypeBufferType


TQFP PLCC TQFP





configuration bit.


PIC18F6585/8585/6680/8680

PORTH is a bidirectional I/O port(5).

RH0/A16RH0A16

— — 79I/OO

STTTL

Digital I/O.External memory address 16.

RH1/A17RH1A17

— — 80I/OO

STTTL


RH2/A18RH2A18

— — 1I/OO

STTTL


RH3/A19RH3A19

— — 2I/OO

STTTL


RH4/AN12RH4AN12

— — 22I/OI

STAnalog


RH5/AN13RH5AN13

— — 21I/OI

STAnalog


RH6/AN14/P1CRH6AN14P1C(7)

— — 20I/OI

I/O

STAnalog

ST

Digital I/O.Analog input 14.Alternate CCP1 PWM output C.

RH7/AN15/P1BRH7AN15P1B(7)

— — 19I/OI

STAnalog

Digital I/O.Analog input 15.Alternate CCP1 PWM output B.


Pin Name

Pin NumberPin

TypeBufferType


TQFP PLCC TQFP





configuration bit.


PIC18F6585/8585/6680/8680

PORTJ is a bidirectional I/O port(5).

RJ0/ALERJ0ALE

— — 62I/OO

STTTL

Digital I/O.External memory address latch enable.

RJ1/OERJ1OE

— — 61I/OO

STTTL

Digital I/O.External memory output enable.

RJ2/WRLRJ2WRL

— — 60I/OO

STTTL

Digital I/O.External memory write low control.

RJ3/WRHRJ3WRH

— — 59I/OO

STTTL

Digital I/O.External memory write high control.

RJ4/BA0RJ4BA0

— — 39I/OO

STTTL

Digital I/O.System bus byte address 0 control.

RJ5/CECE

— — 40 I/OO

STTTL

Digital I/OExternal memory chip enable.

RJ6/LBRJ6LB

— — 42I/OO

STTTL

Digital I/O.External memory low byte select.

RJ7/UBRJ7UB

— — 41I/OO

STTTL

Digital I/O.External memory high byte select.

VSS 9, 25, 41, 56

19, 36,53, 68

11, 31, 51, 70

P — Ground reference for logic and I/O pins.

VDD 10, 26, 38, 57

2, 20, 37, 49

12, 32, 48, 71

P — Positive supply for logic and I/O pins.

AVSS 20 30 26 P — Ground reference for analog modules.

AVDD 19 29 25 P — Positive supply for analog modules.

NC — 1, 18, 35, 52

— — — No connect.


Pin Name

Pin NumberPin

TypeBufferType


TQFP PLCC TQFP





configuration bit.


PIC18F6585/8585/6680/8680

NOTES:


PIC18F6585/8585/6680/8680

2.0 OSCILLATOR CONFIGURATIONS

2.1 Oscillator Types

The PIC18F6585/8585/6680/8680 devices can beoperated in eleven different oscillator modes. The usercan program four configuration bits (FOSC3, FOSC2,FOSC1 and FOSC0) to select one of these elevenmodes:

1. LP Low-Power Crystal

2. XT Crystal/Resonator3. HS High-Speed Crystal/Resonator4. RC External Resistor/Capacitor

5. EC External Clock6. ECIO External Clock with I/O

pin enabled7. HS+PLL High-Speed Crystal/Resonator

with PLL enabled8. RCIO External Resistor/Capacitor with

I/O pin enabled9. ECIO+SPLL External Clock with software

controlled PLL10. ECIO+PLL External Clock with PLL and I/O

pin enabled11. HS+SPLL High-Speed Crystal/Resonator

with software control

2.2 Crystal Oscillator/Ceramic Resonators

In XT, LP, HS, HS+PLL or HS+SPLL Oscillator modes,a crystal or ceramic resonator is connected to the OSC1and OSC2 pins to establish oscillation. Figure 2-1shows the pin connections.

The PIC18F6585/8585/6680/8680 oscillator designrequires the use of a parallel cut crystal.

FIGURE 2-1: CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP CONFIGURATION)

TABLE 2-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS

Note: Use of a series cut crystal may give a fre-quency out of the crystal manufacturersspecifications.

Ranges Tested:

Mode Freq C1 C2

XT 455 kHz2.0 MHz4.0 MHz

68-100 pF15-68 pF15-68 pF

68-100 pF15-68 pF15-68 pF

HS 8.0 MHz16.0 MHz

10-68 pF10-22 pF

10-68 pF10-22 pF

These values are for design guidance only. See notes following this table.

Resonators Used:

2.0 MHz Murata Erie CSA2.00MG ± 0.5%

4.0 MHz Murata Erie CSA4.00MG ± 0.5%

8.0 MHz Murata Erie CSA8.00MT ± 0.5%

16.0 MHz Murata Erie CSA16.00MX ± 0.5%

All resonators used did not have built-in capacitors.

Note 1: Higher capacitance increases the stabilityof the oscillator, but also increases thestart-up time.

2: When operating below 3V VDD, or whenusing certain ceramic resonators at anyvoltage, it may be necessary to use highgain HS mode, try a lower frequencyresonator, or switch to a crystal oscillator.

3: Since each resonator/crystal has its owncharacteristics, the user should consult theresonator/crystal manufacturer for appro-priate values of external components, orverify oscillator performance.

Note 1: See Table 2-1 and Table 2-2 for recommendedvalues of C1 and C2.

2: A series resistor (RS) may be required for ATstrip cut crystals.

3: RF varies with the oscillator mode chosen.

C1(1)

C2(1)

XTAL

OSC2

OSC1

RF(3)

Sleep

To

Logic

PIC18FXX80/XX85RS(2)

Internal


PIC18F6585/8585/6680/8680

TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR

An external clock source may also be connected to theOSC1 pin in the HS, XT and LP modes, as shown inFigure 2-2.

FIGURE 2-2: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION)

2.3 RC Oscillator

For timing insensitive applications, the “RC” and“RCIO” device options offer additional cost savings.The RC oscillator frequency is a function of the supplyvoltage, the resistor (REXT) and capacitor (CEXT) val-ues and the operating temperature. In addition to this,the oscillator frequency will vary from unit to unit, dueto normal process parameter variation. Furthermore,the difference in lead frame capacitance between pack-age types will also affect the oscillation frequency,especially for low CEXT values. The user also needs totake into account variation due to tolerance of externalR and C components used. Figure 2-3 shows how theR/C combination is connected.

In the RC Oscillator mode, the oscillator frequencydivided by 4 is available on the OSC2 pin. This signalmay be used for test purposes or to synchronize otherlogic.

FIGURE 2-3: RC OSCILLATOR MODE

The RCIO Oscillator mode functions like the RC modeexcept that the OSC2 pin becomes an additional gen-eral purpose I/O pin. The I/O pin becomes bit 6 ofPORTA (RA6).

Ranges Tested:

Mode Freq C1 C2

LP 32.0 kHz 33 pF 33 pF

200 kHz 15 pF 15 pF

XT 200 kHz 47-68 pF 47-68 pF

1.0 MHz 15 pF 15 pF

4.0 MHz 15 pF 15 pF

HS 4.0 MHz 15 pF 15 pF

8.0 MHz 15-33 pF 15-33 pF

20.0 MHz 15-33 pF 15-33 pF

25.0 MHz TBD TBD

These values are for design guidance only. See notes following this table.

Crystals Used

32.0 kHz Epson C-001R32.768K-A ± 20 PPM

200 kHz STD XTL 200.000KHz ± 20 PPM

1.0 MHz ECS ECS-10-13-1 ± 50 PPM

4.0 MHz ECS ECS-40-20-1 ± 50 PPM

8.0 MHz Epson CA-301 8.000M-C ± 30 PPM

20.0 MHz Epson CA-301 20.000M-C ± 30 PPM

Note 1: Higher capacitance increases the stabilityof the oscillator, but also increases thestart-up time.

2: Rs (see Figure 2-1) may be required inHS mode, as well as XT mode, to avoidoverdriving crystals with low drive levelspecifications.

3: Since each resonator/crystal has its owncharacteristics, the user should consult theresonator/crystal manufacturer for appro-priate values of external components, orverify oscillator performance.

OSC1

OSC2Open

Clock fromExt. System PIC18FXX80/XX85

OSC2/CLKO

CEXT

REXT

PIC18FXX80/XX85

OSC1

FOSC/4

InternalClock

VDD

VSS

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

CEXT > 20pF


PIC18F6585/8585/6680/8680

2.4 External Clock Input

The EC, ECIO, EC+PLL and EC+SPLL Oscillatormodes require an external clock source to be con-nected to the OSC1 pin. The feedback device betweenOSC1 and OSC2 is turned off in these modes to savecurrent. There is a maximum 1.5 µs start-up requiredafter a Power-on Reset, or wake-up from Sleep mode.

In the EC Oscillator mode, the oscillator frequencydivided by 4 is available on the OSC2 pin. This signalmay be used for test purposes or to synchronize otherlogic. Figure 2-4 shows the pin connections for the ECOscillator mode.

FIGURE 2-4: EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION)

The ECIO Oscillator mode functions like the EC mode,except that the OSC2 pin becomes an additional gen-eral purpose I/O pin. The I/O pin becomes bit 6 ofPORTA (RA6). Figure 2-5 shows the pin connectionsfor the ECIO Oscillator mode.

FIGURE 2-5: EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION)

2.5 Phase Locked Loop (PLL)

A Phase Locked Loop circuit is provided as aprogrammable option for users that want to multiply thefrequency of the incoming oscillator signal by 4. For aninput clock frequency of 10 MHz, the internal clockfrequency will be multiplied to 40 MHz. This is useful forcustomers who are concerned with EMI due tohigh-frequency crystals.

The PLL can only be enabled when the oscillator config-uration bits are programmed for High-Speed Oscillatoror External Clock mode. If they are programmed for anyother mode, the PLL is not enabled and the system clockwill come directly from OSC1. There are two types ofPLL modes: Software Controlled PLL and Configurationbits Controlled PLL. In Software Controlled PLL mode,PIC18F6585/8585/6680/8680 executes at regular clockfrequency after all Reset conditions. During execution,application can enable PLL and switch to 4x clockfrequency operation by setting the PLLEN bit in theOSCCON register. In Configuration bits Controlled PLLmode, PIC18F6585/8585/6680/8680 always executeswith 4x clock frequency.

The type of PLL is selected by programming theFOSC<3:0> configuration bits in the CONFIG1HConfiguration register. The oscillator mode is specifiedduring device programming.

A PLL lock timer is used to ensure that the PLL haslocked before device execution starts. The PLL locktimer has a time-out that is called TPLL.

FIGURE 2-6: PLL BLOCK DIAGRAM

OSC1

OSC2FOSC/4


OSC1

I/O (OSC2)RA6


MU

X

VCOLoop

Filter

Divide by 4

PLL Enable

FIN

FOUT SYSCLK

Phase

Comparator

PIC18F6585/8585/6680/8680

2.6 Oscillator Switching Feature

The PIC18F6585/8585/6680/8680 devices include afeature that allows the system clock source to beswitched from the main oscillator to an alternatelow-frequency clock source. For thePIC18F6585/8585/6680/8680 devices, this alternateclock source is the Timer1 oscillator. If a low-frequencycrystal (32 kHz, for example) has been attached to theTimer1 oscillator pins and the Timer1 oscillator hasbeen enabled, the device can switch to a low-power

execution mode. Figure 2-7 shows a block diagram ofthe system clock sources. The clock switching featureis enabled by programming the Oscillator SwitchingEnable (OSCSEN) bit in configuration register,CONFIG1H, to a ‘0’. Clock switching is disabled in anerased device. See Section 12.0 “Timer1 Module” forfurther details of the Timer1 oscillator. See Section 24.0“Special Features of the CPU” for configurationregister details.

FIGURE 2-7: DEVICE CLOCK SOURCES

PIC18FXX80/XX85

TOSC

4 x PLL

TT1P

TSCLK

ClockSource

MU

X

Tosc/4

Timer1 Oscillator

T1OSCENEnableOscillator

T1OSO

T1OSI

Clock Source Option for other Modules

OSC1

OSC2

Sleep

Main Oscillator


PIC18F6585/8585/6680/8680

2.6.1 SYSTEM CLOCK SWITCH BIT

The system clock source switching is performed undersoftware control. The System Clock Switch bits,SCS1:SCS0 (OSCCON<1:0>), control the clock switch-ing. When the SCS0 bit is ‘0’, the system clock sourcecomes from the main oscillator that is selected by theFOSC configuration bits in configuration register,CONFIG1H. When the SCS0 bit is set, the system clocksource will come from the Timer1 oscillator. The SCS0bit is cleared on all forms of Reset.

When FOSC bits are programmed for software PLLmode, the SCS1 bit can be used to select between pri-mary oscillator/clock and PLL output. The SCS1 bit willonly have an effect on the system clock if the PLL is

enabled (PLLEN = 1) and locked (LOCK = 1), else it willbe forced clear. When programmed with ConfigurationControlled PLL mode, the SCS1 bit will be forced clear.

REGISTER 2-1: OSCCON REGISTER

Note: The Timer1 oscillator must be enabledand operating to switch the system clocksource. The Timer1 oscillator is enabledby setting the T1OSCEN bit in the Timer1Control register (T1CON). If the Timer1oscillator is not enabled, then any write tothe SCS0 bit will be ignored (SCS0 bitforced cleared) and the main oscillator willcontinue to be the system clock source.

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — LOCK PLLEN SCS1 SCS0

bit 7 bit 0

bit 7-4 Unimplemented: Read as ‘0’

bit 3 LOCK: Phase Lock Loop Lock Status bit1 = Phase Lock Loop output is stable as system clock0 = Phase Lock Loop output is not stable and output cannot be used as system clock

bit 2 PLLEN(1): Phase Lock Loop Enable bit

1 = Enable Phase Lock Loop output as system clock0 = Disable Phase Lock Loop

bit 1 SCS1: System Clock Switch bit 1When PLLEN and LOCK bits are set:1 = Use PLL output0 = Use primary oscillator/clock input pinWhen PLLEN or LOCK bit is cleared:Bit is forced clear.

bit 0 SCS0(2): System Clock Switch bit 0

When OSCSEN configuration bit = 0 and T1OSCEN bit = 1:1 = Switch to Timer1 oscillator/clock pin 0 = Use primary oscillator/clock input pinWhen OSCSEN and T1OSCEN are in other states:Bit is forced clear.

Note 1: PLLEN bit is ignored when configured for ECIO+PLL and HS+PLL. This bit is usedin ECIO+SPLL and HS+SPLL modes only.

2: The setting of SCS0 = 1 supersedes SCS1 = 1.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC18F6585/8585/6680/8680

2.6.2 OSCILLATOR TRANSITIONS

PIC18F6585/8585/6680/8680 devices contain circuitryto prevent “glitches” when switching between oscillatorsources. Essentially, the circuitry waits for eight risingedges of the clock source that the processor is switch-ing to. This ensures that the new clock source is stableand that its pulse width will not be less than the shortestpulse width of the two clock sources.

A timing diagram, indicating the transition from themain oscillator to the Timer1 oscillator, is shown inFigure 2-8. The Timer1 oscillator is assumed to be run-ning all the time. After the SCS0 bit is set, the processoris frozen at the next occurring Q1 cycle. After eightsynchronization cycles are counted from the Timer1oscillator, operation resumes. No additional delays arerequired after the synchronization cycles.

The sequence of events that takes place when switch-ing from the Timer1 oscillator to the main oscillator willdepend on the mode of the main oscillator. In additionto eight clock cycles of the main oscillator, additionaldelays may take place.

If the main oscillator is configured for an externalcrystal (HS, XT, LP), then the transition will take placeafter an oscillator start-up time (TOST) has occurred. Atiming diagram, indicating the transition from theTimer1 oscillator to the main oscillator for HS, XT andLP modes, is shown in Figure 2-9.

FIGURE 2-8: TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR

FIGURE 2-9: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)

Q3Q2Q1Q4Q3Q2

OSC1

Internal

SCS(OSCCON<0>)

ProgramPC + 2PC

Note: TDLY is the delay from SCS high to first count of transition circuit.

Q1

T1OSI

Q4 Q1

PC + 4

Q1

TSCS

Clock

Counter

System

Q2 Q3 Q4 Q1

TDLY

TT1P

TOSC

21 3 4 5 6 7 8

Q3Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2

OSC1

Internal

SCS(OSCCON<0>)

ProgramPC PC + 2

Note: TOST = 1024 TOSC (drawing not to scale).

T1OSI

System Clock

TOST

Q1

PC + 6

TT1P

TOSC

TSCS

1 2 3 4 5 6 7 8

Counter

PIC18F6585/8585/6680/8680

If the main oscillator is configured for HS mode withPLL active, an oscillator start-up time (TOST) plus anadditional PLL time-out (TPLL) will occur. The PLL time-out is typically 2 ms and allows the PLL to lock to themain oscillator frequency. A timing diagram, indicatingthe transition from the Timer1 oscillator to the mainoscillator for HS-PLL mode, is shown in Figure 2-10.

If the main oscillator is configured for EC mode with PLLactive, only the PLL time-out (TPLL) will occur. The PLLtime-out is typically 2 ms and allows the PLL to lock tothe main oscillator frequency. A timing diagram, indicat-ing the transition from the Timer1 oscillator to the mainoscillator for EC with PLL active, is shown in Figure 2-11.

FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1(HS WITH PLL ACTIVE, SCS1 = 1)

FIGURE 2-11: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (EC WITH PLL ACTIVE, SCS1 = 1)

Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2

OSC1

Internal System

SCS(OSCCON<0>)

Program Counter PC PC + 2

Note: TOST = 1024 TOSC (drawing not to scale).

T1OSI

Clock

TOST

Q3

PC + 4

TPLL

TOSC

TT1P

TSCS

Q4

PLL ClockInput 1 2 3 4 5 6 7 8

Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2

OSC1

Internal System

SCS(OSCCON<0>)

Program Counter PC PC + 2

T1OSI

Clock

Q3

PC + 4

TPLL

TOSC

TT1P

TSCS

Q4

PLL ClockInput 1 2 3 4 5 6 7 8

PIC18F6585/8585/6680/8680

If the main oscillator is configured in the RC, RCIO, ECor ECIO modes, there is no oscillator start-up time-out.Operation will resume after eight cycles of the mainoscillator have been counted. A timing diagram, indi-cating the transition from the Timer1 oscillator to themain oscillator for RC, RCIO, EC and ECIO modes, isshown in Figure 2-12.

FIGURE 2-12: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)

Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3

OSC1

Internal System

SCS(OSCCON<0>)

ProgramPC PC + 2

Note: RC Oscillator mode assumed.

PC + 4

T1OSI

Clock

Q4TT1P

TOSC

TSCS

1 2 3 4 5 6 7 8

Counter

PIC18F6585/8585/6680/8680

2.7 Effects of Sleep Mode on the On-Chip Oscillator

When the device executes a SLEEP instruction, the on-chip clocks and oscillator are turned off and the deviceis held at the beginning of an instruction cycle (Q1state). With the oscillator off, the OSC1 and OSC2signals will stop oscillating. Since all the transistor

switching currents have been removed, Sleep modeachieves the lowest current consumption of the device(only leakage currents). Enabling any on-chip featurethat will operate during Sleep will increase the currentconsumed during Sleep. The user can wake fromSleep through external Reset, Watchdog Timer Reset,or through an interrupt.

TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE

2.8 Power-up Delays

Power-up delays are controlled by two timers so that noexternal Reset circuitry is required for most applica-tions. The delays ensure that the device is kept inReset until the device power supply and clock are sta-ble. For additional information on Reset operation, seeSection 3.0 “Reset”.

The first timer is the Power-up Timer (PWRT) whichoptionally provides a fixed delay of 72 ms (nominal) onpower-up only (POR and BOR). The second timer isthe Oscillator Start-up Timer (OST), intended to keepthe chip in Reset until the crystal oscillator is stable.

With the PLL enabled (HS+PLL and EC+PLL Oscillatormode), the time-out sequence following a Power-onReset is different from other oscillator modes. Thetime-out sequence is as follows: First, the PWRT time-out is invoked after a POR time delay has expired.Then, the Oscillator Start-up Timer (OST) is invoked.However, this is still not a sufficient amount of time toallow the PLL to lock at high frequencies. The PWRTtimer is used to provide an additional fixed 2 ms(nominal) time-out to allow the PLL ample time to lockto the incoming clock frequency.

OSC Mode OSC1 Pin OSC2 Pin

RC Floating, external resistor should pull high At logic low

RCIO Floating, external resistor should pull high Configured as PORTA, bit 6

ECIO Floating Configured as PORTA, bit 6

EC Floating At logic low

LP, XT, and HS Feedback inverter disabled at quiescent voltage level

Feedback inverter disabled at quiescent voltage level

Note: See Table 3-1 in Section 3.0 “Reset”, for time-outs due to Sleep and MCLR Reset.


PIC18F6585/8585/6680/8680

NOTES:


PIC18F6585/8585/6680/8680

3.0 RESET

The PIC18F6585/8585/6680/8680 devices differentiatebetween various kinds of Reset:

a) Power-on Reset (POR)

b) MCLR Reset during normal operationc) MCLR Reset during Sleep d) Watchdog Timer (WDT) Reset (during normal

operation)e) Programmable Brown-out Reset (BOR)

f) RESET Instructiong) Stack Full Reseth) Stack Underflow Reset

Most registers are unaffected by a Reset. Their statusis unknown on POR and unchanged by all otherResets. The other registers are forced to a “Resetstate” on Power-on Reset, MCLR, WDT Reset, Brown-out Reset, MCLR Reset during Sleep and by theRESET instruction.

Most registers are not affected by a WDT wake-upsince this is viewed as the resumption of normal oper-ation. Status bits from the RCON register, RI, TO, PD,POR and BOR, are set or cleared differently in differentReset situations, as indicated in Table 3-2. These bitsare used in software to determine the nature of theReset. See Table 3-3 for a full description of the Resetstates of all registers.

A simplified block diagram of the On-Chip Reset Circuitis shown in Figure 3-1.

The Enhanced MCU devices have a MCLR noise filterin the MCLR Reset path. The filter will detect andignore small pulses. The MCLR pin is not driven low byany internal Resets, including the WDT.

FIGURE 3-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

S

R Q

External Reset

MCLR

VDD

OSC1

WDTModule

VDD RiseDetect

OST/PWRT

On-chipRC OSC(1)

WDTTime-out

Power-on Reset

OST

10-bit Ripple Counter

PWRT

Chip_Reset

10-bit Ripple Counter

Reset

Enable OST(2)

Enable PWRT

SLEEP

Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.

2: See Table 3-1 for time-out situations.

Brown-outReset BOREN

RESETInstruction

StackPointer Stack Full/Underflow Reset


PIC18F6585/8585/6680/8680

3.1 Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip whenVDD rise is detected. To take advantage of the POR cir-cuitry, tie the MCLR pin through a 1 kΩ to 10 kΩ resis-tor to VDD. This will eliminate external RC componentsusually needed to create a Power-on Reset delay. Aminimum rise rate for VDD is specified (parameterD004). For a slow rise time, see Figure 3-2.

When the device starts normal operation (i.e., exits theReset condition), device operating parameters (volt-age, frequency, temperature, etc.) must be met toensure operation. If these conditions are not met, thedevice must be held in Reset until the operatingconditions are met.

FIGURE 3-2: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)

3.2 Power-up Timer (PWRT)

The Power-up Timer provides a fixed nominal time-out(parameter #33) only on power-up from the POR. ThePower-up Timer operates on an internal RC oscillator.The chip is kept in Reset as long as the PWRT is active.The PWRT’s time delay allows VDD to rise to anacceptable level. A configuration bit is provided toenable/disable the PWRT.

The power-up time delay will vary from chip-to-chip dueto VDD, temperature and process variation. See DCparameter #33 for details.

3.3 Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides 1024oscillator cycles (from OSC1 input) delay after thePWRT delay is over (parameter #32). This ensures thatthe crystal oscillator or resonator has started andstabilized.

The OST time-out is invoked only for XT, LP and HSmodes and only on Power-on Reset, or wake-up fromSleep.

3.4 PLL Lock Time-out

With the PLL enabled, the time-out sequence followinga Power-on Reset is different from other oscillatormodes. A portion of the Power-up Timer is used to pro-vide a fixed time-out that is sufficient for the PLL to lockto the main oscillator frequency. This PLL lock time-out(TPLL) is typically 2 ms and follows the oscillatorstart-up time-out (OST).

3.5 Brown-out Reset (BOR)

A configuration bit, BOREN, can disable (if clear/programmed), or enable (if set) the Brown-out Resetcircuitry. If VDD falls below parameter D005 for greaterthan parameter #35, the brown-out situation will resetthe chip. A Reset may not occur if VDD falls belowparameter D005 for less than parameter #35. The chipwill remain in Brown-out Reset until VDD rises aboveBVDD. If the Power-up Timer is enabled, it will beinvoked after VDD rises above BVDD; it then will keepthe chip in Reset for an additional time delay (parame-ter #33). If VDD drops below BVDD while the Power-upTimer is running, the chip will go back into a Brown-outReset and the Power-up Timer will be initialized. OnceVDD rises above BVDD, the Power-up Timer willexecute the additional time delay.

3.6 Time-out Sequence

On power-up, the time-out sequence is as follows:First, PWRT time-out is invoked after the POR timedelay has expired. Then, OST is activated. The totaltime-out will vary based on oscillator configuration andthe status of the PWRT. For example, in RC mode withthe PWRT disabled, there will be no time-out at all.Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 andFigure 3-7 depict time-out sequences on power-up.

Since the time-outs occur from the POR pulse, thetime-outs will expire if MCLR is kept low long enough.Bringing MCLR high will begin execution immediately(Figure 3-5). This is useful for testing purposes or tosynchronize more than one PIC18FXX8X deviceoperating in parallel.

Table 3-2 shows the Reset conditions for some SpecialFunction Registers while Table 3-3 shows the Resetconditions for all of the registers.

Note 1: External Power-on Reset circuit is requiredonly if the VDD power-up slope is too slow.The diode D helps discharge the capacitorquickly when VDD powers down.

2: R < 40 kΩ is recommended to make sure thatthe voltage drop across R does not violatethe device’s electrical specification.

3: R1 = 1 kΩ to 10 kΩ will limit any current flow-ing into MCLR from external capacitor C, inthe event of MCLR/VPP pin breakdown due toElectrostatic Discharge (ESD) or ElectricalOverstress (EOS).

C

R1RD

VDD

MCLR

PIC18FXX8X

PIC18F6585/8585/6680/8680

TABLE 3-1: TIME-OUT IN VARIOUS SITUATIONS

REGISTER 3-1: RCON REGISTER BITS AND POSITIONS

TABLE 3-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER

OscillatorConfiguration

Power-up(2)

Brown-out Wake-up from

Sleep orOscillator SwitchPWRTE = 0 PWRTE = 1

HS with PLL enabled(1) 72 ms + 1024 TOSC + 2ms 1024 TOSC + 2 ms 1024 TOSC + 2 ms 1024 TOSC + 2 ms

EC with PLL enabled(1) 72 ms + 2ms 1.5 µs + 2 ms 2 ms 1.5 µs + 2 ms

HS, XT, LP 72 ms + 1024 TOSC 1024 TOSC 1024 TOSC 1024 TOSC

EC 72 ms 1.5 µs 1.5 µs 1.5 µs(3)

External RC 72 ms 1.5 µs 1.5 µs 1.5 µs

Note 1: 2 ms is the nominal time required for the 4x PLL to lock.2: 72 ms is the nominal power-up timer delay if implemented.3: 1.5 µs is the recovery time from Sleep. There is no recovery time from oscillator switch.

R/W-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0

IPEN — — RI TO PD POR BOR

bit 7 bit 0

Note: Refer to Section 4.14 “RCON Register” for bit definitions.

ConditionProgramCounter

RCONRegister

RI TO PD POR BOR STKFUL STKUNF

Power-on Reset 0000h 0--1 1100 1 1 1 0 0 u u

MCLR Reset during normal operation

0000h 0--u uuuu u u u u u u u

Software Reset during normal operation

0000h 0--0 uuuu 0 u u u u u u

Stack Full Reset during normal operation

0000h 0--u uu11 u u u u u u 1

Stack Underflow Reset during normal operation

0000h 0--u uu11 u u u u u 1 u

MCLR Reset during Sleep 0000h 0--u 10uu u 1 0 u u u u

WDT Reset 0000h 0--u 01uu 1 0 1 u u u u

WDT Wake-up PC + 2 u--u 00uu u 0 0 u u u u

Brown-out Reset 0000h 0--1 11u0 1 1 1 1 0 u u

Interrupt wake-up from Sleep PC + 2(1) u--u 00uu u 1 0 u u u u

Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the

interrupt vector (000008h or 000018h).


PIC18F6585/8585/6680/8680

TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS

Register Applicable DevicesPower-on Reset,Brown-out Reset

MCLR ResetsWDT Reset

RESET InstructionStack Resets

Wake-up via WDT or Interrupt

TOSU PIC18F6X8X PIC18F8X8X ---0 0000 ---0 0000 ---0 uuuu(3)

TOSH PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu(3)

TOSL PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu(3)

STKPTR PIC18F6X8X PIC18F8X8X 00-0 0000 uu-0 0000 uu-u uuuu(3)

PCLATU PIC18F6X8X PIC18F8X8X ---0 0000 ---0 0000 ---u uuuu

PCLATH PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

PCL PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 PC + 2(2)

TBLPTRU PIC18F6X8X PIC18F8X8X --00 0000 --00 0000 --uu uuuu

TBLPTRH PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

TBLPTRL PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

TABLAT PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

PRODH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

PRODL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

INTCON PIC18F6X8X PIC18F8X8X 0000 000x 0000 000x uuuu uuuu(1)

INTCON2 PIC18F6X8X PIC18F8X8X 1111 1111 1111 1111 uuuu uuuu(1)

INTCON3 PIC18F6X8X PIC18F8X8X 1100 0000 1100 0000 uuuu uuuu(1)

INDF0 PIC18F6X8X PIC18F8X8X N/A N/A N/A

POSTINC0 PIC18F6X8X PIC18F8X8X N/A N/A N/A

POSTDEC0 PIC18F6X8X PIC18F8X8X N/A N/A N/A

PREINC0 PIC18F6X8X PIC18F8X8X N/A N/A N/A

PLUSW0 PIC18F6X8X PIC18F8X8X N/A N/A N/A

FSR0H PIC18F6X8X PIC18F8X8X ---- xxxx ---- uuuu ---- uuuu

FSR0L PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

WREG PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu






Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.

4: See Table 3-2 for Reset value for specific condition.5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’.7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.


PIC18F6585/8585/6680/8680



BSR PIC18F6X8X PIC18F8X8X ---- 0000 ---- 0000 ---- uuuu








STATUS PIC18F6X8X PIC18F8X8X ---x xxxx ---u uuuu ---u uuuu

TMR0H PIC18F6X8X PIC18F8X8X 0000 0000 uuuu uuuu uuuu uuuu

TMR0L PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

T0CON PIC18F6X8X PIC18F8X8X 1111 1111 1111 1111 uuuu uuuu

OSCCON PIC18F6X8X PIC18F8X8X ---- 0000 ---- 0000 ---- uuuu

LVDCON PIC18F6X8X PIC18F8X8X --00 0101 --00 0101 --uu uuuu

WDTCON PIC18F6X8X PIC18F8X8X ---- ---0 ---- ---0 ---- ---u

RCON(4) PIC18F6X8X PIC18F8X8X 0--q 11qq 0--q qquu u--u qquu

TMR1H PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu


T1CON PIC18F6X8X PIC18F8X8X 0-00 0000 u-uu uuuu u-uu uuuu

TMR2 PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

PR2 PIC18F6X8X PIC18F8X8X 1111 1111 1111 1111 1111 1111

T2CON PIC18F6X8X PIC18F8X8X -000 0000 -000 0000 -uuu uuuu

SSPBUF PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

SSPADD PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

SSPSTAT PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

SSPCON1 PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

SSPCON2 PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)










oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’.7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.


PIC18F6585/8585/6680/8680

ADRESH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

ADRESL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

ADCON0 PIC18F6X8X PIC18F8X8X --00 0000 --00 0000 --uu uuuu

ADCON1 PIC18F6X8X PIC18F8X8X --00 0000 --00 0000 --uu uuuu

ADCON2 PIC18F6X8X PIC18F8X8X 0-00 0000 0-00 0000 u-uu uuuu

CCPR1H PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

CCPR1L PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

CCP1CON PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

CCPR2H PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

CCPR2L PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

CCP2CON PIC18F6X8X PIC18F8X8X --00 0000 --00 0000 --uu uuuu

CCPAS1 PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

CVRCON PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

CMCON PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

TMR3H PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu


T3CON PIC18F6X8X PIC18F8X8X 0000 0000 uuuu uuuu uuuu uuuu

PSPCON PIC18F6X8X PIC18F8X8X 0000 ---- 0000 ---- uuuu ----

SPBRG PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

RCREG PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

TXREG PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

TXSTA PIC18F6X8X PIC18F8X8X 0000 0010 0000 0010 uuuu uuuu

RCSTA PIC18F6X8X PIC18F8X8X 0000 000x 0000 000x uuuu uuuu

EEADRH PIC18F6X8X PIC18F8X8X ---- --00 ---- --00 ---- --uu

EEADR PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

EEDATA PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

EECON2 PIC18F6X8X PIC18F8X8X xx-0 x000 uu-0 u000 uu-0 u000

EECON1 PIC18F6X8X PIC18F8X8X 00-0 x000 00-0 u000 uu-u uuuu











oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’.

7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.


PIC18F6585/8585/6680/8680

IPR3 PIC18F6X8X PIC18F8X8X 1111 1111 1111 1111 uuuu uuuu

PIR3 PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

PIE3 PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

IPR2 PIC18F6X8X PIC18F8X8X -1-1 1111 -1-1 1111 -u-u uuuu

PIR2 PIC18F6X8X PIC18F8X8X -0-0 0000 -0-0 0000 -u-u uuuu(1)

PIE2 PIC18F6X8X PIC18F8X8X -0-0 0000 -0-0 0000 -u-u uuuu

IPR1 PIC18F6X8X PIC18F8X8X 1111 1111 1111 1111 uuuu uuuu

PIR1 PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu(1)

PIE1 PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

MEMCON PIC18F6X8X PIC18F8X8X 0-00 --00 0-00 --00 u-uu --uu

TRISJ PIC18F6X8X PIC18F8X8X 1111 1111 1111 1111 uuuu uuuu

TRISH PIC18F6X8X PIC18F8X8X 1111 1111 1111 1111 uuuu uuuu

TRISG PIC18F6X8X PIC18F8X8X ---1 1111 ---1 1111 ---u uuuu

TRISF PIC18F6X8X PIC18F8X8X 1111 1111 1111 1111 uuuu uuuu

TRISE PIC18F6X8X PIC18F8X8X 0000 -111 0000 -111 uuuu -uuu

TRISD PIC18F6X8X PIC18F8X8X 1111 1111 1111 1111 uuuu uuuu

TRISC PIC18F6X8X PIC18F8X8X 1111 1111 1111 1111 uuuu uuuu

TRISB PIC18F6X8X PIC18F8X8X 1111 1111 1111 1111 uuuu uuuu

TRISA(5,6) PIC18F6X8X PIC18F8X8X -111 1111(5) -111 1111(5) -uuu uuuu(5)

LATJ PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

LATH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

LATG PIC18F6X8X PIC18F8X8X ---x xxxx ---u uuuu ---u uuuu

LATF PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

LATE PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

LATD PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

LATC PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

LATB PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

LATA(5,6) PIC18F6X8X PIC18F8X8X -xxx xxxx(5) -uuu uuuu(5) -uuu uuuu(5)














PIC18F6585/8585/6680/8680

PORTJ PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

PORTH PIC18F6X8X PIC18F8X8X 0000 xxxx 0000 uuuu uuuu uuuu

PORTG PIC18F6X8X PIC18F8X8X --xx xxxx --uu uuuu --uu uuuu

PORTF PIC18F6X8X PIC18F8X8X x000 0000 u000 0000 u000 0000

PORTE PIC18F6X8X PIC18F8X8X ---- -000 ---- -000 ---- -uuu

PORTD PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

PORTC PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

PORTB PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

PORTA(5,6) PIC18F6X8X PIC18F8X8X -x0x 0000(5) -u0u 0000(5) -uuu uuuu(5)

SPBRGH PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

BAUDCON PIC18F6X8X PIC18F8X8X -1-0 0-00 -1-0 0-00 -u-u u-uu

ECCP1DEL PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

ECANCON PIC18F6X8X PIC18F8X8X 0001 0000 0001 0000 uuuu uuuu

TXERRCNT PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

RXERRCNT PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

COMSTAT PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

CIOCON PIC18F6X8X PIC18F8X8X 0000 ---- 0000 ---- uuuu ----

BRGCON3 PIC18F6X8X PIC18F8X8X 00-- -000 00-- -000 uu-- -uuu

BRGCON2 PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

BRGCON1 PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

CANCON PIC18F6X8X PIC18F8X8X 1000 000- 1000 000- uuuu uuu-

CANSTAT PIC18F6X8X PIC18F8X8X 100- 000- 100- 000- uuu- uuu-

RXB0D7 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu








RXB0DLC PIC18F6X8X PIC18F8X8X -xxx xxxx -uuu uuuu -uuu uuuu














PIC18F6585/8585/6680/8680

RXB0EIDL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

RXB0EIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

RXB0SIDL PIC18F6X8X PIC18F8X8X xxxx x-xx uuuu u-uu uuuu u-uu

RXB0SIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

RXB0CON PIC18F6X8X PIC18F8X8X 000- 0000 000- 0000 uuu- uuuu









RXB1DLC PIC18F6X8X PIC18F8X8X -xxx xxxx -uuu uuuu -uuu uuuu

RXB1EIDL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

RXB1EIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

RXB1SIDL PIC18F6X8X PIC18F8X8X xxxx x-xx uuuu u-uu uuuu u-uu

RXB1SIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

RXB1CON PIC18F6X8X PIC18F8X8X 000- 0000 000- 0000 uuu- uuuu

TXB0D7 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu








TXB0DLC PIC18F6X8X PIC18F8X8X -x-- xxxx -u-- uuuu -u-- uuuu

TXB0EIDL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

TXB0EIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu -uuu uuuu

TXB0SIDL PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- u-uu







Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.

4: See Table 3-2 for Reset value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’.7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.


PIC18F6585/8585/6680/8680

TXB0SIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

TXB0CON PIC18F6X8X PIC18F8X8X 0000 0-00 0000 0-00 uuuu u-uu











TXB1EIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

TXB1SIDL PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- uu-u

TXB1SIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu -uuu uuuu


TXB2D7 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu 0uuu uuuu










TXB2EIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

TXB2SIDL PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- u-uu

TXB2SIDH PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- u-uu


RXM1EIDL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu














PIC18F6585/8585/6680/8680

RXM1EIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

RXM1SIDL PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- u-uu

RXM1SIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

RXM0EIDL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

RXM0EIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

RXM0SIDL PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- u-uu

RXM0SIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

RXF5EIDL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

RXF5EIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

RXF5SIDL PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- u-uu

RXF5SIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu


































PIC18F6585/8585/6680/8680

B5D7(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu








B5DLC(7) PIC18F6X8X PIC18F8X8X -xxx xxxx -uuu uuuu -uuu uuuu

B5EIDL(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

B5EIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

B5SIDL(7) PIC18F6X8X PIC18F8X8X xxxx x-xx uuuu u-uu uuuu u-uu

B5SIDH(7) PIC18F6X8X PIC18F8X8X xxxx x-xx uuuu u-uu uuuu u-uu

B5CON(7) PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu













B4SIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu


















PIC18F6585/8585/6680/8680













































PIC18F6585/8585/6680/8680























TXBIE(7) PIC18F6X8X PIC18F8X8X ---0 00-- ---u uu-- ---u uu--

BIE0(7) PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

BSEL0(7) PIC18F6X8X PIC18F8X8X 0000 00-- 0000 00-- uuuu uu--

MSEL3(7) PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu




SDFLC(7) PIC18F6X8X PIC18F8X8X ---0 0000 ---0 0000 -u-- uuuu

RXFCON1(7) PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu














PIC18F6585/8585/6680/8680

RXFCON0(7) PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu

RXFBCON7(7) PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu








RXF15EIDL(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

RXF15EIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

RXF15SIDL(7) PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- u-uu

RXF15SIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu

















RXF10EIDL(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu -uuu uuuu

RXF10EIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu -uuu uuuu














PIC18F6585/8585/6680/8680

RXF10SIDL(7) PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu -uuu uuuu

RXF10SIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu -uuu uuuu






























PIC18F6585/8585/6680/8680

FIGURE 3-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD VIA 1 kΩ RESISTOR)

FIGURE 3-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST


PIC18F6585/8585/6680/8680

FIGURE 3-6: SLOW RISE TIME (MCLR TIED TO VDD VIA 1 kΩ RESISTOR)

FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD VIA 1 kΩ RESISTOR)

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

0V 1V

5V

TPWRT

TOST

TPWRT

TOST

VDD

MCLR

IINTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

PLL TIME-OUT

TPLL

Note: TOST = 1024 clock cycles.TPLL ≈ 2 ms max. First three stages of the PWRT timer.


PIC18F6585/8585/6680/8680

4.0 MEMORY ORGANIZATION

There are three memory blocks inPIC18F6585/8585/6680/8680 devices. They are:

• Program Memory

• Data RAM • Data EEPROM

Data and program memory use separate busses whichallows for concurrent access of these blocks. Additionaldetailed information for Flash program memory and dataEEPROM is provided in Section 5.0 “Flash ProgramMemory” and Section 7.0 “Data EEPROM Memory”,respectively.

In addition to on-chip Flash, the PIC18F8X8X devicesare also capable of accessing external program mem-ory through an external memory bus. Depending on theselected operating mode (discussed in Section 4.1.1“PIC18F8X8X Program Memory Modes”), thecontrollers may access either internal or external pro-gram memory exclusively, or both internal and externalmemory in selected blocks. Additional information onthe external memory interface is provided inSection 6.0 “External Memory Interface”.

4.1 Program Memory Organization

A 21-bit program counter is capable of addressing the2-Mbyte program memory space. Accessing a locationbetween the physically implemented memory and the2-Mbyte address will cause a read of all ‘0’s (a NOPinstruction).

The PIC18F6585 and PIC18F8585 each have48 Kbytes of on-chip Flash memory, while thePIC18F6680 and PIC18F8680 have 64 Kbytes of Flash.This means that PIC18FX585 devices can store inter-nally up to 24,576 single-word instructions andPIC18FX680 devices can store up to 32,768 single-wordinstructions.

The Reset vector address is at 0000h and the interruptvector addresses are at 0008h and 0018h.

Figure 4-1 shows the program memory map forPIC18F6585/8585 devices while Figure 4-2 shows theprogram memory map for PIC18F6680/8680 devices.

4.1.1 PIC18F8X8X PROGRAM MEMORY MODES

PIC18F8X8X devices differ significantly from theirPIC18 predecessors in their utilization of programmemory. In addition to available on-chip Flash programmemory, these controllers can also address up to2 Mbytes of external program memory through theexternal memory interface. There are four distinctoperating modes available to the controllers:

• Microprocessor (MP)

• Microprocessor with Boot Block (MPBB)• Extended Microcontroller (EMC)• Microcontroller (MC)

The Program Memory mode is determined by settingthe two Least Significant bits of the CONFIG3L config-uration byte, as shown in Register 4-1. (See alsoSection 24.1 “Configuration Bits” for additionaldetails on the device configuration bits.)

The Program Memory modes operate as follows:

• The Microprocessor Mode permits access only to external program memory; the contents of the on-chip Flash memory are ignored. The 21-bit program counter permits access to a 2-MByte linear program memory space.

• The Microprocessor with Boot Block Mode accesses on-chip Flash memory from addresses 000000h to 0007FFh. Above this, external program memory is accessed all the way up to the 2-MByte limit. Program execution auto-matically switches between the two memories as required.

• The Microcontroller Mode accesses only on-chip Flash memory. Attempts to read above the physical limit of the on-chip Flash (0BFFFh for the PIC18F8585, 0FFFFh for the PIC18F8680) causes a read of all ‘0’s (a NOP instruction).The Microcontroller mode is the only operating mode available to PIC18F6X8X devices.

• The Extended Microcontroller Mode allows access to both internal and external program memories as a single block. The device can access its entire on-chip Flash memory; above this, the device accesses external program mem-ory up to the 2-MByte program space limit. As with Boot Block mode, execution automatically switches between the two memories as required.

In all modes, the microcontroller has complete accessto data RAM and EEPROM.

Figure 4-3 compares the memory maps of the differentProgram Memory modes. The differences between on-chip and external memory access limitations are morefully explained in Table 4-1.


PIC18F6585/8585/6680/8680

FIGURE 4-1: INTERNAL PROGRAM MEMORY MAP AND STACK FOR PIC18F6585/8585

FIGURE 4-2: INTERNAL PROGRAM MEMORY MAP AND STACK FOR PIC18F6680/8680

TABLE 4-1: MEMORY ACCESS FOR PIC18F8X8X PROGRAM MEMORY MODES

PC<20:0>

Stack Level 1•

Stack Level 31

Reset Vector

Low Priority Interrupt Vector

••

CALL,RCALL,RETURNRETFIE,RETLW

21

000000h

000018h

On-Chip FlashProgram Memory

High Priority Interrupt Vector 000008h

Use

r M

emor

y S

pace

1FFFFFh

00C000h00BFFFh

Read ‘0’

200000h

PC<20:0>

Stack Level 1•

Stack Level 31

Reset Vector

Low Priority Interrupt Vector

••

CALL,RCALL,RETURNRETFIE,RETLW

21

000000h

000018h

010000h

00FFFFh

On-Chip FlashProgram Memory

High Priority Interrupt Vector 000008h

Use

r M

emor

y S

pace

Read ‘0’

1FFFFFh200000h

Operating Mode

Internal Program Memory External Program Memory

ExecutionFrom

Table Read From

Table Write ToExecution

FromTable Read

FromTable Write To

Microprocessor No Access No Access No Access Yes Yes Yes

Microprocessor w/ Boot Block

Yes Yes Yes Yes Yes Yes

Microcontroller Yes Yes Yes No Access No Access No Access

Extended Microcontroller

Yes Yes Yes Yes Yes Yes

PIC18F6585/8585/6680/8680

REGISTER 4-1: CONFIG3L CONFIGURATION BYTE

FIGURE 4-3: MEMORY MAPS FOR PIC18F8X8X PROGRAM MEMORY MODES

R/P-1 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1

WAIT — — — — — PM1 PM0

bit 7 bit 0

bit 7 WAIT: External Bus Data Wait Enable bit1 = Wait selections unavailable, device will not wait 0 = Wait programmed by WAIT1 and WAIT0 bits of MEMCOM register (MEMCOM<5:4>)


bit 1-0 PM1:PM0: Processor Data Memory Mode Select bits11 = Microcontroller mode10 = Microprocessor mode01 = Microcontroller with Boot Block mode 00 = Extended Microcontroller mode

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’

- n = Value after erase ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MicroprocessorMode

000000h

1FFFFFh

ExternalProgramMemory


1FFFFFh

000000h

On-ChipProgramMemory

ExtendedMicrocontroller

Mode

MicrocontrollerMode

000000h

External On-Chip

Pro

gra

m S

pace

Exe

cuti

on


1FFFFFh

Reads

000800h

1FFFFFh

0007FFh

Microprocessorwith Boot Block

Mode

000000hOn-ChipProgramMemory


Memory Flash


(Noaccess)

‘0’s

010000h(2)

00FFFFh(2)

External On-ChipMemory Flash

On-ChipFlash

External On-ChipMemory Flash

00BFFFh(1)

00C000h(1)00FFFFh(2)00BFFFh(1)

010000h(2)00C000h(1)

Note 1: PIC18F6585 and PIC18F8585.2: PIC18F6680 and PIC18F8680.

PIC18F6585/8585/6680/8680

4.2 Return Address Stack

The return address stack allows any combination of upto 31 program calls and interrupts to occur. The PC(Program Counter) is pushed onto the stack when aCALL or RCALL instruction is executed or an interrupt isAcknowledged. The PC value is pulled off the stack ona RETURN, RETLW, or a RETFIE instruction. PCLATUand PCLATH are not affected by any of the RETURN orCALL instructions.

The stack operates as a 31-word by 21-bit RAM and a5-bit stack pointer, with the stack pointer initialized to00000b after all Resets. There is no RAM associatedwith stack pointer 00000b. This is only a Reset value.During a CALL type instruction causing a push onto thestack, the stack pointer is first incremented and theRAM location pointed to by the stack pointer is writtenwith the contents of the PC. During a RETURN typeinstruction causing a pop from the stack, the contentsof the RAM location pointed to by the STKPTR aretransferred to the PC and then the stack pointer isdecremented.

The stack space is not part of either program or dataspace. The stack pointer is readable and writable andthe address on the top of the stack is readable and writ-able through SFR registers. Data can also be pushedto or popped from the stack, using the top-of-stackSFRs. Status bits indicate if the stack pointer is at orbeyond the 31 levels provided.

4.2.1 TOP-OF-STACK ACCESS

The top of the stack is readable and writable. Threeregister locations, TOSU, TOSH and TOSL, hold thecontents of the stack location pointed to by theSTKPTR register. This allows users to implement asoftware stack if necessary. After a CALL, RCALL orinterrupt, the software can read the pushed value byreading the TOSU, TOSH and TOSL registers. Thesevalues can be placed on a user defined software stack.At return time, the software can replace the TOSU,TOSH and TOSL and do a return.

The user must disable the global interrupt enable bitsduring this time to prevent inadvertent stackoperations.

4.2.2 RETURN STACK POINTER (STKPTR)

The STKPTR register contains the stack pointer value,the STKFUL (Stack Full) status bit, and the STKUNF(Stack Underflow) status bits. Register 4-2 shows theSTKPTR register. The value of the stack pointer can be0 through 31. The stack pointer increments when valuesare pushed onto the stack and decrements when valuesare popped off the stack. At Reset, the stack pointervalue will be ‘0’. The user may read and write the stackpointer value. This feature can be used by a Real-TimeOperating System for return stack maintenance.

After the PC is pushed onto the stack 31 times (withoutpopping any values off the stack), the STKFUL bit isset. The STKFUL bit can only be cleared in software orby a POR.

The action that takes place when the stack becomesfull depends on the state of the STVREN (StackOverflow Reset Enable) configuration bit. Refer toSection 25.0 “Instruction Set Summary” for adescription of the device configuration bits. If STVRENis set (default), the 31st push will push the (PC + 2)value onto the stack, set the STKFUL bit and reset thedevice. The STKFUL bit will remain set and the stackpointer will be set to ‘0’.

If STVREN is cleared, the STKFUL bit will be set on the31st push and the stack pointer will increment to 31.Any additional pushes will not overwrite the 31st pushand STKPTR will remain at 31.

When the stack has been popped enough times tounload the stack, the next pop will return a value of zeroto the PC and sets the STKUNF bit while the stackpointer remains at ‘0’. The STKUNF bit will remain setuntil cleared in software or a POR occurs.

Note: Returning a value of zero to the PC on anunderflow has the effect of vectoring theprogram to the Reset vector, where thestack conditions can be verified andappropriate actions can be taken.


PIC18F6585/8585/6680/8680

REGISTER 4-2: STKPTR REGISTER

FIGURE 4-4: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS

4.2.3 PUSH AND POP INSTRUCTIONS

Since the Top-of-Stack (TOS) is readable and writable,the ability to push values onto the stack and pull valuesoff the stack, without disturbing normal program execu-tion, is a desirable option. To push the current PC valueonto the stack, a PUSH instruction can be executed.This will increment the stack pointer and load the cur-rent PC value onto the stack. TOSU, TOSH and TOSLcan then be modified to place a return address on thestack.

The ability to pull the TOS value off of the stack andreplace it with the value that was previously pushedonto the stack, without disturbing normal execution, isachieved by using the POP instruction. The POP instruc-tion discards the current TOS by decrementing thestack pointer. The previous value pushed onto thestack then becomes the TOS value.

4.2.4 STACK FULL/UNDERFLOW RESETS

These Resets are enabled by programming theSTVREN configuration bit. When the STVREN bit isdisabled, a full or underflow condition will set theappropriate STKFUL or STKUNF bit, but not cause adevice Reset. When the STVREN bit is enabled, a fullor underflow condition will set the appropriate STKFULor STKUNF bit and then cause a device Reset. TheSTKFUL or STKUNF bits are only cleared by the usersoftware or a POR Reset.

R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0

bit 7 bit 0

bit 7 STKFUL: Stack Full Flag bit1 = Stack became full or overflowed 0 = Stack has not become full or overflowed

bit 6 STKUNF: Stack Underflow Flag bit

1 = Stack underflow occurred 0 = Stack underflow did not occur

bit 5 Unimplemented: Read as ‘0’

bit 4-0 SP4:SP0: Stack Pointer Location bits

Note 1: Bit 7 and bit 6 can only be cleared in user software or by a POR.

Legend:

C = Clearable bit R = Readable bit U = Unimplemented bit, read as ‘0’ W = Writable bit


00011001A34h

111111111011101

000100000100000

00010

Return Address Stack

Top-of-Stack000D58h

TOSLTOSHTOSU34h1Ah00h

STKPTR<4:0>

PIC18F6585/8585/6680/8680

4.3 Fast Register Stack

A “fast interrupt return” option is available for interrupts.A fast register stack is provided for the Status, WREGand BSR registers and is only one in depth. The stackis not readable or writable and is loaded with thecurrent value of the corresponding register when theprocessor vectors for an interrupt. The values in theregisters are then loaded back into the working regis-ters if the FAST RETURN instruction is used to returnfrom the interrupt.

A low or high priority interrupt source will push valuesinto the stack registers. If both low and high priorityinterrupts are enabled, the stack registers cannot beused reliably for low priority interrupts. If a high priorityinterrupt occurs while servicing a low priority interrupt,the stack register values stored by the low priorityinterrupt will be overwritten.

If high priority interrupts are not disabled during lowpriority interrupts, users must save the key registers insoftware during a low priority interrupt.

If no interrupts are used, the fast register stack can beused to restore the Status, WREG and BSR registers atthe end of a subroutine call. To use the fast registerstack for a subroutine call, a FAST CALL instructionmust be executed.

Example 4-1 shows a source code example that usesthe fast register stack.

EXAMPLE 4-1: FAST REGISTER STACK CODE EXAMPLE

4.4 PCL, PCLATH and PCLATU

The program counter (PC) specifies the address of theinstruction to fetch for execution. The PC is 21 bitswide. The low byte is called the PCL register; this reg-ister is readable and writable. The high byte is calledthe PCH register. This register contains the PC<15:8>bits and is not directly readable or writable; updates tothe PCH register may be performed through thePCLATH register. The upper byte is called PCU. Thisregister contains the PC<20:16> bits and is not directlyreadable or writable; updates to the PCU register maybe performed through the PCLATU register.

The PC addresses bytes in the program memory. Toprevent the PC from becoming misaligned with wordinstructions, the LSB of the PCL is fixed to a value of‘0’. The PC increments by 2 to address sequentialinstructions in the program memory.

The CALL, RCALL, GOTO and program branchinstructions write to the program counter directly. Forthese instructions, the contents of PCLATH andPCLATU are not transferred to the program counter.

The contents of PCLATH and PCLATU will be trans-ferred to the program counter by an operation thatwrites PCL. Similarly, the upper two bytes of the pro-gram counter will be transferred to PCLATH andPCLATU by an operation that reads PCL. This is usefulfor computed offsets to the PC (see Section 4.8.1“Computed GOTO”).

4.5 Clocking Scheme/Instruction Cycle

The clock input (from OSC1) is internally divided byfour to generate four non-overlapping quadratureclocks, namely Q1, Q2, Q3 and Q4. Internally, theprogram counter (PC) is incremented every Q1, theinstruction is fetched from the program memory andlatched into the instruction register in Q4. The instruc-tion is decoded and executed during the following Q1through Q4. The clocks and instruction execution floware shown in Figure 4-5.

FIGURE 4-5: CLOCK/INSTRUCTION CYCLE

CALL SUB1, FAST ;STATUS, WREG, BSR;SAVED IN FAST REGISTER;STACK

••

SUB1 •••

RETURN FAST ;RESTORE VALUES SAVED;IN FAST REGISTER STACK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

Q1

Q2

Q3

Q4

PC

OSC2/CLKO(RC Mode)

PC PC+2 PC+4

Fetch INST (PC)Execute INST (PC-2)

Fetch INST (PC+2)Execute INST (PC)

Fetch INST (PC+4)Execute INST (PC+2)

InternalPhaseClock

PIC18F6585/8585/6680/8680

4.6 Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1,Q2, Q3 and Q4). The instruction fetch and execute arepipelined such that fetch takes one instruction cycle,while decode and execute takes another instructioncycle. However, due to the pipelining each instructioneffectively executes in one cycle. If an instructioncauses the program counter to change (e.g., GOTO),then two cycles are required to complete the instruction(Example 4-2).

A fetch cycle begins with the program counter (PC)incrementing in Q1.

In the execution cycle, the fetched instruction is latchedinto the “Instruction Register” (IR) in cycle Q1. Thisinstruction is then decoded and executed during theQ2, Q3, and Q4 cycles. Data memory is read during Q2(operand read) and written during Q4 (destinationwrite).

EXAMPLE 4-2: INSTRUCTION PIPELINE FLOW

4.7 Instructions in Program Memory

The program memory is addressed in bytes. Instruc-tions are stored as two bytes or four bytes in programmemory. The Least Significant Byte (LSB) of aninstruction word is always stored in a program memorylocation with an even address (LSB = 0). Figure 4-6shows an example of how instruction words are storedin the program memory. To maintain alignment withinstruction boundaries, the PC increments in steps of 2and the LSB will always read ‘0’ (see Section 4.4“PCL, PCLATH and PCLATU”).

The CALL and GOTO instructions have an absolute pro-gram memory address embedded into the instruction.Since instructions are always stored on word bound-aries, the data contained in the instruction is a wordaddress. The word address is written to PC<20:1>which accesses the desired byte address in programmemory. Instruction #2 in Figure 4-6 shows how theinstruction “GOTO 000006h” is encoded in the programmemory. Program branch instructions which encode arelative address offset operate in the same manner.The offset value stored in a branch instruction repre-sents the number of single-word instructions that thePC will be offset by. Section 25.0 “Instruction SetSummary” provides further details of the instructionset.

FIGURE 4-6: INSTRUCTIONS IN PROGRAM MEMORY

All instructions are single cycle except for any program branches. These take two cycles since the fetch instructionis “flushed” from the pipeline while the new instruction is being fetched and then executed.

TCY0 TCY1 TCY2 TCY3 TCY4 TCY5

1. MOVLW 55h Fetch 1 Execute 1

2. MOVWF PORTB Fetch 2 Execute 2

3. BRA SUB_1 Fetch 3 Execute 3

4. BSF PORTA, 3 (Forced NOP) Fetch 4 Flush (NOP)

5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1

Word AddressLSB = 1 LSB = 0 ↓

Program MemoryByte Locations →

000000h000002h000004h000006h

Instruction 1: MOVLW 055h 0Fh 55h 000008hInstruction 2: GOTO 000006h 0EFh 03h 00000Ah

0F0h 00h 00000ChInstruction 3: MOVFF 123h, 456h 0C1h 23h 00000Eh

0F4h 56h 000010h000012h000014h

PIC18F6585/8585/6680/8680

4.7.1 TWO-WORD INSTRUCTIONS

The PIC18F6585/8585/6680/8680 devices have fourtwo-word instructions: MOVFF, CALL, GOTO andLFSR. The second word of these instructions has the 4MSBs set to ‘1’s and is a special kind of NOP instruction.The lower 12 bits of the second word contain data to beused by the instruction. If the first word of the instruc-tion is executed, the data in the second word is

accessed. If the second word of the instruction is exe-cuted by itself (first word was skipped), it will execute asa NOP. This action is necessary when the two-wordinstruction is preceded by a conditional instruction thatchanges the PC. A program example that demon-strates this concept is shown in Example 4-3. Refer toSection 25.0 “Instruction Set Summary” for furtherdetails of the instruction set.

EXAMPLE 4-3: TWO-WORD INSTRUCTIONS

4.8 Look-up Tables

Look-up tables are implemented two ways. These are:

• Computed GOTO • Table Reads

4.8.1 COMPUTED GOTO

A computed GOTO is accomplished by adding an offsetto the program counter (ADDWF PCL).

A look-up table can be formed with an ADDWF PCLinstruction and a group of RETLW 0xnn instructions.WREG is loaded with an offset into the table beforeexecuting a call to that table. The first instruction of thecalled routine is the ADDWF PCL instruction. The nextinstruction executed will be one of the RETLW 0xnninstructions that returns the value 0xnn to the callingfunction.

The offset value (value in WREG) specifies the numberof bytes that the program counter should advance.

In this method, only one data byte may be stored ineach instruction location and room on the returnaddress stack is required.

4.8.2 TABLE READS/TABLE WRITES

A better method of storing data in program memoryallows 2 bytes of data to be stored in each instructionlocation.

Look-up table data may be stored 2 bytes per programword by using table reads and writes. The Table Pointer(TBLPTR) specifies the byte address and the TableLatch (TABLAT) contains the data that is read from, orwritten to program memory. Data is transferred to/fromprogram memory, one byte at a time.

A description of the table read/table write operation isshown in Section 5.0 “Flash Program Memory”.

CASE 1:

Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?

1100 0001 0010 0011 MOVFF REG1, REG2 ; No, execute 2-word instruction

1111 0100 0101 0110 ; 2nd operand holds address of REG2

0010 0100 0000 0000 ADDWF REG3 ; continue code

CASE 2:

Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?

1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes

1111 0100 0101 0110 ; 2nd operand becomes NOP

0010 0100 0000 0000 ADDWF REG3 ; continue code


PIC18F6585/8585/6680/8680

4.9 Data Memory Organization

The data memory is implemented as static RAM. Eachregister in the data memory has a 12-bit address,allowing up to 4096 bytes of data memory. Figure 4-7shows the data memory organization for thePIC18F6585/8585/6680/8680 devices.

The data memory map is divided into 16 banks thatcontain 256 bytes each. The lower 4 bits of the BankSelect Register (BSR<3:0>) select which bank will beaccessed. The upper 4 bits for the BSR are notimplemented.

The data memory contains Special Function Registers(SFR) and General Purpose Registers (GPR). TheSFRs are used for control and status of the controllerand peripheral functions, while GPRs are used for datastorage and scratch pad operations in the user’s appli-cation. The SFRs start at the last location of Bank 15(0FFFh) and extend downwards. Any remaining spacebeyond the SFRs in the Bank may be implemented asGPRs. GPRs start at the first location of Bank 0 andgrow upwards. Any read of an unimplemented locationwill read as ‘0’s.

The entire data memory may be accessed directly orindirectly. Direct addressing may require the use of theBSR register. Indirect addressing requires the use of aFile Select Register (FSRn) and a corresponding Indi-rect File Operand (INDFn). Each FSR holds a 12-bitaddress value that can be used to access any locationin the data memory map without banking.

The instruction set and architecture allow operationsacross all banks. This may be accomplished by indirectaddressing or by the use of the MOVFF instruction. TheMOVFF instruction is a two-word/two-cycle instructionthat moves a value from one register to another.

To ensure that commonly used registers (SFRs andselect GPRs) can be accessed in a single cycle regard-less of the current BSR values, an Access Bank isimplemented. A segment of Bank 0 and a segment ofBank 15 comprise the Access RAM. Section 4.10“Access Bank” provides a detailed description of theAccess RAM.

4.9.1 GENERAL PURPOSE REGISTER FILE

The register file can be accessed either directly or indi-rectly. Indirect addressing operates using a File SelectRegister and corresponding Indirect File Operand. Theoperation of indirect addressing is shown inSection 4.12 “Indirect Addressing, INDF and FSRRegisters”.

Enhanced MCU devices may have banked memory inthe GPR area. GPRs are not initialized by a Power-onReset and are unchanged on all other Resets.

Data RAM is available for use as general purpose regis-ters by all instructions. The top section of Bank 15(0F60h to 0FFFh) contains SFRs. All other banks of datamemory contain GPR registers, starting with Bank 0.

4.9.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registersused by the CPU and peripheral modules for controllingthe desired operation of the device. These registers areimplemented as static RAM. A list of these registers isgiven in Table 4-2 and Table 4-3.

The SFRs can be classified into two sets: those asso-ciated with the “core” function and those related to theperipheral functions. Those registers related to the“core” are described in this section, while those relatedto the operation of the peripheral features aredescribed in the section of that peripheral feature. TheSFRs are typically distributed among the peripheralswhose functions they control.

The unused SFR locations are unimplemented andread as ‘0’s. The addresses for the SFRs are listed inTable 4-2.

PIC18F6585/8585/6680/8680

FIGURE 4-7: DATA MEMORY MAP FOR PIC18FXX80/XX85 DEVICES

Bank 0

Bank 1

Bank 12

Bank 15

Data Memory MapBSR<3:0>

= 0000

= 0001

= 1110

= 1111

060h05Fh

F60hFFFh

00h5Fh60h

FFh

Access Bank

When a = 0, the BSR is ignored and theAccess Bank is used. The first 96 bytes are GeneralPurpose RAM (from Bank 0). The second 160 bytes are Special Function Registers(from Bank 15).

When a = 1, the BSR is used to specify theRAM location that the instructionuses.

Bank 4

Bank 3

Bank 2

F5FhF00hEFFh

3FFh

300h2FFh

200h1FFh

100h0FFh

000h

= 0011

= 0010

Access RAM

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

GPRs

GPRs

GPRs

GPRs

SFRs

CAN SFRs

Access RAM high

Access RAM low

Bank 14

GPRs

CAN SFRs

Bank 5to

4FFh

400h

DFFh

500h

E00h

= 0100

(SFRs)

GPRs

CAN SFRs

D00hCFFh

Bank 13= 1101

PIC18F6585/8585/6680/8680

TABLE 4-2: SPECIAL FUNCTION REGISTER MAP

Address Name Address Name Address Name Address Name

FFFh TOSU FDFh INDF2(3) FBFh CCPR1H F9Fh IPR1

FFEh TOSH FDEh POSTINC2(3) FBEh CCPR1L F9Eh PIR1

FFDh TOSL FDDh POSTDEC2(3) FBDh CCP1CON F9Dh PIE1

FFCh STKPTR FDCh PREINC2(3) FBCh CCPR2H F9Ch MEMCON(2)

FFBh PCLATU FDBh PLUSW2(3) FBBh CCPR2L F9Bh —(1)

FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah TRISJ(2)

FF9h PCL FD9h FSR2L FB9h —(1) F99h TRISH(2)

FF8h TBLPTRU FD8h STATUS FB8h —(1) F98h TRISG

FF7h TBLPTRH FD7h TMR0H FB7h —(1) F97h TRISF

FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS F96h TRISE

FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD

FF4h PRODH FD4h —(1) FB4h CMCON F94h TRISC

FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB

FF2h INTCON FD2h LVDCON FB2h TMR3L F92h TRISA

FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h LATJ(2)

FF0h INTCON3 FD0h RCON FB0h PSPCON F90h LATH(2)

FEFh INDF0(3) FCFh TMR1H FAFh SPBRG F8Fh LATG

FEEh POSTINC0(3) FCEh TMR1L FAEh RCREG F8Eh LATF

FEDh POSTDEC0(3) FCDh T1CON FADh TXREG F8Dh LATE

FECh PREINC0(3) FCCh TMR2 FACh TXSTA F8Ch LATD

FEBh PLUSW0(3) FCBh PR2 FABh RCSTA F8Bh LATC

FEAh FSR0H FCAh T2CON FAAh EEADRH F8Ah LATB

FE9h FSR0L FC9h SSPBUF FA9h EEADR F89h LATA

FE8h WREG FC8h SSPADD FA8h EEDATA F88h PORTJ(2)

FE7h INDF1(3) FC7h SSPSTAT FA7h EECON2 F87h PORTH(2)

FE6h POSTINC1(3) FC6h SSPCON1 FA6h EECON1 F86h PORTG

FE5h POSTDEC1(3) FC5h SSPCON2 FA5h IPR3 F85h PORTF

FE4h PREINC1(3) FC4h ADRESH FA4h PIR3 F84h PORTE

FE3h PLUSW1(3) FC3h ADRESL FA3h PIE3 F83h PORTD

FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC

FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB

FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA

Note 1: Unimplemented registers are read as ‘0’.2: This register is not available on PIC18F6X8X devices.3: This is not a physical register.


PIC18F6585/8585/6680/8680


F7Fh SPBRGH F5Fh CANCON_RO0 F3Fh CANCON_RO2 F1Fh RXM1EIDL

F7Eh BAUDCON F5Eh CANSTAT_RO0 F3Eh CANSTAT_RO2 F1Eh RXM1EIDH

F7Dh —(1) F5Dh RXB1D7 F3Dh TXB1D7 F1Dh RXM1SIDL

F7Ch —(1) F5Ch RXB1D6 F3Ch TXB1D6 F1Ch RXM1SIDH

F7Bh —(1) F5Bh RXB1D5 F3Bh TXB1D5 F1Bh RXM0EIDL

F7Ah —(1) F5Ah RXB1D4 F3Ah TXB1D4 F1Ah RXM0EIDH

F79h ECCP1DEL F59h RXB1D3 F39h TXB1D3 F19h RXM0SIDL

F78h —(1) F58h RXB1D2 F38h TXB1D2 F18h RXM0SIDH

F77h ECANCON F57h RXB1D1 F37h TXB1D1 F17h RXF5EIDL

F76h TXERRCNT F56h RXB1D0 F36h TXB1D0 F16h RXF5EIDH

F75h RXERRCNT F55h RXB1DLC F35h TXB1DLC F15h RXF5SIDL

F74h COMSTAT F54h RXB1EIDL F34h TXB1EIDL F14h RXF5SIDH

F73h CIOCON F53h RXB1EIDH F33h TXB1EIDH F13h RXF4EIDL

F72h BRGCON3 F52h RXB1SIDL F32h TXB1SIDL F12h RXF4EIDH

F71h BRGCON2 F51h RXB1SIDH F31h TXB1SIDH F11h RXF4SIDL

F70h BRGCON1 F50h RXB1CON F30h TXB1CON F10h RXF4SIDH

F6Fh CANCON F4Fh CANCON_RO1 F2Fh CANCON_RO3 F0Fh RXF3EIDL

F6Eh CANSTAT F4Eh CANSTAT_RO1 F2Eh CANSTAT_RO3 F0Eh RXF3EIDH

F6Dh RXB0D7 F4Dh TXB0D7 F2Dh TXB2D7 F0Dh RXF3SIDL

F6Ch RXB0D6 F4Ch TXB0D6 F2Ch TXB2D6 F0Ch RXF3SIDH

F6Bh RXB0D5 F4Bh TXB0D5 F2Bh TXB2D5 F0Bh RXF2EIDL

F6Ah RXB0D4 F4Ah TXB0D4 F2Ah TXB2D4 F0Ah RXF2EIDH

F69h RXB0D3 F49h TXB0D3 F29h TXB2D3 F09h RXF2SIDL

F68h RXB0D2 F48h TXB0D2 F28h TXB2D2 F08h RXF2SIDH

F67h RXB0D1 F47h TXB0D1 F27h TXB2D1 F07h RXF1EIDL

F66h RXB0D0 F46h TXB0D0 F26h TXB2D0 F06h RXF1EIDH

F65h RXB0DLC F45h TXB0DLC F25h TXB2DLC F05h RXF1SIDL

F64h RXB0EIDL F44h TXB0EIDL F24h TXB2EIDL F04h RXF1SIDH

F63h RXB0EIDH F43h TXB0EIDH F23h TXB2EIDH F03h RXF0EIDL

F62h RXB0SIDL F42h TXB0SIDL F22h TXB2SIDL F02h RXF0EIDH

F61h RXB0SIDH F41h TXB0SIDH F21h TXB2SIDH F01h RXF0SIDL

F60h RXB0CON F40h TXB0CON F20h TXB2CON F00h RXF0SIDH

TABLE 4-2: SPECIAL FUNCTION REGISTER MAP (CONTINUED)



PIC18F6585/8585/6680/8680


EFFh —(1) EDFh —(1) EBFh —(1) E9Fh —(1)

EFEh —(1) EDEh —(1) EBEh —(1) E9Eh —(1)

EFDh —(1) EDDh —(1) EBDh —(1) E9Dh —(1)

EFCh —(1) EDCh —(1) EBCh —(1) E9Ch —(1)

EFBh —(1) EDBh —(1) EBBh —(1) E9Bh —(1)

EFAh —(1) EDAh —(1) EBAh —(1) E9Ah —(1)

EF9h —(1) ED9h —(1) EB9h —(1) E99h —(1)

EF8h —(1) ED8h —(1) EB8h —(1) E98h —(1)

EF7h —(1) ED7h —(1) EB7h —(1) E97h —(1)

EF6h —(1) ED6h —(1) EB6h —(1) E96h —(1)

EF5h —(1) ED5h —(1) EB5h —(1) E95h —(1)

EF4h —(1) ED4h —(1) EB4h —(1) E94h —(1)

EF3h —(1) ED3h —(1) EB3h —(1) E93h —(1)

EF2h —(1) ED2h —(1) EB2h —(1) E92h —(1)

EF1h —(1) ED1h —(1) EB1h —(1) E91h —(1)

EF0h —(1) ED0h —(1) EB0h —(1) E90h —(1)

EEFh —(1) ECFh —(1) EAFh —(1) E8Fh —(1)

EEEh —(1) ECEh —(1) EAEh —(1) E8Eh —(1)

EEDh —(1) ECDh —(1) EADh —(1) E8Dh —(1)

EECh —(1) ECCh —(1) EACh —(1) E8Ch —(1)

EEBh —(1) ECBh —(1) EABh —(1) E8Bh —(1)

EEAh —(1) ECAh —(1) EAAh —(1) E8Ah —(1)

EE9h —(1) EC9h —(1) EA9h —(1) E89h —(1)

EE8h —(1) EC8h —(1) EA8h —(1) E88h —(1)

EE7h —(1) EC7h —(1) EA7h —(1) E87h —(1)

EE6h —(1) EC6h —(1) EA6h —(1) E86h —(1)

EE5h —(1) EC5h —(1) EA5h —(1) E85h —(1)

EE4h —(1) EC4h —(1) EA4h —(1) E84h —(1)

EE3h —(1) EC3h —(1) EA3h —(1) E83h —(1)

EE2h —(1) EC2h —(1) EA2h —(1) E82h —(1)

EE1h —(1) EC1h —(1) EA1h —(1) E81h —(1)

EE0h —(1) EC0h —(1) EA0h —(1) E80h —(1)




PIC18F6585/8585/6680/8680


E7Fh CANCON_RO4 E5Fh CANCON_RO6 E3Fh CANCON_RO8 E1Fh —(1)

E7Eh CANSTAT_RO4 E5Eh CANSTAT_RO6 E3Eh CANSTAT_RO8 E1Eh —(1)

E7Dh B5D7 E5Dh B3D7 E3Dh B1D7 E1Dh —(1)

E7Ch B5D6 E5Ch B3D6 E3Ch B1D6 E1Ch —(1)

E7Bh B5D5 E5Bh B3D5 E3Bh B1D5 E1Bh —(1)

E7Ah B5D4 E5Ah B3D4 E3Ah B1D4 E1Ah —(1)

E79h B5D3 E59h B3D3 E39h B1D3 E19h —(1)

E78h B5D2 E58h B3D2 E38h B1D2 E18h —(1)

E77h B5D1 E57h B3D1 E37h B1D1 E17h —(1)

E76h B5D0 E56h B3D0 E36h B1D0 E16h —(1)

E75h B5DLC E55h B3DLC E35h B1DLC E15h —(1)

E74h B5EIDL E54h B3EIDL E34h B1EIDL E14h —(1)

E73h B5EIDH E53h B3EIDH E33h B1EIDH E13h —(1)

E72h B5SIDL E52h B3SIDL E32h B1SIDL E12h —(1)

E71h B5SIDH E51h B3SIDH E31h B1SIDH E11h —(1)

E70h B5CON E50h B3CON E30h B1CON E10h —(1)







E69h B4D3 E49h B2D3 E29h B0D3 E09h —(1)

E68h B4D2 E48h B2D2 E28h B0D2 E08h —(1)

E67h B4D1 E47h B2D1 E27h B0D1 E07h —(1)

E66h B4D0 E46h B2D0 E26h B0D0 E06h —(1)










PIC18F6585/8585/6680/8680


DFFh —(1) DDFh —(1) DBFh —(1) D9Fh —(1)

DFEh —(1) DDEh —(1) DBEh —(1) D9Eh —(1)

DFDh —(1) DDDh —(1) DBDh —(1) D9Dh —(1)

DFCh TXBIE DDCh —(1) DBCh —(1) D9Ch —(1)

DFBh —(1) DDBh —(1) DBBh —(1) D9Bh —(1)

DFAh BIE0 DDAh —(1) DBAh —(1) D9Ah —(1)

DF9h —(1) DD9h —(1) DB9h —(1) D99h —(1)

DF8h BSEL0 DD8h SDFLC DB8h —(1) D98h —(1)

DF7h —(1) DD7h —(1) DB7h —(1) D97h —(1)

DF6h —(1) DD6h —(1) DB6h —(1) D96h —(1)

DF5h —(1) DD5h RXFCON1 DB5h —(1) D95h —(1)


DF3h MSEL3 DD3h —(1) DB3h —(1) D93h RXF15EIDL

DF2h MSEL2 DD2h —(1) DB2h —(1) D92h RXF15EIDH

DF1h MSEL1 DD1h —(1) DB1h —(1) D91h RXF15SIDL

DF0h MSEL0 DD0h —(1) DB0h —(1) D90h RXF15SIDH

DEFh —(1) DCFh —(1) DAFh —(1) D8Fh —(1)

DEEh —(1) DCEh —(1) DAEh —(1) D8Eh —(1)

DEDh —(1) DCDh —(1) DADh —(1) D8Dh —(1)

DECh —(1) DCCh —(1) DACh —(1) D8Ch —(1)

DEBh —(1) DCBh —(1) DABh —(1) D8Bh RXF14EIDL

DEAh —(1) DCAh —(1) DAAh —(1) D8Ah RXF14EIDH

DE9h —(1) DC9h —(1) DA9h —(1) D89h RXF14SIDL

DE8h —(1) DC8h —(1) DA8h —(1) D88h RXF14SIDH

DE7h RXFBCON7 DC7h —(1) DA7h —(1) D87h RXF13EIDL

DE6h RXFBCON6 DC6h —(1) DA6h —(1) D86h RXF13EIDH

DE5h RXFBCON5 DC5h —(1) DA5h —(1) D85h RXF13SIDL

DE4h RXFBCON4 DC4h —(1) DA4h —(1) D84h RXF13SIDH

DE3h RXFBCON3 DC3h —(1) DA3h —(1) D83h RXF12EIDL

DE2h RXFBCON2 DC2h —(1) DA2h —(1) D82h RXF12EIDH

DE1h RXFBCON1 DC1h —(1) DA1h —(1) D81h RXF12SIDL

DE0h RXFBCON0 DC0h —(1) DA0h —(1) D80h RXF12SIDH




PIC18F6585/8585/6680/8680


D7Fh —(1)

D7Eh —(1)

D7Dh —(1)

D7Ch —(1)

D7Bh RXF11EIDL

D7Ah RXF11EIDH

D79h RXF11SIDL

D78h RXF11SIDH

D77h RXF10EIDL

D76h RXF10EIDH

D75h RXF10SIDL

D74h RXF10SIDH

D73h RXF9EIDL

D72h RXF9EIDH

D71h RXF9SIDL

D70h RXF9SIDH

D6Fh —(1)

D6Eh —(1)

D6Dh —(1)

D6Ch —(1)

D6Bh RXF8EIDL

D6Ah RXF8EIDH

D69h RXF8SIDL

D68h RXF8SIDH

D67h RXF7EIDL

D66h RXF7EIDH

D65h RXF7SIDL

D64h RXF7SIDH

D63h RXF6EIDL

D62h RXF6EIDH

D61h RXF6SIDL

D60h RXF6SIDH




PIC18F6585/8585/6680/8680

TABLE 4-3: REGISTER FILE SUMMARY

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Value on

POR, BORDetails

on page:

TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 36, 54

TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 36, 54

TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 36, 54

STKPTR STKFUL STKUNF — Return Stack Pointer 00-0 0000 36, 55

PCLATU — — bit 21 Holding Register for PC<20:16> --00 0000 36, 56

PCLATH Holding Register for PC<15:8> 0000 0000 36, 56

PCL PC Low Byte (PC<7:0>) 0000 0000 36, 56

TBLPTRU — — bit 21(2) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 36, 86

TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 36, 86

TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 36, 86

TABLAT Program Memory Table Latch 0000 0000 36, 86

PRODH Product Register High Byte xxxx xxxx 36, 107

PRODL Product Register Low Byte xxxx xxxx 36, 107

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 36, 111

INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 36, 112

INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 36, 113

INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) n/a 79

POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) n/a 79

POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) n/a 79

PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) n/a 79

PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – value of FSR0 offset by value in WREG

n/a 79

FSR0H — — — — Indirect Data Memory Address Pointer 0 High Byte ---- 0000 36, 79

FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 36, 79

WREG Working Register xxxx xxxx 36






n/a 79



BSR — — — — Bank Select Register ---- 0000 37, 78






n/a 79



Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on conditionNote 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator

modes.2: Bit 21 of the TBLPTRU allows access to the device configuration bits.3: These registers are unused on PIC18F6X80 devices; always maintain these clear.4: These bits have multiple functions depending on the CAN module mode selection.5: Meaning of this register depends on whether this buffer is configured as transmit or receive.6: RG5 is available as an input when MCLR is disabled.7: This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2.

PIC18F6585/8585/6680/8680

STATUS — — — N OV Z DC C ---x xxxx 37, 81

TMR0H Timer0 Register High Byte 0000 0000 37, 157

TMR0L Timer0 Register Low Byte xxxx xxxx 37, 157

T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 37, 155

OSCCON — — — — LOCK PLLEN SCS1 SCS ---- 0000 27, 37

LVDCON — — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 37, 271

WDTCON — — — — — — — SWDTE ---- ---0 37, 355

RCON IPEN — — RI TO PD POR BOR 0--1 11qq 37, 82, 123

TMR1H Timer1 Register High Byte xxxx xxxx 37, 159


T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 37, 159

TMR2 Timer2 Register 0000 0000 37, 162

PR2 Timer2 Period Register 1111 1111 37, 163

T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 37, 162

SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 37, 189

SSPADD SSP Address Register in I2C Slave mode. SSP Baud Rate Reload Register in I2C Master mode. 0000 0000 37, 198

SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 37, 199

SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 37, 191

SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 37, 201

ADRESH A/D Result Register High Byte xxxx xxxx 38, 257

ADRESL A/D Result Register Low Byte xxxx xxxx 38, 257

ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 38, 249

ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 38, 257

ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 38, 251

CCPR1H Enhanced Capture/Compare/PWM Register 1 High Byte xxxx xxxx 38, 173

CCPR1L Enhanced Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 38, 172

CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 38, 172

CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 38, 172

CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 38, 172

CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 38, 172

ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 38, 172

CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 38, 265

CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 38, 259

TMR3H Timer3 Register High Byte xxxx xxxx 38, 164


T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 38, 164

PSPCON IBF OBF IBOV PSPMODE — — — — 0000 ---- 38, 153

TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED)


POR, BORDetails

on page:




PIC18F6585/8585/6680/8680

SPBRG USART Baud Rate Generator 0000 0000 38, 239

RCREG USART Receive Register 0000 0000 38, 241

TXREG USART Transmit Register 0000 0000 38, 239

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 38, 230

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 38, 231

EEADRH — — — — — — EE Adr Register High ---- --00 38, 105

EEADR Data EEPROM Address Register 0000 0000 38, 105

EEDATA Data EEPROM Data Register 0000 0000 38, 105

EECON2 Data EEPROM Control Register 2 (not a physical register) ---- ---- 38, 105

EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 00-0 x000 38, 102

IPR3 IRXIP WAKIP ERRIP TXB2IP/TXBnIP

TXB1IP TXB0IP RXB1IP/RXBnIP

RXB0IP/FIFOWMIP

1111 1111 39, 122

PIR3 IRXIF WAKIF ERRIF TXB2IF/TXBnIF

TXB1IF TXB0IF RXB1IF/RXBnIF

RXB0IF/FIFOWMIF

0000 0000 39, 116

PIE3 IRXIE WAKIE ERRIE TXB2IE/TXBnIE

TXB1IE TXB0IE RXB1IE/RXBnIE

RXB0IE/FIFOWMIE

0000 0000 39, 119

IPR2 — CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 39, 121

PIR2 — CMIF — EEIF BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 39, 115

PIE2 — CMIE — EEIE BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 39, 118

IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 39, 120

PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 39, 114

PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 39, 117

MEMCON(3) EBDIS — WAIT1 WAIT0 — — WM1 WM0 0-00 --00 39, 94

TRISJ(3) Data Direction Control Register for PORTJ 1111 1111 39, 151

TRISH(3) Data Direction Control Register for PORTH 1111 1111 39, 148

TRISG — — — Data Direction Control Register for PORTG ---1 1111 39, 145

TRISF Data Direction Control Register for PORTF 1111 1111 39, 141

TRISE Data Direction Control Register for PORTE 1111 1111 39, 138

TRISD Data Direction Control Register for PORTD 1111 1111 39, 135

TRISC Data Direction Control Register for PORTC 1111 1111 39, 131

TRISB Data Direction Control Register for PORTB 1111 1111 39, 128

TRISA — TRISA6(1) Data Direction Control Register for PORTA -111 1111 39, 125

LATJ(3) Read PORTJ Data Latch, Write PORTJ Data Latch xxxx xxxx 39, 151

LATH(3) Read PORTH Data Latch, Write PORTH Data Latch xxxx xxxx 39, 148

LATG — — — Read PORTG Data Latch, Write PORTG Data Latch ---x xxxx 39, 145

LATF Read PORTF Data Latch, Write PORTF Data Latch xxxx xxxx 39, 141

LATE Read PORTE Data Latch, Write PORTE Data Latch xxxx xxxx 39, 138

LATD Read PORTD Data Latch, Write PORTD Data Latch xxxx xxxx 39, 133

LATC Read PORTC Data Latch, Write PORTC Data Latch xxxx xxxx 39, 131

LATB Read PORTB Data Latch, Write PORTB Data Latch xxxx xxxx 39, 128

LATA — LATA6(1) Read PORTA Data Latch, Write PORTA Data Latch(1) -xxx xxxx 39, 125



POR, BORDetails

on page:




PIC18F6585/8585/6680/8680

PORTJ(3) Read PORTJ pins, Write PORTJ Data Latch xxxx xxxx 40, 151

PORTH(3) Read PORTH pins, Write PORTH Data Latch xxxx xxxx 40, 148

PORTG — — RG5(6) Read PORTG pins, Write PORTG Data Latch --0x xxxx 40, 145

PORTF Read PORTF pins, Write PORTF Data Latch xxxx xxxx 40, 141

PORTE Read PORTE pins, Write PORTE Data Latch xxxx xxxx 40, 136

PORTD Read PORTD pins, Write PORTD Data Latch xxxx xxxx 40, 133

PORTC Read PORTC pins, Write PORTC Data Latch xxxx xxxx 40, 131

PORTB Read PORTB pins, Write PORTB Data Latch xxxx xxxx 40, 128

PORTA — RA6(1) Read PORTA pins, Write PORTA Data Latch(1) -x0x 0000 40, 125

SPBRGH Enhanced USART Baud Rate Generator High Byte 0000 0000 40, 233

BAUDCON — RCIDL — SCKP BRG16 — WUE ABDEN -1-0 0-00 40, 233

ECCP1DEL PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 40, 187

TXERRCNT TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 0000 0000 40, 288

RXERRCNT REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 0000 0000 40, 296

COMSTATMode 0

RXB0OVFL RXB1OVFL TXBO TXBP RXBP TXWARN RXWARN EWARN 0000 0000 40, 284

COMSTATMode 1

— RXBnOVFL TXBO TXBP RXBP TXWARN RXWARN EWARN -000 0000 40, 284

COMSTATMode 2

FIFOEMPTY RXBnOVFL TXBO TXBP RXBP TXWARN RXWARN EWARN 0000 0000 40, 284

CIOCON TX2SRC TX2EN ENDRHI CANCAP — — — — 0000 ---- 40, 318

BRGCON3 WAKDIS WAKFIL — — — SEG2PH2 SEG2PH1 SEG2PH0 00-- -000 40, 317

BRGCON2 SEG2PHT SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0 0000 0000 40, 317

BRGCON1 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 0000 0000 40, 317

CANCONMode 0

REQOP2 REQOP1 REQOP0 ABAT WIN2 WIN1 WIN0 — 1000 000- 40, 239

CANCONMode 1

REQOP2 REQOP1 REQOP0 ABAT — — — — 1000 ---- 40, 239

CANCONMode 2

REQOP2 REQOP1 REQOP0 ABAT FP3 FP2 FP1 FP0 1000 0000 40, 239

CANSTATMode 0

OPMODE2 OPMODE1 OPMODE0 — ICODE2 ICODE1 ICODE0 — 000- 0000 40, 239

CANSTATModes 0, 1

OPMODE2 OPMODE1 OPMODE0 EICODE4 EICODE3 EICODE2 EICODE1 EICODE0 0000 0000 40, 239

ECANCON MDSEL1 MDSEL0 FIFOWM EWIN4 EWIN3 EWIN2 EWIN1 EWIN0 0001 0000 40, 323

RXB0D7 RXB0D77 RXB0D76 RXB0D75 RXB0D74 RXB0D73 RXB0D72 RXB0D71 RXB0D70 xxxx xxxx 40, 230










POR, BORDetails

on page:




PIC18F6585/8585/6680/8680

RXB0DLC — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 40, 230

RXB0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 41, 230

RXB0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 41, 230

RXB0SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 xxxx x-xx 41, 230

RXB0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 41, 230

RXB0CONMode 0

RXFUL RXM1 RXM0(4) —(4) RXRTRR0(4) RXB0DBEN(4) JTOFF(4) FILHIT0(4) 000- 0000 41, 230

RXB0CONMode 1, 2

RXFUL RXM1 RTRR0(4) FILHIT4(4) FILHIT3(4) FILHIT2(4) FILHIT1(4) FILHIT0(4) 0000 0000 41, 230









RXB1DLC — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 41, 230

RXB1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 41, 230

RXB1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 41, 230

RXB1SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 xxxx x-xx 41, 230

RXB1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 41, 230

RXB1CONMode 0

RXFUL RXM1 RXM0(4) —(4) RXRTRR0(4) FILHIT2(4) FILHIT1(4) FILHIT0(4) 000- 0000 41, 230

RXB1CONMode 1, 2

RXFUL RXM1 RTRRO(4) FILHIT4(4) FILHIT3(4) FILHIT2(4) FILHIT1(4) FILHIT0(4) 0000 0000 41, 230

TXB0D7 TXB0D77 TXB0D76 TXB0D75 TXB0D74 TXB0D73 TXB0D72 TXB0D71 TXB0D70 xxxx xxxx 41, 230








TXB0DLC — TXRTR — — DLC3 DLC2 DLC1 DLC0 -x-- xxxx 41, 230

TXB0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 41, 230

TXB0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 41, 230

TXB0SIDL SID2 SID1 SID0 — EXIDE — EID17 EID16 xx-x x-xx 41, 230

TXB0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 42, 230

TXB0CONMode 0

— TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 -000 0-00 42, 230

TXB0CONMode 1, 2

TXBIF TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 0000 0-00 42, 230



POR, BORDetails

on page:




PIC18F6585/8585/6680/8680












TXB1SIDL SID2 SID1 SID0 — EXIDE — EID17 EID16 xx-x x-xx 42, 230


TXB1CONMode 0


TXB1CONMode 1, 2













TXB2SIDL SID2 SID1 SID0 — EXIDE — EID17 EID16 xxx- x-xx 42, 230


TXB2CONMode 0


TXB2CONMode 1, 2


RXM1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 42, 230

RXM1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 43, 230

RXM1SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xx-x 0-xx 43, 230

RXM1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 43, 230

RXM0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 43, 230

RXM0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 43, 230

RXM0SIDL SID2 SID1 SID0 — EXIDM — EID17 EID16 xx-x 0-xx 43, 230

RXM0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 43, 230

RXF15EIDL(7) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 47, 230



POR, BORDetails

on page:




PIC18F6585/8585/6680/8680

RXF15EIDH(7) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 47, 230

RXF15SIDL(7) SID2 SID1 SID0 — EXIDEN — EID17 EID16 xx-x x-xx 47, 230

RXF15SIDH(7) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 47, 230





































RXF5EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 43, 230

RXF5EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 43, 230



POR, BORDetails

on page:




PIC18F6585/8585/6680/8680

RXF5SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xx-x x-xx 43, 230

RXF5SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 43, 230





















B5D7(7) B5D77 B5D76 B5D75 B5D74 B5D73 B5D72 B5D71 B5D70 xxxx xxxx 44, 230








B5DLC(7) — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 44, 230

B5EIDL(7) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 44, 230

B5EIDH(7) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 44, 230

B5SIDL(7) SID2 SID1 SID0 SRR EXID/EXIDE(5)

— EID17 EID16 xxxx x-xx 44, 230

B5SIDH(7) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 44, 230

B5CON(5, 7) RXFUL/TXBIF

RXM1/TXABT

RTRRO/ TXLARB

FILHIT4/TXERR

FILHIT3/TXREQ

FILHIT2/RTREN

FILHIT1/TXPRI1

FILHIT0/TXPRI0

0000 0000 44, 230







POR, BORDetails

on page:




PIC18F6585/8585/6680/8680











B4CON(5, 7) RXFUL/TXB3IF

RXM1/TXABT

RTRRO/ TXLARB

FILHIT4/TXERR

FILHIT3/TXREQ

FILHIT2/RTREN

FILHIT1/TXPRI1

FILHIT0/TXPRI0

0000 0000 44, 230
















RXM1/TXABT

RTRRO/ TXLARB

FILHIT4/TXERR

FILHIT3/TXREQ

FILHIT2/RTREN

FILHIT1/TXPRI1

FILHIT0/TXPRI0

0000 0000 45, 230

















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RXM1/TXABT

RTRRO/ TXLARB

FILHIT4/TXERR

FILHIT3/TXREQ

FILHIT2/RTREN

FILHIT1/TXPRI1

FILHIT0/TXPRI0

0000 0000 45, 230












B1SIDL(7) SID2 SID1 SID0 SRR EXID — EID17 EID16 xxxx x-xx 46, 230



RXM1/TXABT

RTRRO/ TXLARB

FILHIT4/TXERR

FILHIT3/TXREQ

FILHIT2/RTREN

FILHIT1/TXPRI1

FILHIT0/TXPRI0

0000 0000 46, 230









B0DLC(7) — RTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 46, 230



B0SIDL(7) SID2 SID1 SID0 SRR EXID — EID17 EID16 xxxx x-xx 46, 230



RXM1/TXABT

RTRRO/ TXLARB

FILHIT4/TXERR

FILHIT3/TXREQ

FILHIT2/RTREN

FILHIT1/TXPRI1

FILHIT0/TXPRI0

0000 0000 46, 230

TXBIE(7) — — — TXB2IE TXB1IE TXB0IE — — ---0 00-- 46, 230

BIE0(7) B5IE B4IE B3IE B2IE B1IE B0IE RXB1IE RXB0IE 0000 0000 46, 230

BSEL0(7) B5TXEN B4TXEN B3TXEN B2TXEN B1TXEN B0TXEN — — 0000 00-- 46, 230

MSEL3(7) FIL15_1 FIL15_0 FIL14_1 FIL14_0 FIL13_1 FIL13_0 FIL12_1 FIL12_0 0000 0000 46, 230




SDFLC(7) — — — DFLC4 DFLC3 DFLC2 DFLC1 DFLC0 ---0 0000 46, 230

RXFCON1(7) RXF15EN RXF14EN RXF13EN RXF12EN RXF11EN RXF10EN RXF9EN RXF8EN 0000 0000 46, 230

RXFCON0(7) RXF7EN RXF6EN RXF5EN RXF4EN RXF3EN RXF2EN RXF1EN RXF0EN 0011 1111 47, 230



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RXFBCON7(7) F15BP_3 F15BP_2 F15BP_1 F15BP_0 F14BP_3 F14BP_2 F14BP_1 F14BP_01 0000 0000 47, 230










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4.10 Access Bank

The Access Bank is an architectural enhancementwhich is very useful for C compiler code optimization.The techniques used by the C compiler may also beuseful for programs written in assembly.

This data memory region can be used for:

• Intermediate computational values

• Local variables of subroutines• Faster context saving/switching of variables• Common variables

• Faster evaluation/control of SFRs (no banking)

The Access Bank is comprised of the upper 160 bytesin Bank 15 (SFRs) and the lower 96 bytes in Bank 0.These two sections will be referred to as Access RAMHigh and Access RAM Low, respectively. Figure 4-7indicates the Access RAM areas.

A bit in the instruction word specifies if the operation isto occur in the bank specified by the BSR register or inthe Access Bank. This bit is denoted by the ‘a’ bit (foraccess bit).

When forced in the Access Bank (a = 0), the lastaddress in Access RAM Low is followed by the firstaddress in Access RAM High. Access RAM High mapsthe Special Function Registers so that these registerscan be accessed without any software overhead. This isuseful for testing status flags and modifying control bits.

4.11 Bank Select Register (BSR)

The need for a large general purpose memory spacedictates a RAM banking scheme. The data memory ispartitioned into sixteen banks. When using directaddressing, the BSR should be configured for thedesired bank.

BSR<3:0> holds the upper 4 bits of the 12-bit RAMaddress. The BSR<7:4> bits will always read ‘0’s andwrites will have no effect.

A MOVLB instruction has been provided in theinstruction set to assist in selecting banks.

If the currently selected bank is not implemented, anyread will return all ‘0’s and all writes are ignored. TheStatus register bits will be set/cleared as appropriate forthe instruction performed.

Each Bank extends up to 0FFh (256 bytes). All datamemory is implemented as static RAM.

A MOVFF instruction ignores the BSR since the 12-bitaddresses are embedded into the instruction word.

Section 4.12 “Indirect Addressing, INDF and FSRRegisters” provides a description of indirect address-ing which allows linear addressing of the entire RAMspace.

FIGURE 4-8: DIRECT ADDRESSING

Note 1: For register file map detail, see Table 4-2.

2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to theregisters of the Access Bank.

3: The MOVFF instruction embeds the entire 12-bit address in the instruction.

DataMemory(1)

Direct Addressing

Bank Select(2) Location Select(3)

BSR<3:0> 7 0From Opcode(3)

00h 01h 0Eh 0Fh

Bank 0 Bank 1 Bank 14 Bank 15

1FFh

100h

0FFh

000h

EFFh

E00h

FFFh

F00h

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4.12 Indirect Addressing, INDF and FSR Registers

Indirect addressing is a mode of addressing data mem-ory where the data memory address in the instructionis not fixed. An FSR register is used as a pointer to thedata memory location that is to be read or written. Sincethis pointer is in RAM, the contents can be modified bythe program. This can be useful for data tables in thedata memory and for software stacks. Figure 4-9shows the operation of indirect addressing. This showsthe moving of the value to the data memory addressspecified by the value of the FSR register.

Indirect addressing is possible by using one of theINDF registers. Any instruction using the INDF registeractually accesses the register pointed to by the FileSelect Register, FSR. Reading the INDF register itself,indirectly (FSR = 0), will read 00h. Writing to the INDFregister indirectly, results in a no operation. The FSRregister contains a 12-bit address which is shown inFigure 4-10.

The INDFn register is not a physical register. Address-ing INDFn actually addresses the register whoseaddress is contained in the FSRn register (FSRn is apointer). This is indirect addressing.

Example 4-4 shows a simple use of indirect addressingto clear the RAM in Bank 1 (locations 100h-1FFh) in aminimum number of instructions.

EXAMPLE 4-4: HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING

There are three Indirect Addressing registers. Toaddress the entire data memory space (4096 bytes),these registers are 12-bits wide. To store the 12 bits ofaddressing information, two 8-bit registers arerequired. These Indirect Addressing registers are:

1. FSR0: composed of FSR0H:FSR0L2. FSR1: composed of FSR1H:FSR1L

3. FSR2: composed of FSR2H:FSR2L

In addition, there are registers INDF0, INDF1 andINDF2 which are not physically implemented. Readingor writing to these registers activates indirect address-ing with the value in the corresponding FSR registerbeing the address of the data. If an instruction writes avalue to INDF0, the value will be written to the addresspointed to by FSR0H:FSR0L. A read from INDF1 reads

the data from the address pointed to byFSR1H:FSR1L. INDFn can be used in code anywherean operand can be used.

If INDF0, INDF1, or INDF2 are read indirectly via anFSR, all ‘0’s are read (zero bit is set). Similarly, ifINDF0, INDF1, or INDF2 are written to indirectly, theoperation will be equivalent to a NOP instruction and theStatus bits are not affected.

4.12.1 INDIRECT ADDRESSING OPERATION

Each FSR register has an INDF register associatedwith it plus four additional register addresses.Performing an operation on one of these five registersdetermines how the FSR will be modified duringindirect addressing.

When data access is done to one of the five INDFnlocations, the address selected will configure the FSRnregister to:

• Do nothing to FSRn after an indirect access (no change) – INDFn.

• Auto-decrement FSRn after an indirect access (post-decrement) – POSTDECn.

• Auto-increment FSRn after an indirect access (post-increment) – POSTINCn.

• Auto-increment FSRn before an indirect access (pre-increment) – PREINCn.

• Use the value in the WREG register as an offset to FSRn. Do not modify the value of the WREG or the FSRn register after an indirect access (no change) – PLUSWn.

When using the auto-increment or auto-decrement fea-tures, the effect on the FSR is not reflected in the Statusregister. For example, if the indirect address causes theFSR to equal ‘0’, the Z bit will not be set.

Incrementing or decrementing an FSR affects all12 bits. That is, when FSRnL overflows from anincrement, FSRnH will be incremented automatically.

Adding these features allows the FSRn to be used as astack pointer in addition to its uses for table operationsin data memory.

Each FSR has an address associated with it thatperforms an indexed indirect access. When a dataaccess to this INDFn location (PLUSWn) occurs, theFSRn is configured to add the signed value in theWREG register and the value in FSR to form theaddress before an indirect access. The FSR value isnot changed.

If an FSR register contains a value that points to one ofthe INDFn, an indirect read will read 00h (zero bit isset), while an indirect write will be equivalent to a NOP(Status bits are not affected).

LFSR FSR0, 100h ; NEXT CLRF POSTINC0 ; Clear INDF

; register and ; inc pointer

BTFSS FSR0H, 1 ; All done with; Bank1?

BRA NEXT ; NO, clear next CONTINUE ; YES, continue


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If an indirect addressing operation is done where thetarget address is an FSRnH or FSRnL register, thewrite operation will dominate over the pre- orpost-increment/decrement functions.

FIGURE 4-9: INDIRECT ADDRESSING OPERATION

FIGURE 4-10: INDIRECT ADDRESSING

Opcode Address

File Address = Access of an Indirect Addressing Register

FSR

InstructionExecuted

InstructionFetched

RAM

Opcode File

1212

12

BSR<3:0>

84

0h

0FFFh

Note 1: For register file map detail, see Table 4-2.

DataMemory(1)

Indirect Addressing

FSR Register11 0

0FFFh

0000h

Location Select

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4.13 Status Register

The Status register, shown in Register 4-3, contains thearithmetic status of the ALU. The Status register can bethe destination for any instruction as with any other reg-ister. If the Status register is the destination for aninstruction that affects the Z, DC, C, OV or N bits, thenthe write to these five bits is disabled. These bits are setor cleared according to the device logic. Therefore, theresult of an instruction with the Status register asdestination may be different than intended.

For example, CLRF STATUS will clear the upper threebits and set the Z bit. This leaves the Status registeras 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,SWAPF, MOVFF and MOVWF instructions are used toalter the Status register because these instructions donot affect the Z, C, DC, OV or N bits from the Statusregister. For other instructions not affecting any statusbits, see Table 25-2.

REGISTER 4-3: STATUS REGISTER

Note: The C and DC bits operate as a borrow anddigit borrow bit respectively, in subtraction.

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — — N OV Z DC C

bit 7 bit 0


bit 4 N: Negative bitThis bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative (ALU MSB = 1).1 = Result was negative 0 = Result was positive

bit 3 OV: Overflow bitThis bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7) to change state.1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit carry/borrow bit For ADDWF, ADDLW, SUBLW, and SUBWF instructions:

1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result

Note: For borrow, the polarity is reversed. A subtraction is executed by adding the2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bitis loaded with either the bit 4 or bit 3 of the source register.

bit 0 C: Carry/borrow bit

For ADDWF, ADDLW, SUBLW, and SUBWF instructions:1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

Note: For borrow, the polarity is reversed. A subtraction is executed by adding the2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bitis loaded with either the high or low-order bit of the source register.

Legend:




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4.14 RCON Register

The Reset Control (RCON) register contains flag bitsthat allow differentiation between the sources of adevice Reset. These flags include the TO, PD, POR,BOR and RI bits. This register is readable and writable.

REGISTER 4-4: RCON REGISTER

Note 1: It is recommended that the POR bit be setafter a Power-on Reset has beendetected so that subsequent Power-onResets may be detected.

2: Brown-out Reset is said to have occurredwhen BOR is ‘0’ and POR is ‘1’ (assum-ing that POR was set to ‘1’ by softwareimmediately after POR).

R/W-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0


bit 7 bit 0

bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)


bit 4 RI: RESET Instruction Flag bit

1 = The RESET instruction was not executed0 = The RESET instruction was executed causing a device Reset

(must be set in software after a Brown-out Reset occurs)

bit 3 TO: Watchdog Time-out Flag bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred

bit 2 PD: Power-down Detection Flag bit

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

bit 1 POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR: Brown-out Reset Status bit1 = A Brown-out Reset has not occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Legend:




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5.0 FLASH PROGRAM MEMORY

The Flash program memory is readable, writable anderasable during normal operation over the entire VDD

range.

A read from program memory is executed on one byteat a time. A write to program memory is executed onblocks of 8 bytes at a time. Program memory is erasedin blocks of 64 bytes at a time. A bulk erase operationcannot be issued from user code.

Writing or erasing program memory will ceaseinstruction fetches until the operation is complete. Theprogram memory cannot be accessed during the writeor erase, therefore, code cannot execute. An internalprogramming timer terminates program memory writesand erases.

A value written to program memory does not need to bea valid instruction. Executing a program memorylocation that forms an invalid instruction results in aNOP.

5.1 Table Reads and Table Writes

In order to read and write program memory, there aretwo operations that allow the processor to move bytesbetween the program memory space and the data RAM:

• Table Read (TBLRD)• Table Write (TBLWT)

The program memory space is 16 bits wide, while thedata RAM space is 8-bits wide. Table reads and tablewrites move data between these two memory spacesthrough an 8-bit register (TABLAT).

Table read operations retrieve data from programmemory and places it into the data RAM space.Figure 5-1 shows the operation of a table read withprogram memory and data RAM.

Table write operations store data from the data memoryspace into holding registers in program memory. Theprocedure to write the contents of the holdingregisters into program memory is detailed inSection 5.5 “Writing to Flash Program Memory”.Figure 5-2 shows the operation of a table write withprogram memory and data RAM.

Table operations work with byte entities. A table blockcontaining data, rather than program instructions, is notrequired to be word aligned. Therefore, a table block canstart and end at any byte address. If a table write is beingused to write executable code into program memory,program instructions will need to be word aligned.

FIGURE 5-1: TABLE READ OPERATION

Table Pointer(1)

Table Latch (8-bit)Program Memory

TBLPTRH TBLPTRLTABLAT

TBLPTRU

Instruction: TBLRD*

Note 1: Table Pointer points to a byte in program memory.

Program Memory(TBLPTR)


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FIGURE 5-2: TABLE WRITE OPERATION

5.2 Control Registers

Several control registers are used in conjunction withthe TBLRD and TBLWT instructions. These include the:

• EECON1 register

• EECON2 register• TABLAT register• TBLPTR registers

5.2.1 EECON1 AND EECON2 REGISTERS

EECON1 is the control register for memory accesses.

EECON2 is not a physical register. Reading EECON2will read all ‘0’s. The EECON2 register is usedexclusively in the memory write and erase sequences.

Control bit EEPGD determines if the access will be aprogram or data EEPROM memory access. Whenclear, any subsequent operations will operate on thedata EEPROM memory. When set, any subsequentoperations will operate on the program memory.

Control bit CFGS determines if the access will be to theconfiguration/calibration registers or to programmemory/data EEPROM memory. When set, subse-quent operations will operate on configuration registersregardless of EEPGD (see Section 24.0 “SpecialFeatures of the CPU”). When clear, memory selectionaccess is determined by EEPGD.

The FREE bit, when set, will allow a program memoryerase operation. When the FREE bit is set, the eraseoperation is initiated on the next WR command. WhenFREE is clear, only writes are enabled.

The WREN bit, when set, will allow a write operation.On power-up, the WREN bit is clear. The WRERR bit isset when a write operation is interrupted by a MCLRReset or a WDT Time-out Reset during normal opera-tion. In these situations, the user can check theWRERR bit and rewrite the location. It is necessary toreload the data and address registers (EEDATA andEEADR) due to Reset values of zero.

The WR control bit initiates write operations. The bitcannot be cleared, only set in software; it is cleared inhardware at the completion of the write operation. Theinability to clear the WR bit in software prevents theaccidental or premature termination of a writeoperation.

Table Pointer(1)Table Latch (8-bit)

TBLPTRH TBLPTRL TABLAT

Program Memory(TBLPTR)

TBLPTRU

Instruction: TBLWT*

Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined byTBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed inSection 5.5 “Writing to Flash Program Memory”.

Holding Registers Program Memory

Note: Interrupt flag bit, EEIF in the PIR2 register,is set when the write is complete. It mustbe cleared in software.

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REGISTER 5-1: EECON1 REGISTER (ADDRESS FA6h) R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0

EEPGD CFGS — FREE WRERR WREN WR RD

bit 7 bit 0

bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit1 = Access Flash program memory0 = Access data EEPROM memory

bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit

1 = Access configuration registers0 = Access Flash program or data EEPROM memory


bit 4 FREE: Flash Row Erase Enable bit1 = Erase the program memory row addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)0 = Perform write only

bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit1 = A write operation is prematurely terminated

(any Reset during self-timed programming in normal operation)0 = The write operation completed

Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition.

bit 2 WREN: Flash Program/Data EEPROM Write Enable bit1 = Allows write cycles0 = Inhibits write to the EEPROM

bit 1 WR: Write Control bit

1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or writecycle. (The operation is self-timed and the bit is cleared by hardware once write iscomplete. The WR bit can only be set (not cleared) in software.)

0 = Write cycle to the EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read. (Read takes one cycle. RD is cleared in hardware. The RD bitcan only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)

0 = Does not initiate an EEPROM read

Legend:

R = Readable bit U = Unimplemented bit, read as ‘0’

W = Writable bit S = Settable bit - n = Value after erase

‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown


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5.2.2 TABLAT – TABLE LATCH REGISTER

The Table Latch (TABLAT) is an 8-bit register mappedinto the SFR space. The Table Latch is used to hold 8-bit data during data transfers between programmemory and data RAM.

5.2.3 TBLPTR – TABLE POINTER REGISTER

The Table Pointer (TBLPTR) addresses a byte withinthe program memory. The TBLPTR is comprised ofthree SFR registers: Table Pointer Upper Byte, TablePointer High Byte and Table Pointer Low Byte(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-ters join to form a 22-bit wide pointer. The low-order21 bits allow the device to address up to 2 Mbytes ofprogram memory space. The 22nd bit allows access tothe device ID, the user ID and the configuration bits.

The Table Pointer, TBLPTR, is used by the TBLRD andTBLWT instructions. These instructions can update theTBLPTR in one of four ways based on the table opera-tion. These operations are shown in Table 5-1. Theseoperations on the TBLPTR only affect the low-order21 bits.

5.2.4 TABLE POINTER BOUNDARIES

TBLPTR is used in reads, writes and erases of theFlash program memory.

When a TBLRD is executed, all 22 bits of the tablepointer determine which byte is read from programmemory into TABLAT.

When a TBLWT is executed, the three LSbs of the TablePointer (TBLPTR<2:0>) determine which of the eightprogram memory holding registers is written to. Whenthe timed write to program memory (long write) begins,the 19 MSbs of the Table Pointer (TBLPTR<21:3>) willdetermine which program memory block of 8 bytes iswritten to. For more detail, see Section 5.5 “Writing toFlash Program Memory”.

When an erase of program memory is executed, the16 MSbs of the Table Pointer (TBLPTR<21:6>) point tothe 64-byte block that will be erased. The LeastSignificant bits (TBLPTR<5:0>) are ignored.

Figure 5-3 describes the relevant boundaries ofTBLPTR based on Flash program memory operations.

TABLE 5-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS

FIGURE 5-3: TABLE POINTER BOUNDARIES BASED ON OPERATION

Example Operation on Table Pointer

TBLRD*TBLWT*

TBLPTR is not modified

TBLRD*+TBLWT*+

TBLPTR is incremented after the read/write

TBLRD*-TBLWT*-

TBLPTR is decremented after the read/write

TBLRD+*TBLWT+*

TBLPTR is incremented before the read/write

21 16 15 8 7 0

ERASE – TBLPTR<20:6>

WRITE – TBLPTR<21:3>

READ – TBLPTR<21:0>

TBLPTRLTBLPTRHTBLPTRU

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5.3 Reading the Flash Program Memory

The TBLRD instruction is used to retrieve data fromprogram memory and places it into data RAM. Tablereads from program memory are performed one byte ata time.

TBLPTR points to a byte address in program space.Executing TBLRD places the byte pointed to intoTABLAT. In addition, TBLPTR can be modifiedautomatically for the next table read operation.

The internal program memory is typically organized bywords. The Least Significant bit of the address selectsbetween the high and low bytes of the word. Figure 5-4shows the interface between the internal programmemory and the TABLAT.

FIGURE 5-4: READS FROM FLASH PROGRAM MEMORY

EXAMPLE 5-1: READING A FLASH PROGRAM MEMORY WORD

(Even Byte Address)

Program Memory

(Odd Byte Address)

TBLRDTABLAT

TBLPTR = xxxxx1

FETCHInstruction Register

(IR) Read Register

TBLPTR = xxxxx0

MOVLW upper(CODE_ADDR) ; Load TBLPTR with the baseMOVWF TBLPTRU ; address of the wordMOVLW high(CODE_ADDR)MOVWF TBLPTRHMOVLW low(CODE_ADDR_LOW)MOVWF TBLPTRL

READ_WORDTBLRD*+ ; read into TABLAT and incrementMOVF TABLAT, W ; get dataMOVWF LSBTBLRD*+ ; read into TABLAT and incrementMOVF TABLAT, W ; get dataMOVWF MSB


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5.4 Erasing Flash Program Memory

The minimum erase block is 32 words or 64 bytes. Onlythrough the use of an external programmer or throughICSP control can larger blocks of program memory bebulk erased. Word erase in the Flash array is notsupported.

When initiating an erase sequence from the micro-controller itself, a block of 64 bytes of program memoryis erased. The Most Significant 16 bits of theTBLPTR<21:6> point to the block being erased.TBLPTR<5:0> are ignored.

The EECON1 register commands the erase operation.The EEPGD bit must be set to point to the Flashprogram memory. The WREN bit must be set to enablewrite operations. The FREE bit is set to select an eraseoperation.

For protection, the write initiate sequence for EECON2must be used.

A long write is necessary for erasing the internal Flash.Instruction execution is halted while in a long writecycle. The long write will be terminated by the internalprogramming timer.

5.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE

The sequence of events for erasing a block of internalprogram memory location is:

1. Load table pointer with address of row beingerased.

2. Set the EECON1 register for the eraseoperation:• set EEPGD bit to point to program memory;• clear the CFGS bit to access program memory;

• set WREN bit to enable writes; • set FREE bit to enable the erase.

3. Disable interrupts.

4. Write 55h to EECON2.5. Write 0AAh to EECON2.6. Set the WR bit. This will begin the row erase

cycle.7. The CPU will stall for duration of the erase

(about 2 ms using internal timer).8. Execute a NOP.

9. Re-enable interrupts.

EXAMPLE 5-2: ERASING A FLASH PROGRAM MEMORY ROW MOVLW upper(CODE_ADDR) ; load TBLPTR with the baseMOVWF TBLPTRU ; address of the memory blockMOVLW high(CODE_ADDR)MOVWF TBLPTRH MOVLW low(CODE_ADDR)MOVWF TBLPTRL

ERASE_ROW BSF EECON1, EEPGD ; point to Flash program memoryBCF EECON1, CFGS ; access Flash program memoryBSF EECON1, WREN ; enable write to memoryBSF EECON1, FREE ; enable Row Erase operationBCF INTCON, GIE ; disable interruptsMOVLW 55hMOVWF EECON2 ; write 55h

Required MOVLW 0AAhSequence MOVWF EECON2 ; write 0AAh

BSF EECON1, WR ; start erase (CPU stall)NOPBSF INTCON, GIE ; re-enable interrupts

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5.5 Writing to Flash Program Memory

The minimum programming block is 4 words or 8 bytes.Word or byte programming is not supported.

Table writes are used internally to load the holdingregisters needed to program the Flash memory. Thereare eight holding registers used by the table writes forprogramming.

Since the Table Latch (TABLAT) is only a single byte,the TBLWT instruction has to be executed 8 times foreach programming operation. All of the table writeoperations will essentially be short writes because only

the holding registers are written. At the end of updatingeight registers, the EECON1 register must be writtento, to start the programming operation with a long write.

The long write is necessary for programming the inter-nal Flash. Instruction execution is halted while in a longwrite cycle. The long write will be terminated by theinternal programming timer.

The EEPROM on-chip timer controls the write time.The write/erase voltages are generated by an on-chipcharge pump, rated to operate over the voltage rangeof the device for byte or word operations.

FIGURE 5-5: TABLE WRITES TO FLASH PROGRAM MEMORY

Holding Register

TABLAT

Holding Register

TBLPTR = xxxxx7

Holding Register

TBLPTR = xxxxx1

Holding Register

TBLPTR = xxxxx0

8 8 8 8

Write Register

TBLPTR = xxxxx2

Program Memory


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5.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE

The sequence of events for programming an internalprogram memory location should be:

1. Read 64 bytes into RAM.2. Update data values in RAM as necessary.

3. Load table pointer with address being erased.4. Do the row erase procedure.5. Load table pointer with address of first byte

being written.6. Write the first 8 bytes into the holding registers

with auto-increment.7. Set the EECON1 register for the write operation:

• set EEPGD bit to point to program memory;• clear the CFGS bit to access program memory;• set WREN to enable byte writes.

8. Disable interrupts.9. Write 55h to EECON2.

10. Write 0AAh to EECON2.11. Set the WR bit. This will begin the write cycle.12. The CPU will stall for duration of the write (about

5 ms using internal timer).13. Execute a NOP.

14. Re-enable interrupts.15. Repeat steps 6-14 seven times to write 64 bytes.16. Verify the memory (table read).

This procedure will require about 40 ms to update onerow of 64 bytes of memory. An example of the requiredcode is given in Example 5-3.

EXAMPLE 5-3: WRITING TO FLASH PROGRAM MEMORY

Note: Before setting the WR bit, the TablePointer address needs to be within theintended address range of the eight bytesin the holding register.

MOVLW D’64 ; number of bytes in erase blockMOVWF COUNTERMOVLW high(BUFFER_ADDR) ; point to bufferMOVWF FSR0HMOVLW low(BUFFER_ADDR)MOVWF FSR0LMOVLW upper(CODE_ADDR) ; Load TBLPTR with the baseMOVWF TBLPTRU ; address of the memory blockMOVLW high(CODE_ADDR)MOVWF TBLPTRHMOVLW low(CODE_ADDR)MOVWF TBLPTRL

READ_BLOCKTBLRD*+ ; read into TABLAT, and incMOVF TABLAT, W ; get dataMOVWF POSTINC0 ; store dataDECFSZ COUNTER ; done?BRA READ_BLOCK ; repeat

MODIFY_WORDMOVLW high(DATA_ADDR) ; point to bufferMOVWF FSR0HMOVLW low(DATA_ADDR)MOVWF FSR0LMOVLW low(NEW_DATA) ; update buffer wordMOVWF POSTINC0MOVLW high(NEW_DATA)MOVWF INDF0


PIC18F6585/8585/6680/8680

EXAMPLE 5-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)ERASE_BLOCK

MOVLW upper(CODE_ADDR) ; load TBLPTR with the baseMOVWF TBLPTRU ; address of the memory blockMOVLW high(CODE_ADDR)MOVWF TBLPTRH MOVLW low(CODE_ADDR)MOVWF TBLPTRL BSF EECON1, EEPGD ; point to Flash program memoryBCF EECON1, CFGS ; access Flash program memoryBSF EECON1, WREN ; enable write to memoryBSF EECON1, FREE ; enable Row Erase operationBCF INTCON, GIE ; disable interruptsMOVLW 55hMOVWF EECON2 ; write 55H

Required MOVLW 0AAhSequence MOVWF EECON2 ; write AAH

BSF EECON1, WR ; start erase (CPU stall)NOPBSF INTCON, GIE ; re-enable interruptsTBLRD*- ; dummy read decrement

WRITE_BUFFER_BACKMOVLW 8 ; number of write buffer groups of 8 bytesMOVWF COUNTER_HIMOVLW high(BUFFER_ADDR) ; point to bufferMOVWF FSR0HMOVLW low(BUFFER_ADDR)MOVWF FSR0L

PROGRAM_LOOPMOVLW 8 ; number of bytes in holding registerMOVWF COUNTER

WRITE_WORD_TO_HREGSMOVFW POSTINC0, W ; get low byte of buffer dataMOVWF TABLAT ; present data to table latchTBLWT+* ; write data, perform a short write

; to internal TBLWT holding register.DECFSZ COUNTER ; loop until buffers are fullBRA WRITE_WORD_TO_HREGS

PROGRAM_MEMORYBSF EECON1, EEPGD ; point to Flash program memoryBCF EECON1, CFGS ; access Flash program memoryBSF EECON1, WREN ; enable write to memoryBCF INTCON, GIE ; disable interruptsMOVLW 55hMOVWF EECON2 ; write 55h

Required MOVLW 0AAhSequence MOVWF EECON2 ; write 0AAh

BSF EECON1, WR ; start program (CPU stall)NOPBSF INTCON, GIE ; re-enable interruptsDECFSZ COUNTER_HI ; loop until doneBRA PROGRAM_LOOPBCF EECON1, WREN ; disable write to memory


PIC18F6585/8585/6680/8680

5.5.2 WRITE VERIFY

Depending on the application, good programmingpractice may dictate that the value written to the mem-ory should be verified against the original value. Thisshould be used in applications where excessive writescan stress bits near the specification limit.

5.5.3 UNEXPECTED TERMINATION OF WRITE OPERATION

If a write is terminated by an unplanned event, such asloss of power or an unexpected Reset, the memorylocation just programmed should be verified and repro-grammed if needed. The WRERR bit is set when awrite operation is interrupted by a MCLR Reset or aWDT Time-out Reset during normal operation. In thesesituations, users can check the WRERR bit and rewritethe location.

5.5.4 PROTECTION AGAINST SPURIOUS WRITES

To protect against spurious writes to Flash programmemory, the write initiate sequence must also befollowed. See Section 24.0 “Special Features of theCPU” for more detail.

5.6 Flash Program Operation During Code Protection

See Section 24.0 “Special Features of the CPU” fordetails on code protection of Flash program memory.

TABLE 5-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Value on:POR, BOR

Value on all other Resets

TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)

--00 0000 --00 0000

TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 0000 0000

TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>) 0000 0000 0000 0000

TABLAT Program Memory Table Latch 0000 0000 0000 0000

INTCON GIE/GIEH PEIE/GIEL TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 0000 0000 0000

EECON2 EEPROM Control Register 2 (not a physical register) — —

EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 uu-0 u000

IPR2 — CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 -1-1 1111

PIR2 — CMIF — EEIF BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 -0-0 0000

PIE2 — CMIE — EEIE BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 -0-0 0000

Legend: x = unknown, u = unchanged, r = reserved, – = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.

PIC18F6585/8585/6680/8680

6.0 EXTERNAL MEMORY INTERFACE

The external memory interface is a feature of thePIC18F8X8X devices that allows the controller toaccess external memory devices (such as Flash,EPROM, SRAM, etc.) as program memory.

The physical implementation of the interface uses27 pins. These pins are reserved for external address/data bus functions; they are multiplexed with I/O portpins on four ports. Three I/O ports are multiplexed withthe address/data bus, while the fourth port is multi-plexed with the bus control signals. The I/O port func-tions are enabled when the EBDIS bit in the MEMCONregister is set (see Register 6-1). A list of themultiplexed pins and their functions is provided inTable 6-1.

As implemented in the PIC18F8X8X devices, theinterface operates in a similar manner to the externalmemory interface introduced on PIC18C601/801microcontrollers. The most notable difference is thatthe interface on PIC18F8X8X devices only operates in16-bit modes. The 8-bit mode is not supported.

For a more complete discussion of the operating modesthat use the external memory interface, refer toSection 4.1.1 “PIC18F8X8X Program MemoryModes”.

6.1 Program Memory Modes and the External Memory Interface

As previously noted, PIC18F8X8X controllers arecapable of operating in any one of four program mem-ory modes using combinations of on-chip and externalprogram memory. The functions of the multiplexed portpins depend on the program memory mode selected aswell as the setting of the EBDIS bit.

In Microprocessor Mode, the external bus is alwaysactive and the port pins have only the external busfunction.

In Microcontroller Mode, the bus is not active and thepins have their port functions only. Writes to theMEMCOM register are not permitted.

In Microprocessor with Boot Block or ExtendedMicrocontroller Mode, the external program memorybus shares I/O port functions on the pins. When thedevice is fetching or doing table read/table writeoperations on the external program memory space, thepins will have the external bus function. If the device isfetching and accessing internal program memorylocations only, the EBDIS control bit will change thepins from external memory to I/O port functions. WhenEBDIS = 0, the pins function as the external bus. WhenEBDIS = 1, the pins function as I/O ports.

Note: The external memory interface is notimplemented on PIC18F6X8X (64/68-pin)devices.


PIC18F6585/8585/6680/8680

REGISTER 6-1: MEMCON REGISTER R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0

EBDIS(1) — WAIT1 WAIT0 — — WM1 WM0

bit 7 bit 0

bit 7 EBDIS: External Bus Disable bit(1)

1 = External system bus disabled, all external bus drivers are mapped as I/O ports0 = External system bus enabled and I/O ports are disabled

Note 1: This bit is ignored when device is accessing external memory either to fetch aninstruction or perform TBLRD/TBLWT.


bit 5-4 WAIT<1:0>: Table Reads and Writes Bus Cycle Wait Count bits11 = Table reads and writes will wait 0 TCY

10 = Table reads and writes will wait 1 TCY




bit 1-0 WM<1:0>: TBLWT Operation with 16-bit Bus bits

1x = Word Write mode: LSB and MSB word output, WRH active when MSB written01 = Byte Select mode: TABLAT data copied on both MS and LS Byte, WRH and (UB or LB)

will activate00 = Byte Write mode: TABLAT data copied on both MS and LS Byte, WRH or WRL will activate

Legend:



Note: The MEMCON register is held in Reset in Microcontroller mode.

PIC18F6585/8585/6680/8680

If the device fetches or accesses external memorywhile EBDIS = 1, the pins will switch to external bus. Ifthe EBDIS bit is set by a program executing from exter-nal memory, the action of setting the bit will be delayeduntil the program branches into the internal memory. Atthat time, the pins will change from external bus to I/Oports.

When the device is executing out of internal memory(with EBDIS = 0) in Microprocessor with Boot Blockmode or Extended Microcontroller mode, the control sig-nals will be in inactive. They will go to a state where theAD<15:0>, A<19:16> are tri-state; the OE, WRH, WRL,UB and LB signals are ‘1’; and ALE and BA0 are ‘0’.

TABLE 6-1: PIC18F8X8X EXTERNAL BUS – I/O PORT FUNCTIONS

Name Port Bit Function

RD0/AD0 PORTD bit 0 Input/Output or System Bus Address bit 0 or Data bit 0








RE0/AD8 PORTE bit 0 Input/Output or System Bus Address bit 8 or Data bit 8








RH0/A16 PORTH bit 0 Input/Output or System Bus Address bit 16




RJ0/ALE PORTJ bit 0 Input/Output or System Bus Address Latch Enable (ALE) Control pin

RJ1/OE PORTJ bit 1 Input/Output or System Bus Output Enable (OE) Control pin

RJ2/WRL PORTJ bit 2 Input/Output or System Bus Write Low (WRL) Control pin

RJ3/WRH PORTJ bit 3 Input/Output or System Bus Write High (WRH) Control pin

RJ4/BA0 PORTJ bit 4 Input/Output or System Bus Byte Address bit 0

RJ5/CE PORTJ bit 5 Input/Output or Chip Enable

RJ6/LB PORTJ bit 6 Input/Output or System Bus Lower Byte Enable (LB) Control pin

RJ7/UB PORTJ bit 7 Input/Output or System Bus Upper Byte Enable (UB) Control pin

PIC18F6585/8585/6680/8680

6.2 16-bit Mode

The external memory interface implemented inPIC18F8X8X devices operates only in 16-bit mode.The mode selection is not software configurable but isprogrammed via the configuration bits.

The WM<1:0> bits in the MEMCON register determinethree types of connections in 16-bit mode. They arereferred to as:

• 16-bit Byte Write• 16-bit Word Write• 16-bit Byte Select

These three different configurations allow the designermaximum flexibility in using 8-bit and 16-bit memorydevices.

For all 16-bit modes, the Address Latch Enable (ALE)pin indicates that the Address bits (A<15:0>) are avail-able on the external memory interface bus. Followingthe address latch, the Output Enable signal (OE ) willenable both bytes of program memory at once to forma 16-bit instruction word.

In Byte Select mode, JEDEC standard Flash memorieswill require BA0 for the byte address line, and one I/Oline to select between Byte and Word mode. The other16-bit modes do not need BA0. JEDEC standard staticRAM memories will use the UB or LB signals for byteselection.

6.2.1 16-BIT BYTE WRITE MODE

Figure 6-1 shows an example of 16-bit Byte Writemode for PIC18F8X8X devices.

FIGURE 6-1: 16-BIT BYTE WRITE MODE EXAMPLE

AD<7:0>

A<19:16>

ALE

D<15:8>

373 A<x:0>

D<7:0>

A<19:0>A<x:0>

D<7:0>

373

OE

WRH

OE OEWR(1) WR(1)

CE CE

Note 1: This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”.

WRL

D<7:0>

(LSB)(MSB)PIC18F8X8X

D<7:0>

AD<15:8>

Address Bus

Data Bus

Control Lines

CE

PIC18F6585/8585/6680/8680

6.2.2 16-BIT WORD WRITE MODE

Figure 6-2 shows an example of 16-bit Word Writemode for PIC18F8X8X devices.

FIGURE 6-2: 16-BIT WORD WRITE MODE EXAMPLE

AD<7:0>

PIC18F8X8X

AD<15:8>

ALE

373 A<20:1>

373

OE

WRH

A<19:16>

A<x:0>

D<15:0>

OE WR(1) CE

D<15:0>

JEDEC Word EPROM Memory

Address Bus

Data Bus

Control Lines


CE

PIC18F6585/8585/6680/8680

6.2.3 16-BIT BYTE SELECT MODE

Figure 6-3 shows an example of 16-bit Byte Selectmode for PIC18F8X8X devices.

FIGURE 6-3: 16-BIT BYTE SELECT MODE EXAMPLE

AD<7:0>PIC18F8X8X

AD<15:8>

ALE

373 A<20:1>

373

OE

WRH

A<19:16>

WRLBA0

A<20:1>

CE

A0JEDEC Word

A<x:1>

D<15:0>

CED<15:0>

OE

WR(1)

LB

UB

SRAM Memory

LB

UB

Address Bus

Data Bus

Control Lines

PIC18F6585/8585/6680/8680

6.2.4 16-BIT MODE TIMING

Figure 6-4 shows the 16-bit mode external bus timingfor PIC18F8X8X devices.

FIGURE 6-4: EXTERNAL PROGRAM MEMORY BUS TIMING (16-BIT MODE)

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q4Q4 Q4 Q4

ALE

OE

3AABh

WRH

WRL

AD<15:0>

BA0

CF33h

Opcode Fetch

MOVLW 55hfrom 007556h

9256h0E55h

‘1’ ‘1’

‘1’‘1’

Table Read

of 92hfrom 199E67h

1 TCY Wait

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4Apparent Q

Actual Q

A<19:16> Ch0h

PIC18F6585/8585/6680/8680

NOTES:


PIC18F6585/8585/6680/8680

7.0 DATA EEPROM MEMORY

The data EEPROM is readable and writable during nor-mal operation over the entire VDD range. The datamemory is not directly mapped in the register filespace. Instead, it is indirectly addressed through theSpecial Function Registers (SFR).

There are five SFRs used to read and write theprogram and data EEPROM memory. These registersare:

• EECON1• EECON2• EEDATA

• EEADR• EEADRH

The EEPROM data memory allows byte read and write.When interfacing to the data memory block, EEDATAholds the 8-bit data for read/write and EEADR holds theaddress of the EEPROM location being accessed.These devices have 1024 bytes of data EEPROM withan address range from 0h to 3FFh.

The EEPROM data memory is rated for high erase/write cycles. A byte write automatically erases the loca-tion and writes the new data (erase-before-write). Thewrite time is controlled by an on-chip timer. The writetime will vary with voltage and temperature as well asfrom chip to chip. Please refer to parameter D122(Electrical Characteristics, Section 27.0 “ElectricalCharacteristics”) for exact limits.

7.1 EEADRH:EEADR

The address register pair, EEADRH:EEADR, canaddress up to a maximum of 1024 bytes of dataEEPROM.

7.2 EECON1 and EECON2 Registers

EECON1 is the control register for EEPROM memoryaccesses.

EECON2 is not a physical register. Reading EECON2will read all ‘0’s. The EECON2 register is usedexclusively in the EEPROM write sequence.

Control bits RD and WR initiate read and write opera-tions, respectively. These bits cannot be cleared, onlyset in software. They are cleared in hardware at thecompletion of the read or write operation. The inabilityto clear the WR bit in software prevents the accidentalor premature termination of a write operation.

The WREN bit, when set, will allow a write operation.On power-up, the WREN bit is clear. The WRERR bit isset when a write operation is interrupted by a MCLRReset or a WDT Time-out Reset during normal opera-tion. In these situations, the user can check theWRERR bit and rewrite the location. It is necessary toreload the data and address registers (EEDATA andEEADR) due to the Reset condition forcing thecontents of the registers to zero.

Note: Interrupt flag bit, EEIF in the PIR2 register,is set when write is complete. It must becleared in software.


PIC18F6585/8585/6680/8680

REGISTER 7-1: EECON1 REGISTER (ADDRESS FA6h) R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0

EEPGD CFGS — FREE WRERR WREN WR RD

bit 7 bit 0

bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit1 = Access Flash program memory0 = Access data EEPROM memory

bit 6 CFGS: Flash Program/Data EE or Configuration Select bit

1 = Access configuration or calibration registers0 = Access Flash program or data EEPROM memory


bit 4 FREE: Flash Row Erase Enable bit1 = Erase the program memory row addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)0 = Perform write only

bit 3 WRERR: Flash Program/Data EE Error Flag bit1 = A write operation is prematurely terminated (any MCLR or any WDT Reset during self-timed

programming in normal operation)0 = The write operation completed

Note: When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allowstracing of the error condition.

bit 2 WREN: Flash Program/Data EE Write Enable bit1 = Allows write cycles0 = Inhibits write to the EEPROM

bit 1 WR: Write Control bit

1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.(The operation is self-timed and the bit is cleared by hardware once write is complete. TheWR bit can only be set (not cleared) in software.)

0 = Write cycle to the EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read. (Read takes one cycle. RD is cleared in hardware. The RD bitcan only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)

0 = Does not initiate an EEPROM read

Legend:

R = Readable bit U = Unimplemented bit, read as ‘0’

W = Writable bit S = Settable bit - n = Value after erase

‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown


PIC18F6585/8585/6680/8680

7.3 Reading the Data EEPROM Memory

To read a data memory location, the user must write theaddress to the EEADR register, clear the EEPGD con-trol bit (EECON1<7>), clear the CFGS control bit

(EECON1<6>) and then set control bit, RD(EECON1<0>). The data is available for the very nextinstruction cycle; therefore, the EEDATA register canbe read by the next instruction. EEDATA will hold thisvalue until another read operation or until it is written toby the user (during a write operation).

EXAMPLE 7-1: DATA EEPROM READ

7.4 Writing to the Data EEPROM Memory

To write an EEPROM data location, the address mustfirst be written to the EEADRH:EEADR register pairand the data written to the EEDATA register. Then thesequence in Example 7-2 must be followed to initiatethe write cycle.

The write will not initiate if the above sequence is notexactly followed (write 55h to EECON2, write 0AAh toEECON2, then set WR bit) for each byte. It is stronglyrecommended that interrupts be disabled during thiscode segment.

Additionally, the WREN bit in EECON1 must be set toenable writes. This mechanism prevents accidentalwrites to data EEPROM due to unexpected code exe-

cution (i.e., runaway programs). The WREN bit shouldbe kept clear at all times except when updating theEEPROM. The WREN bit is not cleared by hardware.

After a write sequence has been initiated, EECON1,EEADRH:EEADR and EDATA cannot be modified. TheWR bit will be inhibited from being set unless theWREN bit is set. The WREN bit must be set on a pre-vious instruction. Both WR and WREN cannot be setwith the same instruction.

At the completion of the write cycle, the WR bit iscleared in hardware and the EEPROM Write CompleteInterrupt Flag bit (EEIF) is set. The user may eitherenable this interrupt or poll this bit. EEIF must becleared by software.

EXAMPLE 7-2: DATA EEPROM WRITE

MOVLW DATA_EE_ADR_HI ;MOVWF EEADRH ;MOVLW DATA_EE_ADDR_LOW ;MOVWF EEADR ; Data Memory Address to readBCF EECON1, EEPGD ; Point to DATA memoryBCF EECON1, CFGS ; Access program Flash or Data EEPROM memoryBSF EECON1, RD ; EEPROM ReadMOVF EEDATA, W ; W = EEDATA

MOVLW DATA_EE_ADDR_HI ;MOVWF EEADRH ;MOVLW DATA_EE_ADDR_LOW ;MOVWF EEADR ; Data Memory Address to readMOVLW DATA_EE_DATA ; MOVWF EEDATA ; Data Memory Value to writeBCF EECON1, EEPGD ; Point to DATA memoryBCF EECON1, CFGS ; Access program Flash or Data EEPROM memoryBSF EECON1, WREN ; Enable writes

BCF INTCON, GIE ; Disable interruptsRequired MOVLW 55h ;Sequence MOVWF EECON2 ; Write 55h

MOVLW 0AAh ; MOVWF EECON2 ; Write 0AAhBSF EECON1, WR ; Set WR bit to begin writeBSF INTCON, GIE ; Enable interrupts

. ; user code execution

.

.BCF EECON1, WREN ; Disable writes on write complete (EEIF set)

PIC18F6585/8585/6680/8680

7.5 Write Verify

Depending on the application, good programmingpractice may dictate that the value written to the mem-ory should be verified against the original value. Thisshould be used in applications where excessive writescan stress bits near the specification limit.

7.6 Protection Against Spurious Write

There are conditions when the device may not want towrite to the data EEPROM memory. To protect againstspurious EEPROM writes, various mechanisms havebeen built-in. On power-up, the WREN bit is cleared.Also, the Power-up Timer (72 ms duration) preventsEEPROM write.

The write initiate sequence and the WREN bit togetherhelp prevent an accidental write during brown-out,power glitch, or software malfunction.

7.7 Operation During Code-Protect

Data EEPROM memory has its own code-protectmechanism. External read and write operations aredisabled if either of these mechanisms are enabled.

The microcontroller itself can both read and write to theinternal data EEPROM regardless of the state of thecode-protect configuration bit. Refer to Section 24.0“Special Features of the CPU” for additionalinformation.

7.8 Using the Data EEPROM

The data EEPROM is a high endurance, byte address-able array that has been optimized for the storage offrequently changing information (e.g., program vari-ables or other data that are updated often). Frequentlychanging values will typically be updated more oftenthan specification D124. If this is not the case, an arrayrefresh must be performed. For this reason, variablesthat change infrequently (such as constants, IDs,calibration, etc.) should be stored in Flash programmemory.

A simple data EEPROM refresh routine is shown inExample 7-3.

EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE

Note: If data EEPROM is only used to store con-stants and/or data that changes rarely, anarray refresh is likely not required. Seespecification D124.

CLRF EEADRH ;CLRF EEADR ; Start at address 0BCF EECON1, CFGS ; Set for memoryBCF EECON1, EEPGD ; Set for Data EEPROMBCF INTCON, GIE ; Disable interruptsBSF EECON1, WREN ; Enable writes

Loop ; Loop to refresh arrayBSF EECON1, RD ; Read current addressMOVLW 55h ;MOVWF EECON2 ; Write 55hMOVLW 0AAh ;MOVWF EECON2 ; Write 0AAhBSF EECON1, WR ; Set WR bit to begin writeBTFSC EECON1, WR ; Wait for write to completeBRA $-2INCFSZ EEADR, F ; Increment addressBRA Loop ; Not zero, do it again

INCFS2 EEADRH, F ;BRA Loop ;BCF EECON1, WREN ; Disable writesBSF INTCON, GIE ; Enable interrupts


PIC18F6585/8585/6680/8680

TABLE 7-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Value on:POR, BOR


INTCON GIE/GIEH

PEIE/GIEL

T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

EEADRH — — — — — — EE Addr High ---- --00 ---- --00

EEADR EEPROM Address Register 0000 0000 0000 0000

EEDATA EEPROM Data Register 0000 0000 0000 0000

EECON2 EEPROM Control Register 2 (not a physical register) — —

EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 uu-0 u000

IPR2 — CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 ---1 1111

PIR2 — CMIF — EEIF BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 ---0 0000

PIE2 — CMIE — EEIE BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 ---0 0000

Legend: x = unknown, u = unchanged, r = reserved, – = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.


PIC18F6585/8585/6680/8680

NOTES:


PIC18F6585/8585/6680/8680

8.0 8 x 8 HARDWARE MULTIPLIER

8.1 Introduction

An 8 x 8 hardware multiplier is included in the ALU ofthe PIC18F6585/8585/6680/8680 devices. By makingthe multiply a hardware operation, it completes in a sin-gle instruction cycle. This is an unsigned multiply thatgives a 16-bit result. The result is stored in the 16-bitproduct register pair (PRODH:PRODL). The multiplierdoes not affect any flags in the ALUSTA register.

Making the 8 x 8 multiplier execute in a single cyclegives the following advantages:

• Higher computational throughput• Reduces code size requirements for multiply

algorithms

The performance increase allows the device to be usedin applications previously reserved for Digital SignalProcessors.

Table 8-1 shows a performance comparison betweenenhanced devices using the single-cycle hardwaremultiply and performing the same function without thehardware multiply.

8.2 Operation

Example 8-1 shows the sequence to do an 8 x 8unsigned multiply. Only one instruction is requiredwhen one argument of the multiply is already loaded inthe WREG register.

Example 8-2 shows the sequence to do an 8 x 8 signedmultiply. To account for the sign bits of the arguments,each argument’s Most Significant bit (MSb) is testedand the appropriate subtractions are done.

EXAMPLE 8-1: 8 x 8 UNSIGNED MULTIPLY ROUTINE

EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY ROUTINE

TABLE 8-1: PERFORMANCE COMPARISON

MOVF ARG1, W ; MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL

MOVF ARG1, W ;MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL BTFSC ARG2, SB ; Test Sign Bit SUBWF PRODH ; PRODH = PRODH

; - ARG1 MOVF ARG2, W ;BTFSC ARG1, SB ; Test Sign Bit SUBWF PRODH ; PRODH = PRODH

; - ARG2

Routine Multiply MethodProgramMemory(Words)

Cycles(Max)

Time

@ 40 MHz @ 10 MHz @ 4 MHz

8 x 8 unsignedWithout hardware multiply 13 69 6.9 µs 27.6 µs 69 µs

Hardware multiply 1 1 100 ns 400 ns 1 µs

8 x 8 signedWithout hardware multiply 33 91 9.1 µs 36.4 µs 91 µs

Hardware multiply 6 6 600 ns 2.4 µs 6 µs

16 x 16 unsignedWithout hardware multiply 21 242 24.2 µs 96.8 µs 242 µs

Hardware multiply 24 24 2.4 µs 9.6 µs 24 µs

16 x 16 signedWithout hardware multiply 52 254 25.4 µs 102.6 µs 254 µs

Hardware multiply 36 36 3.6 µs 14.4 µs 36 µs


PIC18F6585/8585/6680/8680

Example 8-3 shows the sequence to do a 16 x 16unsigned multiply. Equation 8-1 shows the algorithmthat is used. The 32-bit result is stored in four registers,RES3:RES0.

EQUATION 8-1: 16 x 16 UNSIGNED MULTIPLICATION ALGORITHM

EXAMPLE 8-3: 16 x 16 UNSIGNED MULTIPLY ROUTINE

Example 8-4 shows the sequence to do a 16 x 16signed multiply. Equation 8-2 shows the algorithmused. The 32-bit result is stored in four registers,RES3:RES0. To account for the sign bits of the argu-ments, each argument pairs’ Most Significant bit (MSb)is tested and the appropriate subtractions are done.

EQUATION 8-2: 16 x 16 SIGNED MULTIPLICATION ALGORITHM

EXAMPLE 8-4: 16 x 16 SIGNED MULTIPLY ROUTINE

MOVF ARG1L, W MULWF ARG2L ; ARG1L * ARG2L ->

; PRODH:PRODL MOVFF PRODH, RES1 ; MOVFF PRODL, RES0 ;

; MOVF ARG1H, W MULWF ARG2H ; ARG1H * ARG2H ->


; MOVF ARG1L, W MULWF ARG2H ; ARG1L * ARG2H ->

; PRODH:PRODL MOVF PRODL, W ; ADDWF RES1 ; Add cross MOVF PRODH, W ; products ADDWFC RES2 ; CLRF WREG ; ADDWFC RES3 ;

; MOVF ARG1H, W ; MULWF ARG2L ; ARG1H * ARG2L ->


RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L= (ARG1H • ARG2H • 216) +

(ARG1H • ARG2L • 28) +(ARG1L • ARG2H • 28) +(ARG1L • ARG2L)

MOVF ARG1L, W MULWF ARG2L ; ARG1L * ARG2L ->


; MOVF ARG1H, W MULWF ARG2H ; ARG1H * ARG2H ->


; MOVF ARG1L, W MULWF ARG2H ; ARG1L * ARG2H ->


; MOVF ARG1H, W ; MULWF ARG2L ; ARG1H * ARG2L ->


; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? BRA SIGN_ARG1 ; no, check ARG1 MOVF ARG1L, W ; SUBWF RES2 ; MOVF ARG1H, W ; SUBWFB RES3

; SIGN_ARG1

BTFSS ARG1H, 7 ; ARG1H:ARG1L neg? BRA CONT_CODE ; no, done MOVF ARG2L, W ; SUBWF RES2 ; MOVF ARG2H, W ; SUBWFB RES3

; CONT_CODE :

RES3:RES0= ARG1H:ARG1L • ARG2H:ARG2L= (ARG1H • ARG2H • 216) +

(ARG1H • ARG2L • 28) +(ARG1L • ARG2H • 28) +(ARG1L • ARG2L) +(-1 • ARG2H<7> • ARG1H:ARG1L • 216) +(-1 • ARG1H<7> • ARG2H:ARG2L • 216)

PIC18F6585/8585/6680/8680

9.0 INTERRUPTS

The PIC18F6585/8585/6680/8680 devices have multi-ple interrupt sources and an interrupt priority featurethat allows each interrupt source to be assigned a highor a low priority level. The high priority interrupt vectoris at 000008h while the low priority interrupt vector is at000018h. High priority interrupt events will override anylow priority interrupts that may be in progress.

There are thirteen registers which are used to controlinterrupt operation. They are:

• RCON

• INTCON• INTCON2• INTCON3

• PIR1, PIR2, PIR3• PIE1, PIE2, PIE3• IPR1, IPR2, IPR3

It is recommended that the Microchip header filessupplied with MPLAB® IDE be used for the symbolic bitnames in these registers. This allows the assembler/compiler to automatically take care of the placement ofthese bits within the specified register.

Each interrupt source (except INT0) has three bits tocontrol its operation. The functions of these bits are:

• Flag bit to indicate that an interrupt event occurred

• Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set

• Priority bit to select high priority or low priority

The interrupt priority feature is enabled by setting theIPEN bit (RCON<7>). When interrupt priority isenabled, there are two bits which enable interruptsglobally. Setting the GIEH bit (INTCON<7>) enables allinterrupts that have the priority bit set. Setting the GIELbit (INTCON<6>) enables all interrupts that have thepriority bit cleared. When the interrupt flag, enable bitand appropriate global interrupt enable bit are set, theinterrupt will vector immediately to address 000008h or000018h depending on the priority level. Individualinterrupts can be disabled through their correspondingenable bits.

When the IPEN bit is cleared (default state), theinterrupt priority feature is disabled and interrupts arecompatible with PICmicro® mid-range devices. In Com-patibility mode, the interrupt priority bits for each sourcehave no effect. INTCON<6> is the PEIE bit whichenables/disables all peripheral interrupt sources.INTCON<7> is the GIE bit which enables/disables allinterrupt sources. All interrupts branch to address000008h in Compatibility mode.

When an interrupt is responded to, the global interruptenable bit is cleared to disable further interrupts. If theIPEN bit is cleared, this is the GIE bit. If interrupt prioritylevels are used, this will be either the GIEH or GIEL bit.High priority interrupt sources can interrupt a lowpriority interrupt.

The return address is pushed onto the stack and thePC is loaded with the interrupt vector address(000008h or 000018h). Once in the Interrupt ServiceRoutine, the source(s) of the interrupt can be deter-mined by polling the interrupt flag bits. The interruptflag bits must be cleared in software before re-enablinginterrupts to avoid recursive interrupts.

The “return from interrupt” instruction, RETFIE, exitsthe interrupt routine and sets the GIE bit (GIEH or GIELif priority levels are used) which re-enables interrupts.

For external interrupt events, such as the INT pins orthe PORTB input change interrupt, the interrupt latencywill be three to four instruction cycles. The exactlatency is the same for one- or two-cycle instructions.Individual interrupt flag bits are set regardless of thestatus of their corresponding enable bit or the GIE bit.

PIC18F6585/8585/6680/8680

FIGURE 9-1: INTERRUPT LOGIC

TMR0IE

GIEH/GIE

GIEL/PEIE

Wake-up if in Sleep Mode

Interrupt to CPUVector to Location0008h

INT2IFINT2IEINT2IP

INT1IFINT1IEINT1IP

TMR0IFTMR0IETMR0IP

RBIFRBIERBIP

IPEN

TMR0IF

TMR0IP

INT1IFINT1IEINT1IPINT2IFINT2IEINT2IP

RBIFRBIERBIP

INT0IFINT0IE

GIEL/PEIE

Interrupt to CPUVector to Location

IPEN

IPE

0018h

Peripheral Interrupt Flag bitPeripheral Interrupt Enable bitPeripheral Interrupt Priority bit

Peripheral Interrupt Flag bitPeripheral Interrupt Enable bitPeripheral Interrupt Priority bit

TMR1IFTMR1IETMR1IP

XXXXIFXXXXIEXXXXIP

Additional Peripheral Interrupts

TMR1IFTMR1IETMR1IP

High Priority Interrupt Generation

Low Priority Interrupt Generation

XXXXIFXXXXIEXXXXIP

Additional Peripheral Interrupts

GIE/GEIH


PIC18F6585/8585/6680/8680

9.1 INTCON Registers

The INTCON registers are readable and writableregisters which contain various enable, priority and flagbits.

REGISTER 9-1: INTCON REGISTER

Note: Interrupt flag bits are set when an interruptcondition occurs regardless of the state ofits corresponding enable bit or the globalenable bit. User software should ensurethe appropriate interrupt flag bits are clearprior to enabling an interrupt. This featureallows for software polling.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF

bit 7 bit 0

bit 7 GIE/GIEH: Global Interrupt Enable bit

When IPEN (RCON<7>) = 0:1 = Enables all unmasked interrupts0 = Disables all interrupts When IPEN (RCON<7>) = 1:1 = Enables all high priority interrupts 0 = Disables all interrupts

bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit

When IPEN (RCON<7>) = 0:1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN (RCON<7>) = 1:1 = Enables all low priority peripheral interrupts 0 = Disables all low priority peripheral interrupts

bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 overflow interrupt0 = Disables the TMR0 overflow interrupt

bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt

bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt

bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow

bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur

bit 0 RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state

Note: A mismatch condition will continue to set this bit. Reading PORTB will end themismatch condition and allow the bit to be cleared.

Legend:

PIC18F6585/8585/6680/8680

REGISTER 9-2: INTCON2 REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP

bit 7 bit 0

bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values

bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge


bit 4 INTEDG2: External Interrupt 2 Edge Select bit

1 = Interrupt on rising edge 0 = Interrupt on falling edge


bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority

bit 1 INT3IP: INT3 External Interrupt Priority bit

1 = High priority 0 = Low priority

bit 0 RBIP: RB Port Change Interrupt Priority bit1 = High priority 0 = Low priority

Legend:



Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the stateof its corresponding enable bit or the global enable bit. User software should ensurethe appropriate interrupt flag bits are clear prior to enabling an interrupt. This featureallows for software polling.


PIC18F6585/8585/6680/8680

REGISTER 9-3: INTCON3 REGISTER


INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF

bit 7 bit 0

bit 7 INT2IP: INT2 External Interrupt Priority bit1 = High priority 0 = Low priority

bit 6 INT1IP: INT1 External Interrupt Priority bit


bit 5 INT3IE: INT3 External Interrupt Enable bit1 = Enables the INT3 external interrupt 0 = Disables the INT3 external interrupt

bit 4 INT2IE: INT2 External Interrupt Enable bit1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt

bit 3 INT1IE: INT1 External Interrupt Enable bit

1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt

bit 2 INT3IF: INT3 External Interrupt Flag bit1 = The INT3 external interrupt occurred (must be cleared in software) 0 = The INT3 external interrupt did not occur

bit 1 INT2IF: INT2 External Interrupt Flag bit1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur

bit 0 INT1IF: INT1 External Interrupt Flag bit

1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur

Legend:



Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the stateof its corresponding enable bit or the global enable bit. User software should ensurethe appropriate interrupt flag bits are clear prior to enabling an interrupt. This featureallows for software polling.


PIC18F6585/8585/6680/8680

9.2 PIR Registers

The PIR registers contain the individual flag bits for theperipheral interrupts. Due to the number of peripheralinterrupt sources, there are three Peripheral InterruptFlag registers (PIR1, PIR2 and PIR3).

REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1

Note 1: Interrupt flag bits are set when an interruptcondition occurs regardless of the state ofits corresponding enable bit or the globalenable bit, GIE (INTCON<7>).

2: User software should ensure the appropri-ate interrupt flag bits are cleared prior toenabling an interrupt, and after servicingthat interrupt.

R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF

bit 7 bit 0

bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1)

1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred

bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete

bit 5 RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The USART receive buffer is empty

bit 4 TXIF: USART Transmit Interrupt Flag bit

1 = The USART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The USART transmit buffer is full

bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software)0 = Waiting to transmit/receive

bit 2 CCP1IF: Enhanced CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred

PWM mode: Unused in this mode.

bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred

bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software)0 = TMR1 register did not overflow

Note 1: Available in Microcontroller mode only.

Legend:

PIC18F6585/8585/6680/8680

REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— CMIF — EEIF BCLIF LVDIF TMR3IF CCP2IF

bit 7 bit 0


bit 6 CMIF: Comparator Interrupt Flag bit

1 = The comparator input has changed (must be cleared in software)0 = The comparator input has not changed


bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit1 = The write operation is complete (must be cleared in software)0 = The write operation is not complete, or has not been started

bit 3 BCLIF: Bus Collision Interrupt Flag bit

1 = A bus collision occurred while the SSP module (configured in I2C Master mode) was transmitting (must be cleared in software)

0 = No bus collision occurred

bit 2 LVDIF: Low-Voltage Detect Interrupt Flag bit 1 = A low-voltage condition occurred (must be cleared in software)0 = The device voltage is above the Low-Voltage Detect trip point

bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit

1 = TMR3 register overflowed (must be cleared in software)0 = TMR3 register did not overflow

bit 0 CCP2IF: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR1 or TMR3 register capture occurred (must be cleared in software) 0 = No TMR1 or TMR3 register capture occurred Compare mode: 1 = A TMR1 or TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1 or TMR3 register compare match occurred

PWM mode:Unused in this mode.

Legend:




PIC18F6585/8585/6680/8680

REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IRXIF WAKIF ERRIF TXB2IF/TXBnIF

TXB1IF(1) TXB0IF(1) RXB1IF/ RXBnIF

RXB0IF/FIFOWMIF

bit 7 bit 0

bit 7 IRXIF: CAN Invalid Received Message Interrupt Flag bit1 = An invalid message has occurred on the CAN bus 0 = No invalid message on CAN bus

bit 6 WAKIF: CAN bus Activity Wake-up Interrupt Flag bit1 = Activity on CAN bus has occurred 0 = No activity on CAN bus

bit 5 ERRIF: CAN bus Error Interrupt Flag bit1 = An error has occurred in the CAN module (multiple sources) 0 = No CAN module errors

bit 4 When CAN is in Mode 0:TXB2IF: CAN Transmit Buffer 2 Interrupt Flag bit1 = Transmit Buffer 2 has completed transmission of a message and may be reloaded0 = Transmit Buffer 2 has not completed transmission of a messageWhen CAN is in Mode 1 or 2:TXBnIF: Any Transmit Buffer Interrupt Flag bit1 = One or more transmit buffers has completed transmission of a message and may be

reloaded (TXBIE or BIE0<7:2> must be non-zero)0 = No message was transmitted

bit 3 TXB1IF: CAN Transmit Buffer 1 Interrupt Flag bit(1)

1 = Transmit Buffer 1 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 1 has not completed transmission of a message



bit 1 When CAN is in Mode 0:RXB1IF: CAN Receive Buffer 1 Interrupt Flag bit1 = Receive Buffer 1 has received a new message 0 = Receive Buffer 1 has not received a new message When CAN is in Mode 1 or 2:RXBnIF: CAN Receive Buffer Interrupt Flag bit1 = One or more receive buffers has received a new message 0 = No receive buffer has received a new message

bit 0 When CAN is in Mode 0:RXB0IF: CAN Receive Buffer 0 Interrupt Flag bit(1)

1 = Receive Buffer 0 has received a new message 0 = Receive Buffer 0 has not received a new messageWhen CAN is in Mode 1:Unimplemented: Read as ‘0’When CAN is in Mode 2:FIFOWMIF: FIFO Watermark Interrupt Flag bit1 = FIFO high watermark is reached 0 = FIFO high watermark is not reached

Legend:

PIC18F6585/8585/6680/8680

9.3 PIE Registers

The PIE registers contain the individual enable bits forthe peripheral interrupts. Due to the number ofperipheral interrupt sources, there are three PeripheralInterrupt Enable registers (PIE1, PIE2 and PIE3).When the IPEN bit (RCON<7>) is ‘0’, the PEIE bit mustbe set to enable any of these peripheral interrupts.

REGISTER 9-7: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE

bit 7 bit 0

bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1)

1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt


bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt

bit 5 RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt

bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt

bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt

bit 2 CCP1IE: Enhanced CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt

bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt

Legend:

PIC18F6585/8585/6680/8680

REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— CMIE — EEIE BCLIE LVDIE TMR3IE CCP2IE

bit 7 bit 0


bit 6 CMIE: Comparator Interrupt Enable bit

1 = Enables the comparator interrupt0 = Disables the comparator interrupt


bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit 1 = Enables the write operation interrupt0 = Disables the write operation interrupt

bit 3 BCLIE: Bus Collision Interrupt Enable bit

1 = Enables the bus collision interrupt0 = Disables the bus collision interrupt

bit 2 LVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Enables the Low-Voltage Detect interrupt0 = Disables the Low-Voltage Detect interrupt

bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enables the TMR3 overflow interrupt 0 = Disables the TMR3 overflow interrupt

bit 0 CCP2IE: CCP2 Interrupt Enable bit

1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt

Legend:




PIC18F6585/8585/6680/8680

REGISTER 9-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IRXIE WAKIE ERRIE TXB2IE/ TXBnIE

TXB1IE(1) TXB0IE(1) RXB1IE/ RXBnIE

RXB0IE/FIFOWMIE

bit 7 bit 0

bit 7 IRXIE: CAN Invalid Received Message Interrupt Enable bit1 = Enable invalid message received interrupt 0 = Disable invalid message received interrupt

bit 6 WAKIE: CAN bus Activity Wake-up Interrupt Enable bit

1 = Enable bus activity wake-up interrupt 0 = Disable bus activity wake-up interrupt

bit 5 ERRIE: CAN bus Error Interrupt Enable bit1 = Enable CAN bus error interrupt 0 = Disable CAN bus error interrupt

bit 4 When CAN is in Mode 0:TXB2IE: CAN Transmit Buffer 2 Interrupt Enable bit1 = Enable Transmit Buffer 2 interrupt 0 = Disable Transmit Buffer 2 interruptWhen CAN is in Mode 1 or 2:TXBnIE: CAN Transmit Buffer Interrupts Enable bit1 = Enable transmit buffer interrupt; individual interrupt is enabled by TXBIE and BIE0 0 = Disable all transmit buffer interrupts

bit 3 TXB1IE: CAN Transmit Buffer 1 Interrupt Enable bit(1)

1 = Enable Transmit Buffer 1 interrupt 0 = Disable Transmit Buffer 1 interrupt



bit 1 When CAN is in Mode 0:RXB1IE: CAN Receive Buffer 1 Interrupt Enable bit1 = Enable Receive Buffer 1 interrupt 0 = Disable Receive Buffer 1 interrupt When CAN is in Mode 1 or 2:RXBnIE: CAN Receive Buffer Interrupts Enable bit

1 = Enable receive buffer interrupt; individual interrupt is enabled by BIE0 0 = Disable all receive buffer interrupts

bit 0 When CAN is in Mode 0:RXB0IE: CAN Receive Buffer 0 Interrupt Enable bit1 = Enable Receive Buffer 0 interrupt 0 = Disable Receive Buffer 0 interrupt When CAN is in Mode 1:Unimplemented: Read as ‘0’When CAN is in Mode 2:FIFOWMIE: FIFO Watermark Interrupt Enable bit1 = Enable FIFO watermark interrupt 0 = Disable FIFO watermark interrupt

Note 1: In CAN Mode 1 and 2, this bit is forced to ‘0’.

Legend:




PIC18F6585/8585/6680/8680

9.4 IPR Registers

The IPR registers contain the individual priority bits forthe peripheral interrupts. Due to the number ofperipheral interrupt sources, there are three PeripheralInterrupt Priority registers (IPR1, IPR2 and IPR3). Theoperation of the priority bits requires that the InterruptPriority Enable (IPEN) bit be set.

REGISTER 9-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP

bit 7 bit 0

bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1) 1 = High priority 0 = Low priority


bit 6 ADIP: A/D Converter Interrupt Priority bit


bit 5 RCIP: USART Receive Interrupt Priority bit 1 = High priority 0 = Low priority

bit 4 TXIP: USART Transmit Interrupt Priority bit


bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority

bit 2 CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority

bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit



Legend:




PIC18F6585/8585/6680/8680

REGISTER 9-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 U-0 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP

bit 7 bit 0


bit 6 CMIP: Comparator Interrupt Priority bit

1 = High priority0 = Low priority


bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit 1 = High priority0 = Low priority

bit 3 BCLIP: Bus Collision Interrupt Priority bit


bit 2 LVDIP: Low-Voltage Detect Interrupt Priority bit 1 = High priority0 = Low priority


bit 0 CCP2IP: CCP2 Interrupt Priority bit


Legend:




PIC18F6585/8585/6680/8680

REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

IRXIP WAKIP ERRIP TXB2IP/ TXBnIP

TXB1IP(1) TXB0IP(1) RXB1IP/RXBnIP

RXB0IP/FIFOWMIP

bit 7 bit 0

bit 7 IRXIP: CAN Invalid Received Message Interrupt Priority bit1 = High priority 0 = Low priority

bit 6 WAKIP: CAN bus Activity Wake-up Interrupt Priority bit


bit 5 ERRIP: CAN bus Error Interrupt Priority bit1 = High priority 0 = Low priority

bit 4 When CAN is in Mode 0:TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit1 = High priority 0 = Low priority When CAN is in Mode 1 or 2:TXBnIP: CAN Transmit Buffer Interrupt Priority bit1 = High priority 0 = Low priority

bit 3 TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit(1)




bit 1 When CAN is in Mode 0:RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit1 = High priority 0 = Low priority When CAN is in Mode 1 or 2:RXBnIP: CAN Receive Buffer Interrupts Priority bit


bit 0 When CAN is in Mode 0:RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit1 = High priority 0 = Low priority When CAN is in Mode 1:Unimplemented: Read as ‘0’When CAN is in Mode 2:FIFOWMIP: FIFO Watermark Interrupt Priority bit1 = High priority 0 = Low priority


Legend:




PIC18F6585/8585/6680/8680

9.5 RCON Register

The RCON register contains the IPEN bit which is usedto enable prioritized interrupts. The functions of theother bits in this register are discussed in more detail inSection 4.14 “RCON Register”.

REGISTER 9-13: RCON REGISTER R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0


bit 7 bit 0

bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts0 = Disable priority levels on interrupts (PIC16 Compatibility mode)


bit 4 RI: RESET Instruction Flag bit

For details of bit operation, see Register 4-4.

bit 3 TO: Watchdog Time-out Flag bit


bit 2 PD: Power-down Detection Flag bit


bit 1 POR: Power-on Reset Status bit


bit 0 BOR: Brown-out Reset Status bit


Legend:




PIC18F6585/8585/6680/8680

9.6 INT0 Interrupt

External interrupts on the RB0/INT0, RB1/INT1, RB2/INT2 and RB3/INT3 pins are edge-triggered: either ris-ing if the corresponding INTEDGx bit is set in theINTCON2 register, or falling if the INTEDGx bit is clear.When a valid edge appears on the RBx/INTx pin, thecorresponding flag bit, INTxF, is set. This interrupt canbe disabled by clearing the corresponding enable bit,INTxE. Flag bit, INTxF, must be cleared in software inthe Interrupt Service Routine before re-enabling theinterrupt. All external interrupts (INT0, INT1, INT2 andINT3) can wake-up the processor from Sleep if bitINTxIE was set prior to going into Sleep. If the globalinterrupt enable bit GIE is set, the processor will branchto the interrupt vector following wake-up.

The interrupt priority for INT, INT2 and INT3 is deter-mined by the value contained in the interrupt prioritybits: INT1IP (INTCON3<6>), INT2IP (INTCON3<7>)and INT3IP (INTCON2<1>). There is no priority bitassociated with INT0; it is always a high priorityinterrupt source.

9.7 TMR0 Interrupt

In 8-bit mode (which is the default), an overflow in theTMR0 register (0FFh → 00h) will set flag bit TMR0IF. In16-bit mode, an overflow in the TMR0H:TMR0L regis-ters (0FFFFh → 0000h) will set flag bit, TMR0IF. Theinterrupt can be enabled/disabled by setting/clearingenable bit, TMR0IE (INTCON<5>). Interrupt priority forTimer0 is determined by the value contained in theinterrupt priority bit, TMR0IP (INTCON2<2>). SeeSection 11.0 “Timer0 Module” for further details onthe Timer0 module.

9.8 PORTB Interrupt-on-Change

An input change on PORTB<7:4> sets flag bit RBIF(INTCON<0>). The interrupt can be enabled/disabledby setting/clearing enable bit, RBIE (INTCON<3>).Interrupt priority for PORTB interrupt-on-change isdetermined by the value contained in the interruptpriority bit, RBIP (INTCON2<0>).

9.9 Context Saving During Interrupts

During an interrupt, the return PC value is saved on thestack. Additionally, the WREG, Status and BSR registersare saved on the fast return stack. If a fast return frominterrupt is not used (See Section 4.3 “Fast RegisterStack”), the user may need to save the WREG, Statusand BSR registers in software. Depending on the user’sapplication, other registers may also need to be saved.Example 9-1 saves and restores the WREG, Status andBSR registers during an Interrupt Service Routine.

EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP ; W_TEMP is in virtual bankMOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhereMOVFF BSR, BSR_TEMP ; BSR located anywhere;; USER ISR CODE;MOVFF BSR_TEMP, BSR ; Restore BSRMOVF W_TEMP, W ; Restore WREGMOVFF STATUS_TEMP, STATUS ; Restore STATUS

PIC18F6585/8585/6680/8680

10.0 I/O PORTS

Depending on the device selected, there are either sevenor nine I/O ports available on PIC18F6X8X/8X8Xdevices. Some of their pins are multiplexed with one ormore alternate functions from the other peripheral fea-tures on the device. In general, when a peripheral isenabled, that pin may not be used as a general purposeI/O pin.

Each port has three registers for its operation. Theseregisters are:

• TRIS register (data direction register)

• PORT register (reads the levels on the pins of the device)

• LAT register (output latch)

The Data Latch register (LAT) is useful for read-modify-write operations on the value that the I/O pins aredriving.

A simplified version of a generic I/O port and itsoperation is shown in Figure 10-1.

FIGURE 10-1: SIMPLIFIED BLOCK DIAGRAM OF PORT/LAT/TRIS OPERATION

10.1 PORTA, TRISA and LATA Registers

PORTA is a 7-bit wide, bidirectional port. The corre-sponding data direction register is TRISA. Setting aTRISA bit (= 1) will make the corresponding PORTA pinan input (i.e., put the corresponding output driver in ahigh-impedance mode). Clearing a TRISA bit (= 0) willmake the corresponding PORTA pin an output (i.e., putthe contents of the output latch on the selected pin).

Reading the PORTA register reads the status of thepins, whereas writing to it will write to the port latch.

The Data Latch register (LATA) is also memorymapped. Read-modify-write operations on the LATAregister read and write the latched output value forPORTA.

The RA4 pin is multiplexed with the Timer0 moduleclock input to become the RA4/T0CKI pin. TheRA4/T0CKI pin is a Schmitt Trigger input and an open-drain output. All other RA port pins have TTL inputlevels and full CMOS output drivers.

The RA6 pin is only enabled as a general I/O pin inECIO and RCIO Oscillator modes.

The other PORTA pins are multiplexed with analoginputs and the analog VREF+ and VREF- inputs. Theoperation of each pin is selected by clearing/setting thecontrol bits in the ADCON1 register (A/D ControlRegister 1).

The TRISA register controls the direction of the RA pinseven when they are being used as analog inputs. Theuser must ensure the bits in the TRISA register aremaintained set when using them as analog inputs.

EXAMPLE 10-1: INITIALIZING PORTA

QD

CK

WR LAT +

Data Latch

I/O pinRD Port

WR Port

TRIS

RD LAT

Data Bus

Note: On a Power-on Reset, RA5 and RA3:RA0are configured as analog inputs and readas ‘0’. RA6 and RA4 are configured asdigital inputs.

CLRF PORTA ; Initialize PORTA by; clearing output; data latches

CLRF LATA ; Alternate method; to clear output; data latches

MOVLW 0Fh ; Configure A/D MOVWF ADCON1 ; for digital inputsMOVLW 0CFh ; Value used to

; initialize data ; direction

MOVWF TRISA ; Set RA<3:0> as inputs; RA<5:4> as outputs

PIC18F6585/8585/6680/8680

FIGURE 10-2: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS

FIGURE 10-3: BLOCK DIAGRAM OF RA4/T0CKI PIN

FIGURE 10-4: BLOCK DIAGRAM OF RA6 PIN (WHEN ENABLED AS I/O)

DataBus

QD

QCK

QD

QCK

Q D

EN

P

N

WR LATA

WR TRISA

Data Latch

TRIS Latch

RD TRISA

RD PORTA

VSS

VDD

I/O pin(1)

Note 1: I/O pins have protection diodes to VDD and VSS.

AnalogInputMode

TTLInputBuffer

To A/D Converter and LVD Modules

RD LATA

orPORTA

DataBus

WR TRISA

RD PORTA

Data Latch

TRIS Latch

SchmittTriggerInputBuffer

N

VSS

I/O pin(1)

TMR0 Clock Input

QD

QCK

QD

QCK

EN

Q D

EN

RD LATA

WR LATAorPORTA

RD TRISA


Data Bus

QD

QCK

Q D

EN

P

N

WR LATA

WR

Data Latch

TRIS Latch

RD

RD PORTA

VSS

VDD

I/O pin(1)


or PORTA

RD LATA

ECRA6 or

TTLInputBuffer

ECRA6 or RCRA6 Enable

RCRA6 Enable

TRISA

QD

QCK

TRISA


PIC18F6585/8585/6680/8680

TABLE 10-1: PORTA FUNCTIONS

TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit# Buffer Function

RA0/AN0 bit 0 TTL Input/output or analog input.

RA1/AN1 bit 1 TTL Input/output or analog input.

RA2/AN2/VREF- bit 2 TTL Input/output or analog input or VREF-.

RA3/AN3/VREF+ bit 3 TTL Input/output or analog input or VREF+.

RA4/T0CKI bit 4 ST/OD Input/output or external clock input for Timer0. Output is open-drain type.

RA5/AN4/LVDIN bit 5 TTL Input/output or slave select input for synchronous serial port or analog input, or Low-Voltage Detect input.

OSC2/CLKO/RA6 bit 6 TTL OSC2 or clock output, or I/O pin.

Legend: TTL = TTL input, ST = Schmitt Trigger input

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Value on

POR, BOR

Value onall other Resets

PORTA — RA6 RA5 RA4 RA3 RA2 RA1 RA0 -x0x 0000 -u0u 0000

LATA — LATA Data Output Register -xxx xxxx -uuu uuuu

TRISA — PORTA Data Direction Register -111 1111 -111 1111

ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --00 0000

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.


PIC18F6585/8585/6680/8680

10.2 PORTB, TRISB and LATB Registers

PORTB is an 8-bit wide, bidirectional port. The corre-sponding data direction register is TRISB. Setting aTRISB bit (= 1) will make the corresponding PORTBpin an input (i.e., put the corresponding output driver ina high-impedance mode). Clearing a TRISB bit (= 0)will make the corresponding PORTB pin an output (i.e.,put the contents of the output latch on the selected pin).

The Data Latch register (LATB) is also memory mapped.Read-modify-write operations on the LATB register readand write the latched output value for PORTB.

EXAMPLE 10-2: INITIALIZING PORTB

Each of the PORTB pins has a weak internal pull-up. Asingle control bit can turn on all the pull-ups. This isperformed by clearing bit RBPU (INTCON2<7>). Theweak pull-up is automatically turned off when the portpin is configured as an output. The pull-ups aredisabled on a Power-on Reset.

Four of the PORTB pins (RB3:RB0) are the externalinterrupt pins, INT3 through INT0. In order to use thesepins as external interrupts, the corresponding TRISBbit must be set to ‘1’.

The other four PORTB pins (RB7:RB4) have aninterrupt-on-change feature. Only pins configured asinputs can cause this interrupt to occur (i.e., anyRB7:RB4 pin configured as an output is excluded fromthe interrupt-on-change comparison). The input pins (ofRB7:RB4) are compared with the old value latched onthe last read of PORTB. The “mismatch” outputs ofRB7:RB4 are OR’ed together to generate the RB portchange interrupt with flag bit, RBIF (INTCON<0>).

This interrupt can wake the device from Sleep. Theuser, in the Interrupt Service Routine, can clear theinterrupt in the following manner:

a) Any read or write of PORTB (except with theMOVFF instruction). This will end the mismatchcondition.

b) Clear flag bit RBIF.

A mismatch condition will continue to set flag bit, RBIF.Reading PORTB will end the mismatch condition andallow flag bit RBIF to be cleared.

The interrupt-on-change feature is recommended forwake-up on key depression operation and operationswhere PORTB is only used for the interrupt-on-changefeature. Polling of PORTB is not recommended whileusing the interrupt-on-change feature.

For PIC18FXX85 devices, RB3 can be configured by theconfiguration bit, CCP2MX, as the alternate peripheralpin for the CCP2 module. This is only available when thedevice is configured in Microprocessor, Microprocessorwith Boot Block, or Extended Microcontroller Operatingmodes.

The RB5 pin is used as the LVP programming pin.When the LVP configuration bit is programmed, this pinloses the I/O function and becomes a programming testfunction.

FIGURE 10-5: BLOCK DIAGRAM OFRB7:RB4 PINS

Note: On a Power-on Reset, these pins areconfigured as digital inputs.

CLRF PORTB ; Initialize PORTB by; clearing output; data latches

CLRF LATB ; Alternate method; to clear output; data latches

MOVLW 0CFh ; Value used to; initialize data ; direction

MOVWF TRISB ; Set RB<3:0> as inputs; RB<5:4> as outputs; RB<7:6> as inputs

Note: When LVP is enabled, the weak pull-up onRB5 is disabled.

Data Latch

From other

RBPU(2)

P

VDD

I/O pin(1)QD

CK

QD

CK

Q D

EN

Q D

EN

Data Bus

WR LATB

WR TRISB

Set RBIF

TRIS Latch

RD TRISB

RD PORTB

RB7:RB4 pins

WeakPull-up

RD PORTB

Latch

TTLInputBuffer ST

Buffer

RB7:RB5 in Serial Programming Mode

Q3

Q1

RD LATB

or PORTB

Note 1: I/O pins have diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit(s)and clear the RBPU bit (INTCON2<7>).

PIC18F6585/8585/6680/8680

FIGURE 10-6: BLOCK DIAGRAM OF RB2:RB0 PINS

FIGURE 10-7: BLOCK DIAGRAM OF RB3 PIN

Data Latch

RBPU(2)

P

VDD

QD

CK

QD

CK

Q D

EN

Data Bus

WR Port

WR TRIS

RD TRIS

RD Port

WeakPull-up

RD Port

INTx

I/O pin(1)

TTLInputBuffer

Schmitt TriggerBuffer

TRIS Latch

Note 1: I/O pins have diode protection to VDD and VSS.2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).

Data Latch

P

VDD

QD

CK

Q D

EN

Data Bus

WR LATB or

WR TRISB

RD TRISB

RD PORTB

WeakPull-up

CCP2 or INT3

TTLInputBuffer

Schmitt TriggerBuffer

TRIS Latch

RD LATB

WR PORTB

RBPU(2)

CK

D

Enable(3) CCP Output

RD PORTB

CCP Output(3)1

0

P

N

VDD

VSS

I/O pin(1)

Q

CCP2MX

CCP2MX = 0

Note 1: I/O pin has diode protection to VDD and VSS.2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).3: For PIC18FXX85 parts, the CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (= 0) in the Configuration

register and the device is operating in Microprocessor, Microprocessor with Boot Block or Extended Microcontroller mode.

PIC18F6585/8585/6680/8680

TABLE 10-3: PORTB FUNCTIONS

TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Name Bit# Buffer Function

RB0/INT0 bit 0 TTL/ST(1) Input/output pin or external interrupt input 0. Internal software programmable weak pull-up.



RB3/INT3/CCP2(3) bit 3 TTL/ST(4) Input/output pin or external interrupt input 3. Capture 2 input/Compare 2 output/PWM output (when CCP2MX configuration bit is enabled, all PIC18FXX85 operating modes except Microcontroller mode). Internal software programmable weak pull-up.

RB4/KBI0 bit 4 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up.

RB5/KBI1/PGM bit 5 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Low-voltage ICSP enable pin.

RB6/KBI2/PGC bit 6 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming clock.

RB7/KBI3/PGD bit 7 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming data.

Legend: TTL = TTL input, ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.3: RC1 is the alternate assignment for CCP2 when CCP2MX is not set (all operating modes except

Microcontroller mode).4: This buffer is a Schmitt Trigger input when configured as the CCP2 input.


POR, BOR


PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu

LATB LATB Data Output Register xxxx xxxx uuuu uuuu

TRISB PORTB Data Direction Register 1111 1111 1111 1111

INTCON GIE/GIEH

PEIE/GIEL

TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000

INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 1111 1111

INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 1100 0000

Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.


PIC18F6585/8585/6680/8680

10.3 PORTC, TRISC and LATC Registers

PORTC is an 8-bit wide, bidirectional port. The corre-sponding data direction register is TRISC. Setting aTRISC bit (= 1) will make the corresponding PORTCpin an input (i.e., put the corresponding output driver ina high-impedance mode). Clearing a TRISC bit (= 0)will make the corresponding PORTC pin an output (i.e.,put the contents of the output latch on the selected pin).

The Data Latch register (LATC) is also memory mapped.Read-modify-write operations on the LATC register readand write the latched output value for PORTC.

PORTC is multiplexed with several peripheral functions(Table 10-5). PORTC pins have Schmitt Trigger inputbuffers.

When enabling peripheral functions, care should betaken in defining TRIS bits for each PORTC pin. Someperipherals override the TRIS bit to make a pin anoutput, while other peripherals override the TRIS bit tomake a pin an input. The user should refer to the corre-sponding peripheral section for the correct TRIS bitsettings.

The pin override value is not loaded into the TRIS reg-ister. This allows read-modify-write of the TRIS registerwithout concern due to peripheral overrides.

RC1 is normally configured by configuration bit,CCP2MX, as the default peripheral pin of the CCP2module (default/erased state, CCP2MX = 1).

EXAMPLE 10-3: INITIALIZING PORTC

FIGURE 10-8: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)


CLRF PORTC ; Initialize PORTC by; clearing output; data latches

CLRF LATC ; Alternate method; to clear output; data latches

MOVLW 0CFh ; Value used to ; initialize data ; direction

MOVWF TRISC ; Set RC<3:0> as inputs; RC<5:4> as outputs; RC<7:6> as inputs

PORTC/Peripheral Out Select

Data Bus

WR LATC

WR TRISC

Data Latch

TRIS Latch

RD TRISC

QD

QCK

Q D

EN

Peripheral Data Out0

1

QD

QCK

P

N

VDD

VSS

RD PORTC

Peripheral Data In

I/O pin(1)orWR PORTC

RD LATC

SchmittTrigger


2: Peripheral output enable is only active if peripheral select is active.

TRISOverride

Peripheral Output

Logic

TRIS OVERRIDE

Pin Override Peripheral

RC0 Yes Timer1 Osc for Timer1/Timer3

RC1 Yes Timer1 Osc for Timer1/Timer3,

CCP2 I/O

RC2 Yes CCP1 I/O

RC3 Yes SPI/I2C Master Clock

RC4 Yes I2C Data Out

RC5 Yes SPI Data Out

RC6 Yes USART Async Xmit, Sync Clock

RC7 Yes USART Sync Data Out

Enable(2)

PIC18F6585/8585/6680/8680

TABLE 10-5: PORTC FUNCTIONS

TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Name Bit# Buffer Type Function

RC0/T1OSO/T13CKI bit 0 ST Input/output port pin, Timer1 oscillator output or Timer1/Timer3clock input.

RC1/T1OSI/CCP2(1) bit 1 ST Input/output port pin, Timer1 oscillator input or Capture 2 input/Compare 2 output/PWM output (when CCP2MX configuration bit is disabled).

RC2/CCP1/P1A bit 2 ST Input/output port pin or Capture 1 input/Compare 1 output/PWM1 output.

RC3/SCK/SCL bit 3 ST RC3 can also be the synchronous serial clock for both SPI and I2C modes.

RC4/SDI/SDA bit 4 ST RC4 can also be the SPI data in (SPI mode) or data I/O (I2C mode).

RC5/SDO bit 5 ST Input/output port pin or synchronous serial port data output.

RC6/TX/CK bit 6 ST Input/output port pin, addressable USART asynchronous transmit or addressable USART synchronous clock.

RC7/RX/DT bit 7 ST Input/output port pin, addressable USART asynchronous receive or addressable USART synchronous data.

Legend: ST = Schmitt Trigger inputNote 1: RB3 is the alternate assignment for CCP2 when CCP2MX is set.


POR, BOR


PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu

LATC LATC Data Output Register xxxx xxxx uuuu uuuu

TRISC PORTC Data Direction Register 1111 1111 1111 1111

Legend: x = unknown, u = unchanged


PIC18F6585/8585/6680/8680

10.4 PORTD, TRISD and LATD Registers

PORTD is an 8-bit wide, bidirectional port. The corre-sponding data direction register is TRISD. Setting aTRISD bit (= 1) will make the corresponding PORTDpin an input (i.e., put the corresponding output driver ina high-impedance mode). Clearing a TRISD bit (= 0)will make the corresponding PORTD pin an output (i.e.,put the contents of the output latch on the selected pin).

The Data Latch register (LATD) is also memory mapped.Read-modify-write operations on the LATD register readand write the latched output value for PORTD.

PORTD is an 8-bit port with Schmitt Trigger inputbuffers. Each pin is individually configurable as an inputor output.

On PIC18F8X8X devices, PORTD is multiplexed withthe system bus as the external memory interface; I/Oport functions are only available when the system busis disabled by setting the EBDIS bit in the MEMCOMregister (MEMCON<7>). When operating as the exter-nal memory interface, PORTD is the low-order byte ofthe multiplexed address/data bus (AD7:AD0).

PORTD can also be configured as an 8-bit wide micro-processor port (Parallel Slave Port) by setting controlbit, PSPMODE (TRISE<4>). In this mode, the inputbuffers are TTL. See Section 10.10 “Parallel SlavePort (PSP)” for additional information.

EXAMPLE 10-4: INITIALIZING PORTD

FIGURE 10-9: PORTD BLOCK DIAGRAM IN I/O PORT MODE


CLRF PORTD ; Initialize PORTD by ; clearing output ; data latchesCLRF LATD ; Alternate method

; to clear output; data latches


MOVWF TRISD ; Set RD<3:0> as inputs; RD<5:4> as outputs; RD<7:6> as inputs

DataBus

WR LATD

WR TRISD

RD PORTD

Data Latch

TRIS Latch

RD TRISD


I/O pin(1)

QD

CK

QD

CK

EN

Q D

EN

RD LATD

orPORTD

PIC18F6585/8585/6680/8680

FIGURE 10-10: PORTD BLOCK DIAGRAM IN SYSTEM BUS MODE (PIC18F8X8X ONLY)

Instruction Register

Bus EnableData/TRIS Out

Drive Bus

System BusControl

Data Bus

WR LATD

WR TRISD

RD PORTD

Data Latch

TRIS Latch

RD TRISD

TTLInputBuffer

I/O pin(1)

QD

CK

QD

CK

EN

Q D

EN

RD LATD

or PORTD

0

1

Port

Data

Instruction Read



PIC18F6585/8585/6680/8680

TABLE 10-7: PORTD FUNCTIONS

TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD


RD0/PSP0/AD0(2) bit 0 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 0 or address/data bus bit 0.








Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel Slave

Port mode.2: Available in PIC18F8X8X devices only.


POR, BOR

Value on all otherResets

PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu

LATD LATD Data Output Register xxxx xxxx uuuu uuuu

TRISD PORTD Data Direction Register 1111 1111 1111 1111

PSPCON IBF OBF IBOV PSPMODE — — — — 0000 ---- 0000 ----

MEMCON EBDIS — WAIT1 WAIT0 — — WM1 WM0 0-00 --00 0-00 --00

Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.


PIC18F6585/8585/6680/8680

10.5 PORTE, TRISE and LATE Registers

PORTE is an 8-bit wide, bidirectional port. The corre-sponding data direction register is TRISE. Setting aTRISE bit (= 1) will make the corresponding PORTEpin an input (i.e., put the corresponding output driver ina high-impedance mode). Clearing a TRISE bit (= 0)will make the corresponding PORTE pin an output (i.e.,put the contents of the output latch on the selected pin).

Read-modify-write operations on the LATE registerread and write the latched output value for PORTE.

PORTE is an 8-bit port with Schmitt Trigger inputbuffers. Each pin is individually configurable as an inputor output. PORTE is multiplexed with the EnhancedCCP module (Table 10-9).

On PIC18F8X8X devices, PORTE is also multiplexedwith the system bus as the external memory interface;the I/O bus is available only when the system bus isdisabled by setting the EBDIS bit in the MEMCONregister (MEMCON<7>). If the device is configured inMicroprocessor or Extended Microcontroller mode, thenthe PORTE<7:0> becomes the high byte of the address/data bus for the external program memory interface. InMicrocontroller mode, the PORTE<2:0> pins become thecontrol inputs for the Parallel Slave Port when bitPSPMODE (PSPCON<4>) is set. (Refer toSection 4.1.1 “PIC18F8X8X Program MemoryModes” for more information on program memorymodes.)

When the Parallel Slave Port is active, three PORTEpins (RE0/RD/AD8, RE1/WR/AD9 and RE2/CS/AD10)function as its control inputs. This automatically occurswhen the PSPMODE bit (PSPCON<4>) is set. Usersmust also make certain that bits TRISE<2:0> are set toconfigure the pins as digital inputs and the ADCON1register is configured for digital I/O. The PORTE PSPcontrol functions are summarized in Table 10-9.

Pin RE7 can be configured as the alternate peripheralpin for the CCP2 module when the device is operatingin Microcontroller mode. This is done by clearing theconfiguration bit, CCP2MX, in configuration register,CONFIG3H (CONFIG3H<0>).

EXAMPLE 10-5: INITIALIZING PORTE

Note: For PIC18F8X8X (80-pin) devices operat-ing in other than Microcontroller mode,PORTE defaults to the system bus onPower-on Reset.

CLRF PORTE ; Initialize PORTE by; clearing output; data latches

CLRF LATE ; Alternate method; to clear output; data latches

MOVLW 03h ; Value used to ; initialize data ; direction

MOVWF TRISE ; Set RE1:RE0 as inputs; RE7:RE2 as outputs

PIC18F6585/8585/6680/8680

FIGURE 10-11: PORTE BLOCK DIAGRAM IN I/O MODE

FIGURE 10-12: PORTE BLOCK DIAGRAM IN SYSTEM BUS MODE (PIC18F8X8X ONLY)

Peripheral Out Select

Data BusWR LATE

WR TRISE

Data Latch

TRIS Latch

RD TRISE

QD

QCK

Q D

EN

Peripheral Data Out0

1

QD

QCK

P

N

VDD

VSS

RD PORTE

Peripheral Data In

I/O pin(1)or WR PORTE

RD LATE

SchmittTrigger


TRISOverride

Peripheral Enable

TRIS OVERRIDE

Pin Override Peripheral

RE0 Yes External Bus








Instruction Register

Bus Enable

Data/TRIS Out

Drive Bus

System BusControl

Data Bus

WR LATE

WR TRISE

RD PORTE

Data Latch

TRIS Latch

RD TRISE

TTLInputBuffer

I/O pin(1)

QD

CK

QD

CK

EN

Q D

EN

RD LATE

or PORTE

0

1

Port

Data

Instruction Read



PIC18F6585/8585/6680/8680

TABLE 10-9: PORTE FUNCTIONS

TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE


RE0/RD/AD8(2) bit 0 ST/TTL(1) Input/output port pin, read control for Parallel Slave Port or address/data bit 8.For RD (PSP Control mode):1 = Not a read operation0 = Read operation, reads PORTD register (if chip selected)

RE1/WR/AD9(2) bit 1 ST/TTL(1) Input/output port pin, write control for Parallel Slave Port or address/data bit 9.For WR (PSP Control mode):1 = Not a write operation0 = Write operation, writes PORTD register (if chip selected)

RE2/CS/AD10(2) bit 2 ST/TTL(1) Input/output port pin, chip select control for Parallel Slave Port or address/data bit 10.For CS (PSP Control mode):1 = Device is not selected0 = Device is selected

RE3/AD11(2) bit 3 ST/TTL(1) Input/output port pin or address/data bit 11.

RE4/AD12(2) bit 4 ST/TTL(1) Input/output port pin or address/data bit 12.

RE5/AD13/(2)P1C(3) bit 5 ST/TTL(1) Input/output port pin, address/data bit 13 or ECCP1 PWM output C.

RE6/AD14/(2)P1B(3) bit 6 ST/TTL(1) Input/output port pin, address/data bit 13 or ECCP1 PWM output B.

RE7/CCP2/AD15(2) bit 7 ST/TTL(1) Input/output port pin, Capture 2 input/Compare 2 output/PWM output (PIC18F8X20 devices in Microcontroller mode only) or address/data bit 15.

Legend: ST = Schmitt Trigger input, TTL = TTL inputNote 1: Input buffers are Schmitt Triggers when in I/O or CCP mode, and TTL buffers when in System Bus or PSP

Control mode.2: Available in PIC18F8X8X devices only.

3: On PIC18F8X8X devices, these pins may be moved to RHY or RH6 by changing the ECCPMX configuration bit.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Value on: POR, BOR


TRISE PORTE Data Direction Control Register 1111 1111 1111 1111

PORTE Read PORTE pin/Write PORTE Data Latch xxxx xxxx uuuu uuuu

LATE Read PORTE Data Latch/Write PORTE Data Latch xxxx xxxx uuuu uuuu

MEMCON EBDIS — WAIT1 WAIT0 — — WM1 WM0 0-00 --00 0000 --00


Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTE.


PIC18F6585/8585/6680/8680

10.6 PORTF, LATF and TRISF Registers

PORTF is an 8-bit wide, bidirectional port. The corre-sponding data direction register is TRISF. Setting aTRISF bit (= 1) will make the corresponding PORTF pinan input (i.e., put the corresponding output driver in ahigh-impedance mode). Clearing a TRISF bit (= 0) willmake the corresponding PORTF pin an output (i.e., putthe contents of the output latch on the selected pin).

Read-modify-write operations on the LATF registerread and write the latched output value for PORTF.

PORTF is multiplexed with several analog peripheralfunctions, including the A/D converter inputs andcomparator inputs, outputs, and voltage reference.

EXAMPLE 10-6: INITIALIZING PORTF

FIGURE 10-13: PORTF RF1/AN6/C2OUT AND RF2/AN7/C1OUT PINS BLOCK DIAGRAM

Note 1: On a Power-on Reset, the RF6:RF0 pinsare configured as inputs and read as ‘0’.

2: To configure PORTF as digital I/O, turn offcomparators and set ADCON1 value.

CLRF PORTF ; Initialize PORTF by ; clearing output ; data latches

CLRF LATF ; Alternate method ; to clear output ; data latches

MOVLW 07h ; MOVWF CMCON ; Turn off comparatorsMOVLW 0Fh ; MOVWF ADCON1 ; Set PORTF as digital I/OMOVLW 0CFh ; Value used to


MOVWF TRISF ; Set RF3:RF0 as inputs; RF5:RF4 as outputs ; RF7:RF6 as inputs

Port/Comparator Select

Data BusWR LATF or

WR TRISF

Data Latch

TRIS Latch

RD TRISF

QD

QCK

Q D

EN

Comparator Data Out0

1

QD

QCK

P

N

VDD

VSS

RD PORTF

I/O pinWR PORTF

RD LATF

SchmittTrigger


AnalogInputMode

To A/D Converter


PIC18F6585/8585/6680/8680

FIGURE 10-14: RF6:RF3 AND RF0 PINS BLOCK DIAGRAM

FIGURE 10-15: RF7 PIN BLOCK DIAGRAM

DataBus

QD

QCK

QD

QCK

Q D

EN

P

N

WR LATF

WR TRISF

Data Latch

TRIS Latch

RD TRISF

RD PORTF

VSS

VDD

I/O pin

AnalogInputMode

STInputBuffer

To A/D Converter or Comparator Input

RD LATF

orWR PORTF


DataBus

WR LATF

WR TRISF

RD PORTF

Data Latch

TRIS Latch

RD TRISF


I/O pin

QD

CK

QD

CK

EN

Q D

EN

RD LATF

orWR PORTF

Note: I/O pins have diode protection to VDD and VSS.

TTLInputBuffer

SS Input


PIC18F6585/8585/6680/8680

TABLE 10-11: PORTF FUNCTIONS

TABLE 10-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF


RF0/AN5 bit 0 ST Input/output port pin or analog input.

RF1/AN6/C2OUT bit 1 ST Input/output port pin, analog input or comparator 2 output.

RF2/AN7/C1OUT bit 2 ST Input/output port pin, analog input or comparator 1 output.

RF3/AN8/C2IN+ bit 3 ST Input/output port pin, analog input or comparator 2 input (+).

RF4/AN9/C2IN- bit 4 ST Input/output port pin, analog input or comparator 2 input (-).


bit 5 ST Input/output port pin, analog input, comparator 1 input (+) or comparator reference output.

RF6/AN11/C1IN- bit 6 ST Input/output port pin, analog input or comparator 1 input (-).

RF7/SS bit 7 ST/TTL Input/output port pin or slave select pin for synchronous serial port.

Legend: ST = Schmitt Trigger input, TTL = TTL input



TRISF PORTF Data Direction Control Register 1111 1111 1111 1111

PORTF Read PORTF pin/Write PORTF Data Latch xxxx xxxx uuuu uuuu

LATF Read PORTF Data Latch/Write PORTF Data Latch 0000 0000 uuuu uuuu


CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000

CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 0000 0000

Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTF.


PIC18F6585/8585/6680/8680

10.7 PORTG, TRISG and LATG Registers

PORTG is a 6-bit wide port with 5 bidirectional pins and1 unidirectional pin. The corresponding data directionregister is TRISG. Setting a TRISG bit (= 1) will makethe corresponding PORTG pin an input (i.e., put thecorresponding output driver in a high-impedancemode). Clearing a TRISG bit (= 0) will make the corre-sponding PORTG pin an output (i.e., put the contentsof the output latch on the selected pin).

The Data Latch register (LATG) is also memory mapped.Read-modify-write operations on the LATG register readand write the latched output value for PORTG.

Pins RG0-RG2 on PORTG are multiplexed with the CANperipheral. Refer to Section 23.0 “ECAN Module” forproper settings of TRISG when CAN is enabled. RG5 ismultiplexed with MCLR/VPP. Refer to Register 24-5 formore information.

When enabling peripheral functions, care should betaken in defining TRIS bits for each PORTG pin. Someperipherals override the TRIS bit to make a pin an output,while other peripherals override the TRIS bit to make apin an input. The user should refer to the correspondingperipheral section for the correct TRIS bit settings.


EXAMPLE 10-7: INITIALIZING PORT

FIGURE 10-16: RG0/CANTX1 PIN BLOCK DIAGRAM


Note 1: On a Power-on Reset, RG5 is enabled asa digital input only if Master Clearfunctionality is disabled (MCLRE = 0).

2: If the device Master Clear is disabled,verify that either of the following is done toensure proper entry into ICSP mode:a) disable Low-Voltage Programming

(CONFIG4L<2> = 0); orb) make certain that RB5/KBI1/PGM is

held low during entry into ICSP.

CLRF PORTG ; Initialize PORTG by; clearing output; data latches

CLRF LATG ; Alternate method; to clear output; data latches

MOVLW 04h ; Value used to ; initialize data ; direction

MOVWF TRISG ; Set RG1:RG0 as outputs; RG2 as input; RG4:RG3 as inputs

Data Latch

TRIS Latch

RD TRISG

P

VSS

QD

QCK

QD

QCK

EN

Q D

EN

N

VDD0

1

RD PORTG

WR TRISG

Data Bus

I/O pin

TXD

ENDRHI

OPMODE2:OPMODE0 = 000

SchmittTrigger

RD LATG

WR PORTG orWR LATG

PIC18F6585/8585/6680/8680

FIGURE 10-17: RG1/CANTX2 PIN BLOCK DIAGRAM

FIGURE 10-18: RG2/CANRX PIN BLOCK DIAGRAM

FIGURE 10-19: RG3 PIN BLOCK DIAGRAM

Data Latch

TRIS Latch

RD TRISG

P

VSS

QD

QCK

QD

QCK

Q D

EN

N

VDD0

1

WR PORTG or

WR TRISG

Data Bus

RD PORTG

I/O pin

0

1

TXD

CANCLK

TX1SRC

ENDRHI


TX2EN

SchmittTrigger

RD LATG

WR LATG



Data Bus

WR LATG

WR TRISG

RD PORTG

Data Latch

TRIS Latch

RD TRISG

I/O pin

QD

CK

QD

CK

EN

Q D

EN

RD LATG

orWR PORTG

CANRX



Data Bus

WR LATG

WR TRISG

RD PORTG

Data Latch

TRIS Latch

RD TRISG


I/O pin

QD

CK

QD

CK

EN

Q D

EN

RD LATG

orWR PORTG



PIC18F6585/8585/6680/8680

FIGURE 10-20: RG4/P1D PIN BLOCK DIAGRAM

FIGURE 10-21: RG5/MCLR/VPP PIN BLOCK DIAGRAM

Data Bus

WR LATG

WR TRISG

RD PORTG

Data Latch

TRIS Latch

RD TRISG


I/O pinQD

CK

QD

CK

EN

Q D

EN

RD LATG

orWR PORTG

1

0

CCP1 P1D Enable

P1D Out

Auto-Shutdown


RG5/MCLR/VPPData Bus

RD PORTA

RD LATA

SchmittTrigger

MCLRE

RD TRISA

Q D

EN

Latch

Filter

Low-LevelMCLR Detect

High-Voltage Detect

Internal MCLR

HV


PIC18F6585/8585/6680/8680

TABLE 10-13: PORTG FUNCTIONS

TABLE 10-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG


RG0/CANTX1 bit 0 ST Input/output port pin or CAN bus transmit output.

RG1/CANTX2 bit 1 ST Input/output port pin, CAN bus complimentary transmit output or CAN bus bit time clock.

RG2/CANRX bit 2 ST Input/output port pin or CAN bus receive.

RG3 bit 3 ST Input/output port pin.

RG4/P1D bit 4 ST Input/output port pin or ECCP1 PWM output D.

RG5/MCLR/VPP bit 5 ST Master Clear input or programming voltage input (if MCLR is enabled).Input only port pin or programming voltage input (if MCLR is disabled).

Legend: ST = Schmitt Trigger input


POR, BOR


PORTG — — RG5(1) Read PORTF pin/Write PORTF Data Latch --0x xxxx --0u uuuu

LATG — — — LATG Data Output Register ---x xxxx ---u uuuu

TRISG — — — Data Direction Control Register for PORTG ---1 1111 ---1 1111

Legend: x = unknown, u = unchangedNote 1: RG5 is available as an input only when MCLR is disabled.


PIC18F6585/8585/6680/8680

10.8 PORTH, LATH and TRISH Registers

PORTH is an 8-bit wide, bidirectional I/O port. The cor-responding data direction register is TRISH. Setting aTRISH bit (= 1) will make the corresponding PORTHpin an input (i.e., put the corresponding output driver ina high-impedance mode). Clearing a TRISH bit (= 0)will make the corresponding PORTH pin an output (i.e.,put the contents of the output latch on the selected pin).

Read-modify-write operations on the LATH registerread and write the latched output value for PORTH.

Pins RH7:RH4 are multiplexed with analog inputsAN15:AN12. Pins RH3:RH0 are multiplexed with thesystem bus as the external memory interface; they arethe high-order address bits, A19:A16. By default, pinsRH7:RH4 are enabled as A/D inputs and pinsRH3:RH0 are enabled as the system address bus.Register ADCON1 configures RH7:RH4 as I/O or A/Dinputs. Register MEMCON configures RH3:RH0 as I/Oor system bus pins.

Pins RH7 and RH6 can be configured as the alternateperipheral pins for CCP1 PWM output P1B and P1C,respectively. This is done by clearing the configurationbit ECCPMX, in configuration register CONFIG3H(CONFIG3H<1>).

EXAMPLE 10-8: INITIALIZING PORTH

FIGURE 10-22: RH3:RH0 PINS BLOCK DIAGRAM IN I/O MODE

FIGURE 10-23: RH7:RH4 PINS BLOCK DIAGRAM IN I/O MODE

Note: PORTH is available only on PIC18F8X8Xdevices.

Note 1: On Power-on Reset, PORTH pinsRH7:RH4 default to A/D inputs and readas ‘0’.

2: On Power-on Reset, PORTH pinsRH3:RH0 default to system bus signals.

CLRF PORTH ; Initialize PORTH by ; clearing output ; data latches

CLRF LATH ; Alternate method ; to clear output ; data latches

MOVLW 0Fh ; MOVWF ADCON1 ; MOVLW 0CFh ; Value used to


MOVWF TRISH ; Set RH3:RH0 as inputs; RH5:RH4 as outputs ; RH7:RH6 as inputs

DataBus

WR LATH

WR TRISH

RD PORTH

Data Latch

TRIS Latch

RD TRISH


I/O pin(1)

QD

CK

QD

CK

EN

Q D

EN

RD LATH

orPORTH


DataBus

WR LATH

WR TRISH

RD PORTH

Data Latch

TRIS Latch

RD TRISH


I/O pin(1)

QD

CK

QD

CK

EN

Q D

EN

RD LATH

orPORTH

To A/D Converter

PIC18F6585/8585/6680/8680

FIGURE 10-24: RH3:RH0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE

To Instruction Register

External Enable

Address Out

Drive System

System BusControl

Data Bus

WR LATH

WR TRISH

RD PORTH

Data Latch

TRIS Latch

RD TRISH

TTLInputBuffer

I/O pin(1)

QD

CK

QD

CK

EN

Q D

EN

RD LATD

orPORTH

0

1

Port

Data

Instruction Read



PIC18F6585/8585/6680/8680

TABLE 10-15: PORTH FUNCTIONS

TABLE 10-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH


RH0/A16 bit 0 ST/TTL(1) Input/output port pin or address bit 16 for external memory interface.




RH4/AN12 bit 4 ST Input/output port pin or analog input channel 12.

RH5/AN13 bit 5 ST Input/output port pin or analog input channel 13.

RH6/AN14/P1C(2) bit 6 ST Input/output port pin or analog input channel 14.

RH7/AN15/P1B(2) bit 7 ST Input/output port pin or analog input channel 15.

Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel Slave

Port mode.2: Alternate pin assignment when ECCPMX configuration bit is cleared.



TRISH PORTH Data Direction Control Register 1111 1111 1111 1111

PORTH Read PORTH pin/Write PORTH Data Latch xxxx xxxx uuuu uuuu

LATH Read PORTH Data Latch/Write PORTH Data Latch xxxx xxxx uuuu uuuu


MEMCON(1) EBDIS — WAIT1 WAIT0 — — WM1 WM0 0-00 --00 0-00 --00

Legend: x = unknown, u = unchanged, – = unimplemented. Shaded cells are not used by PORTH.Note 1: This register is held in Reset in Microcontroller mode.


PIC18F6585/8585/6680/8680

10.9 PORTJ, TRISJ and LATJ Registers

PORTJ is an 8-bit wide, bidirectional port. The corre-sponding data direction register is TRISJ. Setting aTRISJ bit (= 1) will make the corresponding PORTJ pinan input (i.e., put the corresponding output driver in ahigh-impedance mode). Clearing a TRISJ bit (= 0) willmake the corresponding PORTJ pin an output (i.e., putthe contents of the output latch on the selected pin).

The Data Latch register (LATJ) is also memorymapped. Read-modify-write operations on the LATJregister read and write the latched output value forPORTJ.

PORTJ is multiplexed with the system bus as theexternal memory interface; I/O port functions are onlyavailable when the system bus is disabled. Whenoperating as the external memory interface, PORTJprovides the control signal to external memory devices.The RJ5 pin is not multiplexed with any system busfunctions.

When enabling peripheral functions, care should betaken in defining TRIS bits for each PORTJ pin. Someperipherals override the TRIS bit to make a pin anoutput, while other peripherals override the TRIS bit tomake a pin an input. The user should refer to thecorresponding peripheral section for the correct TRISbit settings.


EXAMPLE 10-9: INITIALIZING PORTJ

FIGURE 10-25: PORTJ BLOCK DIAGRAM IN I/O MODE

Note: PORTJ is available only on PIC18F8X8Xdevices.


CLRF PORTJ ; Initialize PORTG by; clearing output; data latches

CLRF LATJ ; Alternate method; to clear output; data latches


MOVWF TRISJ ; Set RJ3:RJ0 as inputs; RJ5:RJ4 as output; RJ7:RJ6 as inputs

DataBus

WR LATJ

WR TRISJ

RD PORTJ

Data Latch

TRIS Latch

RD TRISJ


I/O pin(1)

QD

CK

QD

CK

EN

Q D

EN

RD LATJ

orPORTJ



PIC18F6585/8585/6680/8680

FIGURE 10-26: RJ5:RJ0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE

FIGURE 10-27: RJ7:RJ6 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE

External Enable

Control Out

Drive System

System BusControl

Data Bus

WR LATJ

WR TRISJ

RD PORTJ

Data Latch

TRIS Latch

RD TRISJ

I/O pin(1)

QD

CK

EN

Q D

EN

RD LATJ

orPORTJ

0

1

Port

Data


QD

CK

WM = 01

UB/LB Out

Drive System

System BusControl

Data Bus

WR LATJ

WR TRISJ

RD PORTJ

Data Latch

TRIS Latch

RD TRISJ

I/O pin(1)

QD

CK

EN

Q D

EN

RD LATJ

orPORTJ

0

1

Port

Data


QD

CK


PIC18F6585/8585/6680/8680

TABLE 10-17: PORTJ FUNCTIONS

TABLE 10-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ


RJ0/ALE bit 0 ST Input/output port pin or address latch enable control for external memory interface.

RJ1/OE bit 1 ST Input/output port pin or output enable control for external memory interface.

RJ2/WRL bit 2 ST Input/output port pin or write low byte control for external memory interface.

RJ3/WRH bit 3 ST Input/output port pin or write high byte control for external memory interface.

RJ4/BA0 bit 4 ST Input/output port pin or byte address 0 control for external memory interface.

RJ5/CE bit 5 ST Input/output port pin or external memory chip enable.

RJ6/LB bit 6 ST Input/output port pin or lower byte select control for external memory interface.

RJ7/UB bit 7 ST Input/output port pin or upper byte select control for external memory interface.

Legend: ST = Schmitt Trigger input


POR, BOR


PORTJ Read PORTJ pin/Write PORTJ Data Latch xxxx xxxx uuuu uuuu

LATJ LATJ Data Output Register xxxx xxxx uuuu uuuu

TRISJ Data Direction Control Register for PORTJ 1111 1111 1111 1111

Legend: x = unknown, u = unchanged


PIC18F6585/8585/6680/8680

10.10 Parallel Slave Port (PSP)

PORTD also operates as an 8-bit wide Parallel SlavePort, or microprocessor port, when control bitPSPMODE (TRISE<4>) is set. It is asynchronouslyreadable and writable by the external world through RDcontrol input pin, RE0/RD/AD8 and WR control inputpin, RE1/WR/AD9.

The PSP can directly interface to an 8-bit micro-processor data bus. The external microprocessor canread or write the PORTD latch as an 8-bit latch. Settingbit PSPMODE enables port pin RE0/RD/AD8 to be theRD input, RE1/WR/AD9 to be the WR input andRE2/CS/AD10 to be the CS (chip select) input. For thisfunctionality, the corresponding data direction bits ofthe TRISE register (TRISE<2:0>) must be configuredas inputs (set). The A/D port configuration bitsPCFG2:PCFG0 (ADCON1<2:0>) must be set, whichwill configure pins RE2:RE0 as digital I/O.

A write to the PSP occurs when both the CS and WRlines are first detected low. A read from the PSP occurswhen both the CS and RD lines are first detected low.

The PORTE I/O pins become control inputs forthe microprocessor port when bit PSPMODE(PSPCON<4>) is set. In this mode, the user must makesure that the TRISE<2:0> bits are set (pins are config-ured as digital inputs) and the ADCON1 is configuredfor digital I/O. In this mode, the input buffers are TTL.

FIGURE 10-28: PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT)

Note: For PIC18F8X8X devices, the ParallelSlave Port is available only inMicrocontroller mode.

Data Bus

WR LATDRDx

QD

CK

EN

Q D

ENRD PORTD

pin

One bit of PORTD

Set Interrupt Flag

PSPIF (PIR1<7>)

Read

Chip Select

Write

RD

CS

WR

Note: I/O pin has protection diodes to VDD and VSS.

TTL

TTL

TTL

TTL

orPORTD

RD LATD

Data Latch

TRIS Latch

PIC18F6585/8585/6680/8680

REGISTER 10-1: PSPCON REGISTER

FIGURE 10-29: PARALLEL SLAVE PORT WRITE WAVEFORMS

R-0 R-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0

IBF OBF IBOV PSPMODE — — — —

bit 7 bit 0

bit 7 IBF: Input Buffer Full Status bit1 = A data byte has been received and is waiting to be read by the CPU0 = No data byte has been received

bit 6 OBF: Output Buffer Full Status bit

1 = The output buffer still holds a previously written data byte0 = The output buffer has been read

bit 5 IBOV: Input Buffer Overflow Detect bit1 = A write occurred when a previously input data byte has not been read

(must be cleared in software)0 = No overflow occurred

bit 4 PSPMODE: Parallel Slave Port Mode Select bit

1 = Parallel Slave Port mode0 = General Purpose I/O mode


Legend:



Q1 Q2 Q3 Q4

CS

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

WR

RD

IBF

OBF

PSPIF

PORTD<7:0>

PIC18F6585/8585/6680/8680

FIGURE 10-30: PARALLEL SLAVE PORT READ WAVEFORMS

TABLE 10-19: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT

Q1 Q2 Q3 Q4

CS

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

WR

IBF

PSPIF

RD

OBF

PORTD<7:0>


POR, BOR


PORTD Port Data Latch when Written; Port pins when Read xxxx xxxx uuuu uuuu

LATD LATD Data Output bits xxxx xxxx uuuu uuuu

TRISD PORTD Data Direction bits 1111 1111 1111 1111

PORTE RE7/CCP2/AD15

RE6/AD14/P1B

RE5/AD13/P1C

RE4/AD12

RE3/AD11

RE2/CS(1)/AD10

RE1/WR(1)/AD9

RE0/RD(1)/AD8

xxxx xxxx uuuu uuuu

LATE LATE Data Output bits xxxx xxxx uuuu uuuu

TRISE PORTE Data Direction bits 1111 1111 1111 1111


INTCON GIE/GIEH

PEIE/GIEL

TMR0IF INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000

PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.Note 1: Enabled only in Microcontroller mode.

PIC18F6585/8585/6680/8680

11.0 TIMER0 MODULE

The Timer0 module has the following features:

• Software selectable as an 8-bit or 16-bit timer/counter

• Readable and writable• Dedicated 8-bit software programmable prescaler• Clock source selectable to be external or internal

• Interrupt-on-overflow from 0FFh to 00h in 8-bit mode and 0FFFFh to 0000h in 16-bit mode

• Edge select for external clock

Figure 11-1 shows a simplified block diagram of theTimer0 module in 8-bit mode and Figure 11-2 shows asimplified block diagram of the Timer0 module in 16-bitmode.

The T0CON register (Register 11-1) is a readable andwritable register that controls all the aspects of Timer0,including the prescale selection.

REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER

Note: Timer0 is enabled on POR.


TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0

bit 7 bit 0

bit 7 TMR0ON: Timer0 On/Off Control bit

1 = Enables Timer0 0 = Stops Timer0

bit 6 T08BIT: Timer0 8-bit/16-bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter

bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO)

bit 4 T0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin

bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.

bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits 111 = 1:256 prescale value110 = 1:128 prescale value101 = 1:64 prescale value100 = 1:32 prescale value011 = 1:16 prescale value010 = 1:8 prescale value001 = 1:4 prescale value000 = 1:2 prescale value

Legend:




PIC18F6585/8585/6680/8680

FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE

FIGURE 11-2: TIMER0 BLOCK DIAGRAM IN 16-BIT MODE

Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.

RA4/T0CKI pin

T0SE

0

1

0

1

T0CS

FOSC/4

ProgrammablePrescaler

Sync withInternalClocks

TMR0

(2 TCY delay)

Data Bus

8

PSA

T0PS2, T0PS1, T0PS0Set Interrupt

Flag bit TMR0IFon Overflow

3

Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.

T0CKI pin

T0SE

0

1

0

1

T0CS

FOSC/4

ProgrammablePrescaler

Sync withInternalClocks

TMR0L

(2 TCY delay)

Data Bus<7:0>

8

PSAT0PS2, T0PS1, T0PS0

Set InterruptFlag bit TMR0IF

on Overflow

3

TMR0

TMR0H

High Byte

88

8

Read TMR0L

Write TMR0L

PIC18F6585/8585/6680/8680

11.1 Timer0 Operation

Timer0 can operate as a timer or as a counter.

Timer mode is selected by clearing the T0CS bit. InTimer mode, the Timer0 module will increment everyinstruction cycle (without prescaler). If the TMR0 regis-ter is written, the increment is inhibited for the followingtwo instruction cycles. The user can work around thisby writing an adjusted value to the TMR0 register.

Counter mode is selected by setting the T0CS bit. InCounter mode, Timer0 will increment either on everyrising or falling edge of pin RA4/T0CKI. The increment-ing edge is determined by the Timer0 Source EdgeSelect bit (T0SE). Clearing the T0SE bit selects therising edge. Restrictions on the external clock input arediscussed below.

When an external clock input is used for Timer0, it mustmeet certain requirements. The requirements ensurethe external clock can be synchronized with the internalphase clock (TOSC). Also, there is a delay in the actualincrementing of Timer0 after synchronization.

11.2 Prescaler

An 8-bit counter is available as a prescaler for theTimer0 module. The prescaler is not readable orwritable.

The PSA and T0PS2:T0PS0 bits determine theprescaler assignment and prescale ratio.

Clearing bit PSA will assign the prescaler to the Timer0module. When the prescaler is assigned to the Timer0module, prescale values of 1:2, 1:4, ..., 1:256 areselectable.

When assigned to the Timer0 module, all instructionswriting to the TMR0 register (e.g., CLRF TMR0, MOVWFTMR0, BSF TMR0, x, ..., etc.) will clear the prescalercount.

11.2.1 SWITCHING PRESCALER ASSIGNMENT

The prescaler assignment is fully under softwarecontrol (i.e., it can be changed “on-the-fly” duringprogram execution).

11.3 Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 reg-ister overflows from 0FFh to 00h in 8-bit mode, or0FFFFh to 0000h in 16-bit mode. This overflow sets theTMR0IF bit. The interrupt can be masked by clearingthe TMR0IE bit. The TMR0IE bit must be cleared insoftware by the Timer0 module Interrupt ServiceRoutine before re-enabling this interrupt. The TMR0interrupt cannot awaken the processor from Sleepsince the timer is shut-off during Sleep.

11.4 16-Bit Mode Timer Reads and Writes

TMR0H is not the high byte of the timer/counter in16-bit mode, but is actually a buffered version of thehigh byte of Timer0 (refer to Figure 11-2). The high byteof the Timer0 counter/timer is not directly readable norwritable. TMR0H is updated with the contents of thehigh byte of Timer0 during a read of TMR0L. This pro-vides the ability to read all 16 bits of Timer0 withouthaving to verify that the read of the high and low bytewere valid due to a rollover between successive readsof the high and low byte.

A write to the high byte of Timer0 must also take placethrough the TMR0H buffer register. Timer0 high byte isupdated with the contents of TMR0H when a writeoccurs to TMR0L. This allows all 16 bits of Timer0 to beupdated at once.

TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0

Note: Writing to TMR0 when the prescaler isassigned to Timer0 will clear the prescalercount but will not change the prescalerassignment.


POR, BOR


TMR0L Timer0 Module Low Byte Register xxxx xxxx uuuu uuuu

TMR0H Timer0 Module High Byte Register 0000 0000 0000 0000

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u

T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 1111 1111

TRISA — PORTA Data Direction Register -111 1111 -111 1111

Legend: x = unknown, u = unchanged, – = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0.


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NOTES:


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12.0 TIMER1 MODULE

The Timer1 module timer/counter has the followingfeatures:

• 16-bit timer/counter(two 8-bit registers; TMR1H and TMR1L)

• Readable and writable (both registers)

• Internal or external clock select• Interrupt on overflow from 0FFFFh to 0000h• Reset from CCP module special event trigger

Figure 12-1 is a simplified block diagram of the Timer1module.

Register 12-1 details the Timer1 Control register. Thisregister controls the operating mode of the Timer1module and contains the Timer1 Oscillator Enable bit(T1OSCEN). Timer1 can be enabled or disabled bysetting or clearing control bit, TMR1ON (T1CON<0>).

REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit 7 bit 0

bit 7 RD16: 16-bit Read/Write Mode Enable bit1 = Enables register read/write of Timer1 in one 16-bit operation0 = Enables register read/write of Timer1 in two 8-bit operations


bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits

11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value

bit 3 T1OSCEN: Timer1 Oscillator Enable bit

1 = Timer1 oscillator is enabled 0 = Timer1 oscillator is shut-offThe oscillator inverter and feedback resistor are turned off to eliminate power drain.

bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bitWhen TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input

When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1 TMR1CS: Timer1 Clock Source Select bit1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge) 0 = Internal clock (FOSC/4)

bit 0 TMR1ON: Timer1 On bit1 = Enables Timer1 0 = Stops Timer1

Legend:

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Timer1 can operate in one of these modes:

• As a timer

• As a synchronous counter• As an asynchronous counter

The operating mode is determined by the clock selectbit, TMR1CS (T1CON<1>).

When TMR1CS = 0, Timer1 increments every instruc-tion cycle. When TMR1CS = 1, Timer1 increments onevery rising edge of the external clock input or theTimer1 oscillator if enabled.

When the Timer1 oscillator is enabled (T1OSCEN isset), the RC1/T1OSI and RC0/T1OSO/T13CKI pinsbecome inputs. That is, the TRISC<1:0> value isignored and the pins are read as ‘0’.

Timer1 also has an internal “Reset input”. This Resetcan be generated by the CCP module (Section 15.0“Capture/Compare/PWM (CCP) Modules”).

FIGURE 12-1: TIMER1 BLOCK DIAGRAM

FIGURE 12-2: TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE

TMR1H TMR1L

T1SYNC

TMR1CS

T1CKPS1:T1CKPS0Sleep Input

FOSC/4InternalClock

TMR1ONOn/Off

Prescaler1, 2, 4, 8

Synchronize

det

1

0

0

1

SynchronizedClock Input

2

TMR1IFOverflow

TMR1CLR

CCP Special Event Trigger

T1OSCENEnableOscillator(1)

T1OSC

InterruptFlag Bit

Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

T1OSI

T13CKI/T1OSO

T1OSCT1SYNC

TMR1CS

T1CKPS1:T1CKPS0

Sleep Input


TMR1IFOverflowInterrupt

FOSC/4InternalClock

TMR1ONOn/Off

Prescaler1, 2, 4, 8

Synchronize

det

1

0

0

1


2

T13CKI/T1OSO

T1OSI

TMR1

Flag bit


Data Bus<7:0>

8

TMR1H

88

8

Read TMR1L

Write TMR1LCCP Special Event Trigger

Timer 1 TMR1LHigh Byte

CLR

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12.2 Timer1 Oscillator

A crystal oscillator circuit is built-in between pins T1OSI(input) and T1OSO (amplifier output). It is enabled bysetting control bit, T1OSCEN (T1CON<3>). The oscil-lator is a low-power oscillator rated up to 200 kHz. It willcontinue to run during Sleep. It is primarily intended fora 32 kHz crystal. Table 12-1 shows the capacitorselection for the Timer1 oscillator.

The user must provide a software time delay to ensureproper start-up of the Timer1 oscillator.


The TMR1 register pair (TMR1H:TMR1L) incrementsfrom 0000h to 0FFFFh and rolls over to 0000h. TheTMR1 interrupt, if enabled, is generated on overflowwhich is latched in interrupt flag bit, TMR1IF(PIR1<0>). This interrupt can be enabled/disabled bysetting/clearing TMR1 interrupt enable bit, TMR1IE(PIE1<0>).

12.4 Resetting Timer1 Using a CCP Trigger Output

If the CCP module is configured in Compare modeto generate a “special event trigger”(CCP1M3:CCP1M0 = 1011), this signal will resetTimer1 and start an A/D conversion (if the A/D moduleis enabled).

Timer1 must be configured for either Timer or Synchro-nized Counter mode to take advantage of this feature.If Timer1 is running in Asynchronous Counter mode,this Reset operation may not work.

In the event that a write to Timer1 coincides with aspecial event trigger from CCP1, the write will takeprecedence.

In this mode of operation, the CCPR1H:CCPR1L registerpair effectively becomes the period register for Timer1.

12.5 Timer1 16-Bit Read/Write Mode

Timer1 can be configured for 16-bit reads and writes(see Figure 12-2). When the RD16 control bit(T1CON<7>) is set, the address for TMR1H is mappedto a buffer register for the high byte of Timer1. A readfrom TMR1L will load the contents of the high byte ofTimer1 into the Timer1 high byte buffer. This providesthe user with the ability to accurately read all 16 bits ofTimer1 without having to determine whether a read ofthe high byte, followed by a read of the low byte, is validdue to a rollover between reads.

A write to the high byte of Timer1 must also take placethrough the TMR1H Buffer register. Timer1 high byte isupdated with the contents of TMR1H when a writeoccurs to TMR1L. This allows a user to write all 16 bitsto both the high and low bytes of Timer1 at once.

The high byte of Timer1 is not directly readable or writ-able in this mode. All reads and writes must take placethrough the Timer1 High Byte Buffer register. Writes toTMR1H do not clear the Timer1 prescaler. Theprescaler is only cleared on writes to TMR1L.

TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

TABLE 12-1: CAPACITOR SELECTION FOR THE ALTERNATE OSCILLATOR

Osc Type Freq C1 C2

LP 32 kHz TBD(1) TBD(1)

Crystal to be Tested:

32.768 kHz Epson C-001R32.768K-A ± 20 PPM

Note 1: Microchip suggests 33 pF as a startingpoint in validating the oscillator circuit.

2: Higher capacitance increases the stabilityof the oscillator but also increases thestart-up time.

3: Since each resonator/crystal has its owncharacteristics, the user should consultthe resonator/crystal manufacturer forappropriate values of externalcomponents.

4: Capacitor values are for design guidanceonly.

Note: The special event triggers from the CCP1module will not set interrupt flag bitTMR1IF (PIR1<0>).


POR, BOR


INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000

PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111

TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu

Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

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13.0 TIMER2 MODULE

The Timer2 module timer has the following features:

• 8-bit timer (TMR2 register)• 8-bit period register (PR2)• Readable and writable (both registers)

• Software programmable prescaler (1:1, 1:4, 1:16)• Software programmable postscaler (1:1 to 1:16)• Interrupt on TMR2 match of PR2

• SSP module optional use of TMR2 output to generate clock shift

Timer2 has a control register shown in Register 13-1.Timer2 can be shut-off by clearing control bit, TMR2ON(T2CON<2>), to minimize power consumption.Figure 13-1 is a simplified block diagram of the Timer2module. Register 13-1 shows the Timer2 Control regis-ter. The prescaler and postscaler selection of Timer2are controlled by this register.


Timer2 can be used as the PWM time base for thePWM mode of the CCP module. The TMR2 register isreadable and writable and is cleared on any deviceReset. The input clock (FOSC/4) has a prescale optionof 1:1, 1:4 or 1:16, selected by control bits,T2CKPS1:T2CKPS0 (T2CON<1:0>). The match out-put of TMR2 goes through a 4-bit postscaler (whichgives a 1:1 to 1:16 scaling inclusive) to generate aTMR2 interrupt latched in flag bit, TMR2IF (PIR1<1>).

The prescaler and postscaler counters are clearedwhen any of the following occurs:

• a write to the TMR2 register

• a write to the T2CON register• any device Reset (Power-on Reset, MCLR Reset,

Watchdog Timer Reset, or Brown-out Reset)

TMR2 is not cleared when T2CON is written.

REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 7 bit 0


bit 6-3 T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits

0000 = 1:1 postscale 0001 = 1:2 postscale • • • 1111 = 1:16 postscale

bit 2 TMR2ON: Timer2 On bit1 = Timer2 is on 0 = Timer2 is off

bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits

00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16

Legend:

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The Timer2 module has an 8-bit period register, PR2.Timer2 increments from 00h until it matches PR2 andthen resets to 00h on the next increment cycle. PR2 isa readable and writable register. The PR2 register isinitialized to 0FFh upon Reset.

13.3 Output of TMR2

The output of TMR2 (before the postscaler) is fed to thesynchronous serial port module which optionally uses itto generate the shift clock.



Comparator

TMR2Sets Flag

TMR2

Output(1)

Reset

Postscaler

Prescaler

PR2

2

FOSC/4

1:1 to 1:16

1:1, 1:4, 1:16

EQ

4

bit TMR2IF

Note 1: TMR2 register output can be software selected by the SSP module as a baud clock.

T2OUTPS3:T2OUTPS0

T2CKPS1:T2CKPS0


POR, BOR






TMR2 Timer2 Module Register 0000 0000 0000 0000

T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

PR2 Timer2 Period Register 1111 1111 1111 1111



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14.0 TIMER3 MODULE

The Timer3 module timer/counter has the followingfeatures:

• 16-bit timer/counter(two 8-bit registers; TMR3H and TMR3L)

• Readable and writable (both registers)

• Internal or external clock select• Interrupt on overflow from FFFFh to 0000h• Reset from CCP module trigger

Figure 14-1 is a simplified block diagram of the Timer3module.

Register 14-1 shows the Timer3 Control register. Thisregister controls the operating mode of the Timer3module and sets the Enhanced CCP1 and CCP2 clocksource.

Register 12-1 shows the Timer1 Control register. Thisregister controls the operating mode of the Timer1module, as well as containing the Timer1 oscillatorenable bit (T1OSCEN) which can be a clock source forTimer3.

REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON

bit 7 bit 0

bit 7 RD16: 16-bit Read/Write Mode Enable bit1 = Enables register read/write of Timer3 in one 16-bit operation0 = Enables register read/write of Timer3 in two 8-bit operations

bit 6, 3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits1x = Timer3 is the clock source for compare/capture of CCP1 and CCP2 modules01 = Timer3 is the clock source for compare/capture of CCP2 module,

Timer1 is the clock source for compare/capture of CCP1 module00 = Timer1 is the clock source for compare/capture of CCP1 and CCP2 modules

bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits11 = 1:8 prescale value10 = 1:4 prescale value01 = 1:2 prescale value00 = 1:1 prescale value

bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the system clock comes from Timer1/Timer3.)When TMR3CS = 1:1 = Do not synchronize external clock input0 = Synchronize external clock inputWhen TMR3CS = 0:This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.

bit 1 TMR3CS: Timer3 Clock Source Select bit

1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge)

0 = Internal clock (FOSC/4)

bit 0 TMR3ON: Timer3 On bit1 = Enables Timer3 0 = Stops Timer3

Legend:




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Timer3 can operate in one of these modes:

• As a timer

• As a synchronous counter• As an asynchronous counter

The operating mode is determined by the clock selectbit, TMR3CS (T3CON<1>).

When TMR3CS = 0, Timer3 increments every instruc-tion cycle. When TMR3CS = 1, Timer3 increments onevery rising edge of the Timer1 external clock input orthe Timer1 oscillator if enabled.

When the Timer1 oscillator is enabled (T1OSCEN isset), the RC1/T1OSI and RC0/T1OSO/T13CKI pinsbecome inputs. That is, the TRISC<1:0> value isignored and the pins are read as ‘0’.

Timer3 also has an internal “Reset input”. This Resetcan be generated by the CCP module (Section 14.0“Timer3 Module”).


FIGURE 14-2: TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE

TMR3H TMR3L

T1OSC

T3SYNC

TMR3CST3CKPS1:T3CKPS0

Sleep Input


TMR3IFOverflowInterrupt

FOSC/4InternalClock

TMR3ONOn/Off

Prescaler1, 2, 4, 8

Synchronize

det

1

0

0

1


2

T1OSO/

T1OSI

Flag bit

(3)


T13CKI

CLR

CCP Special TriggerT3CCPx

Timer3TMR3L

T1OSCT3SYNC

TMR3CST3CKPS1:T3CKPS0

Sleep Input


FOSC/4InternalClock

TMR3ONOn/Off

Prescaler1, 2, 4, 8

Synchronize

det

1

0

0

1


2

T1OSO/

T1OSI

TMR3

T13CKI

CLR

CCP Special TriggerT3CCPx

To Timer1 Clock Input

Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

High Byte

Data Bus<7:0>

8

TMR3H

88

8

Read TMR3L

Write TMR3L

Set TMR3IF Flag biton Overflow

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14.2 Timer1 Oscillator

The Timer1 oscillator may be used as the clock sourcefor Timer3. The Timer1 oscillator is enabled by settingthe T1OSCEN (T1CON<3>) bit. The oscillator is a low-power oscillator rated up to 200 kHz. See Section 12.0“Timer1 Module” for further details.


The TMR3 register pair (TMR3H:TMR3L) incrementsfrom 0000h to 0FFFFh and rolls over to 0000h. TheTMR3 interrupt, if enabled, is generated on overflowwhich is latched in interrupt flag bit, TMR3IF(PIR2<1>). This interrupt can be enabled/disabled bysetting/clearing TMR3 interrupt enable bit, TMR3IE(PIE2<1>).

14.4 Resetting Timer3 Using a CCP Trigger Output

If the CCP module is configured in Compare modeto generate a “special event trigger”(CCP1M3:CCP1M0 = 1011), this signal will resetTimer3.

Timer3 must be configured for either Timer or Synchro-nized Counter mode to take advantage of this feature.If Timer3 is running in Asynchronous Counter mode,this Reset operation may not work. In the event that awrite to Timer3 coincides with a special event triggerfrom CCP1, the write will take precedence. In this modeof operation, the CCPR1H:CCPR1L register paireffectively becomes the period register for Timer3.


Note: The special event triggers from the CCPmodule will not set interrupt flag bit,TMR3IF (PIR1<0>).


POR, BOR

Value onall other Resets

INTCON GIE/GIEH

PEIE/GIEL

TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000







T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu

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15.0 CAPTURE/COMPARE/PWM (CCP) MODULES

PIC18FXX80/XX85 devices contain a total of two CCPmodules: CCP1 and CCP2. CCP1 is an enhancedversion of the CCP2 module. CCP1 is fully backwardcompatible with the CCP2 module.

The CCP1 module differs from CCP2 in the followingrespect:

• CCP1 contains a special trigger event that may reset Timer1 or the Timer3 register pair

• CCP1 contains “CAN Message Time-Stamp Trigger”• CCP1 contains enhanced PWM output with

programmable dead band and auto-shutdown functionality

Additionally, the CCP2 special event trigger may beused to start an A/D conversion if the A/D module isenabled.

To avoid duplicate information, this section describesbasic CCP module operation that applies to both CCP1and CCP2. Enhanced CCP functionality of theCCP1 module is described in Section 16.0 “EnhancedCapture/Compare/PWM (ECCP) Module”.

The control registers for the CCP1 and CCP2 modulesare shown in Register 15-1 and Register 15-2,respectively. Table 15-2 details the interactions of theCCP and ECCP modules.

REGISTER 15-1: CCP1CON REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0

bit 7 bit 0

bit 7-6 P1M1:P1M0: Enhanced PWM Output Configuration bitsIf CCP1M<3:2> = 00, 01, 10:xx =P1A assigned as capture/compare input; P1B, P1C, P1D assigned as port pinsIf CCP1M<3:2> = 11:00 = Single output; P1A modulated; P1B, P1C, P1D assigned as port pins01 = Full-bridge output forward; P1D modulated; P1A active; P1B, P1C inactive10 = Half-bridge output; P1A, P1B modulated with dead-band control; P1C, P1D assigned as

port pins11 = Full-bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive

bit 5-4 DC1B1:DC1B0: PWM Duty Cycle bit 1 and bit 0Capture mode:Unused.Compare mode:Unused.PWM mode:These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPR1L.

bit 3-0 CCP1M3:CCP1M0: Enhanced CCP Mode Select bits0000 = Capture/Compare/PWM off (resets CCP1 module)0001 = Reserved 0010 = Compare mode, toggle output on match0011 = Reserved0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge1000 = Compare mode, initialize CCP pin low, on compare match force CCP pin high 1001 = Compare mode, initialize CCP pin high, on compare match force CCP pin low 1010 = Compare mode, generate software interrupt only, CCP pin is unaffected1011 = Compare mode, trigger special event, resets TMR1 or TMR3 1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low

Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC18F6585/8585/6680/8680

REGISTER 15-2: CCP2CON REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0

bit 7 bit 0


bit 5-4 DC2B1:DC2B0: PWM Duty Cycle bit 1 and bit 0

Capture mode:Unused.

Compare mode:Unused.

PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPR2L.

bit 3-0 CCP2M3:CCP2M0: CCP2 Mode Select bits0000 = Capture/Compare/PWM off (resets CCP2 module)0001 = Reserved 0010 = Compare mode, toggle output on match0011 = Reserved0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge1000 = Compare mode, initialize CCP pin low, on compare match force CCP pin high 1001 = Compare mode, initialize CCP pin high, on compare match force CCP pin low 1010 = Compare mode, generate software interrupt only, CCP pin is unaffected1011 = Compare mode, trigger special event, resets TMR1 or TMR3 and starts A/D conversion

if A/D module is enabled11xx = PWM mode

Legend:




PIC18F6585/8585/6680/8680

15.1 CCP Module

Both CCP1 and CCP2 are comprised of two 8-bitregisters: CCPRxL (low byte) and CCPRxH (high byte),1 ≤ x ≤ 2. The CCPxCON register controls theoperation of CCPx. All are readable and writable.

Table 15-1 shows the timer resources of the CCPmodule modes.

TABLE 15-1: CCP MODE – TIMER RESOURCE

15.2 Capture Mode

In Capture mode, CCPRxH:CCPRxL captures the16-bit value of the TMR1 or TMR3 register when anevent occurs on pin CCPn. An event is defined as:

• every falling edge• every rising edge

• every 4th rising edge• every 16th rising edge

An event is selected by control bits CCPxM3:CCPxM0(CCPxCON<3:0>). When a capture is made, the inter-rupt request flag bit, CCPxIF (PIR registers), is set. Itmust be cleared in software. If another capture occursbefore the value in register CCPRx is read, the oldcaptured value will be lost.

15.2.1 CCP PIN CONFIGURATION

In Capture mode, the CCPx pin should be configuredas an input by setting the appropriate TRIS bit.

15.2.2 TIMER1/TIMER3 MODE SELECTION

The timer used with each CCP module is selected inthe T3CCP2:T3CCP1 bits of the T3CON register. Thetimers used with the capture feature (either Timer1 orTimer3) must be running in Timer mode or Synchro-nized Counter mode. In Asynchronous Counter mode,the capture operation may not work.

TABLE 15-2: INTERACTION OF CCP MODULES

CCP Mode Timer Resource

CaptureCompare

PWM

Timer1 or Timer3Timer1 or Timer3

Timer2

Note: If the CCPx is configured as an output, awrite to the port can cause a capturecondition.

CCP1Mode

CCP2Mode

Interaction

Capture Capture TMR1 or TMR3 time base. Time base can be different for each CCP.

Capture Compare The compare could be configured for the special event trigger which clears either TMR1 or TMR3 depending upon which time base is used.

Compare Compare The compare(s) could be configured for the special event trigger which clears TMR1 or TMR3 depending upon which time base is used.

PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt).

PWM Capture None.

PWM Compare None.

PIC18F6585/8585/6680/8680

15.2.3 SOFTWARE INTERRUPT

When the Capture mode is changed, a false captureinterrupt may be generated. The user should keep bitCCPxIE (PIE registers) clear to avoid false interruptsand should clear the flag bit, CCPxIF, following anysuch change in operating mode.

15.2.4 CCP PRESCALER

There are four prescaler settings specified by bitsCCPxM3:CCPxM0. Whenever the CCPx module isturned off, or the CCPx module is not in Capture mode,the prescaler counter is cleared. This means that anyReset will clear the prescaler counter.

Switching from one capture prescaler to another maygenerate an interrupt. The prescaler counter will not becleared; therefore, the first capture may be from anon-zero prescaler. Example 15-1 shows therecommended method for switching between captureprescalers. This example also clears the prescalercounter and will not generate the “false” interrupt.

15.2.5 CAN MESSAGE TIME-STAMP

The CAN capture event occurs when a message isreceived in any of the receive buffers. When config-ured, the CAN module provides the trigger to the CCP1module to cause a capture event. This feature isprovided to time-stamp the received CAN messages.

This feature is enabled by setting the CANCAP bit ofthe CAN I/O Control register (CIOCON<4>). Themessage receive signal from the CAN module thentakes the place of the events on RC2/CCP1.

EXAMPLE 15-1: CHANGING BETWEEN CAPTURE PRESCALERS

FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM

CLRF CCP1CON ; Turn CCP module off MOVLW NEW_CAPT_PS ; Load WREG with the

; new prescaler mode ; value and CCP ON

MOVWF CCP1CON ; Load CCP1CON with ; this value

CCPR1H CCPR1L

TMR1H TMR1L

Set Flag bit CCP1IF

TMR3Enable

Q’sCCP1CON<3:0>

CCP1 pin

Prescaler÷ 1, 4, 16

andEdge Detect

TMR3H TMR3L

TMR1Enable

T3CCP2

T3CCP2

CCPR2H CCPR2L

TMR1H TMR1L

Set Flag bit CCP2IF

TMR3Enable

Q’sCCP2CON<3:0>

CCP2 pin

Prescaler÷ 1, 4, 16

andEdge Detect

TMR3H TMR3L

TMR1Enable

T3CCP2T3CCP1

T3CCP2T3CCP1

PIC18F6585/8585/6680/8680

15.3 Compare Mode

In Compare mode, the 16-bit CCPRx register value isconstantly compared against either the TMR1 registerpair value or the TMR3 register pair value. When amatch occurs, the CCPx pin can have one of thefollowing actions:

• Driven high• Driven low

• Toggle output (high-to-low or low-to-high) • Remains unchanged

The action on the pin is based on the value of controlbits, CCPxM3:CCPxM0. At the same time, interruptflag bit, CCPxIF, is set.

When configured to drive the CCP pin, the CCP1 pincannot be changed; CCP1 module controls the pin.

15.3.1 CCP PIN CONFIGURATION

The user must configure the CCPx pin as an output byclearing the appropriate TRIS bit.

By default, the CCP2 pin is multiplexed with RC1.Alternately, it can also be multiplexed with either RB3or RE7. This is done by changing the CCP2MXconfiguration bit.

15.3.2 TIMER1/TIMER3 MODE SELECTION

The timer used with each CCP module is selected inthe T3CCP2:T3CCP1 bits of the T3CON register.Timer1 and/or Timer3 must be running in Timer mode,or Synchronized Counter mode, if the CCP module isusing the compare feature. In Asynchronous Countermode, the compare operation may not work.

15.3.3 SOFTWARE INTERRUPT MODE

When generate software interrupt is chosen, the CCPxpin is not affected. Only a CCP interrupt is generated (ifenabled).

15.3.4 SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is generatedwhich may be used to initiate an action.

The special event trigger output of CCP1 resets eitherthe TMR1 or TMR3 register pair. This allows the CCPR1register to effectively be a 16-bit programmable periodregister for TMR1 or TMR3.

Additionally, the CCP2 special event trigger will start anA/D conversion if the A/D module is enabled.

FIGURE 15-2: COMPARE MODE OPERATION BLOCK DIAGRAM

Note: Clearing the CCPxCON register will forcethe CCPx compare output latch to thedefault low level. This is not the data latch.

Note: The special event trigger from the CCPxmodule will not set the Timer1 or Timer3interrupt flag bits.

CCPR1H CCPR1L

TMR1H TMR1L

ComparatorQ S

R

OutputLogic

Set Flag bit CCP1IF

MatchRC2/CCP1 pin

TRISC<2>CCP1CON<3:0>

Mode SelectOutput Enable

Special Event Trigger will:Reset Timer1 or Timer3, but not set Timer1 or Timer3 interrupt flag bitand set bit GO/DONE (ADCON0<2>)which starts an A/D conversion (CCP2 only)

TMR3H TMR3L

T3CCP2

CCPR2H CCPR2L

Comparator

10

T3CCP2T3CCP1

Q S

R

OutputLogic

Special Event Trigger

Set Flag bit CCP2IF

MatchRC1/CCP2 pin

TRISC<1>CCP2CON<3:0>

Mode SelectOutput Enable

0 1

PIC18F6585/8585/6680/8680

TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3


POR, BOR

Value onall otherResets

INTCON GIE/GIEH

PEIE/GIEL

TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u




TRISD PORTD Data Direction Register 1111 1111 1111 1111




CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu

CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu

CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000






T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu

Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by capture and Timer1.


PIC18F6585/8585/6680/8680

15.4 PWM Mode

In Pulse Width Modulation (PWM) mode, the CCPx pinproduces up to a 10-bit resolution PWM output. ForPWM mode to function properly, the TRIS bit for theCCPx pin must be cleared to make it an output.

Figure 15-3 shows a simplified block diagram of theCCP module in PWM mode.

For a step-by-step procedure on how to set up the CCPmodule for PWM operation, see Section 15.4.3“Setup for PWM Operation”.

FIGURE 15-3: SIMPLIFIED PWM BLOCK DIAGRAM

A PWM output (Figure 15-4) has a time base (period)and a time that the output stays high (duty cycle). Thefrequency of the PWM is the inverse of the period(1/period).

FIGURE 15-4: PWM OUTPUT

15.4.1 PWM PERIOD

The PWM period is specified by writing to the PR2register. The PWM period can be calculated using thefollowing formula.

EQUATION 15-1:

PWM frequency is defined as 1/[PWM period].

When TMR2 is equal to PR2, the following three eventsoccur on the next increment cycle:

• TMR2 is cleared• The CCP1 pin is set (exception: if PWM duty

cycle = 0%, the CCP1 pin will not be set)• The PWM duty cycle is latched from CCPR1L into

CCPR1H

15.4.2 PWM DUTY CYCLE

The PWM duty cycle is specified by writing to theCCPRxL register and to the CCPxCON<5:4> bits. Upto 10-bit resolution is available. The CCPRxL containsthe eight MSbs and the CCPxCON<5:4> contain thetwo LSbs. This 10-bit value is represented byCCPRxL:CCPxCON<5:4>. The following equation isused to calculate the PWM duty cycle in time.

EQUATION 15-2:

CCPRxL and CCPxCON<5:4> can be written to at anytime but the duty cycle value is not latched intoCCPRxH until after a match between PR2 and TMR2occurs (i.e., the period is complete). In PWM mode,CCPRxH is a read-only register.

The CCPRxH register and a 2-bit internal latch areused to double-buffer the PWM duty cycle. Thisdouble-buffering is essential for glitchless PWMoperation.

When the CCPRxH and 2-bit latch match TMR2,concatenated with an internal 2-bit Q clock or 2 bits ofthe TMR2 prescaler, the CCPx pin is cleared.

Note: Clearing the CCPxCON register will forcethe CCPx PWM output latch to the defaultlow level. This is not the port data latch.

CCPRxL (Master)

CCPRxH (Slave)

Comparator

TMR2

PR2

(Note 1)

R Q

S

Duty Cycle Registers CCPxCON<5:4>

Clear Timer,set CCPx pin and latch D.C.

TRIS bit

CCPx

Note 1: 8-bit timer is concatenated with 2-bit internal Q clock or2 bits of the prescaler to create 10-bit time base.

Comparator

Period

Duty Cycle

TMR2 = PR2

TMR2 = Duty Cycle

TMR2 = PR2

Note: The Timer2 postscaler (see Section 13.0“Timer2 Module”) is not used in thedetermination of the PWM frequency. Thepostscaler could be used to have a servoupdate rate at a different frequency thanthe PWM output.

PWM Period = [(PR2) + 1] • 4 • TOSC •(TMR2 Prescale Value)

PWM Duty Cycle = (CCPRxL:CCPxCON<5:4>) • TOSC • (TMR2 Prescale Value)

PIC18F6585/8585/6680/8680

The maximum PWM resolution (bits) for a given PWMfrequency is given by the following equation.

EQUATION 15-3:

15.4.3 SETUP FOR PWM OPERATION

The following steps should be taken when configuringthe CCP module for PWM operation:

1. Set the PWM period by writing to the PR2register.

2. Set the PWM duty cycle by writing to theCCPRxL register and CCPxCON<5:4> bits.

3. Make the CCPx pin an output by clearingcorresponding TRIS bit.

4. Set the TMR2 prescale value and enable Timer2by writing to T2CON.

5. Configure the CCPx module for PWM operation.

TABLE 15-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

TABLE 15-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2

Note: If the PWM duty cycle value is longer thanthe PWM period, the CCP1 pin will not becleared.

FOSC

FPWM--------------- log

2( )log-----------------------------bits=PWM Resolution (max)

PWM Frequency 2.44 kHz 9.76 kHz 39.06 kHz 156.3 kHz 312.5 kHz 416.6 kHz

Timer Prescaler (1, 4, 16) 16 4 1 1 1 1

PR2 Value 0FFh 0FFh 0FFh 3Fh 1Fh 17h

Maximum Resolution (bits) 10 10 10 8 7 5.5


POR, BOR








PR2 Timer2 Module Period Register 1111 1111 1111 1111

T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000






CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.

PIC18F6585/8585/6680/8680

16.0 ENHANCED CAPTURE/COMPARE/PWM (ECCP) MODULE

The CCP1 module is implemented as a standard CCPmodule with enhanced PWM capabilities. These capa-bilities allow for 2 or 4 output channels, user selectablepolarity, dead-band control, and automatic shutdownand restart and are discussed in detail in Section 16.2“Enhanced PWM Mode”.

The control register for CCP1 is shown in Register 16-1.

In addition to the expanded functions of theCCP1CON register, the CCP1 module has twoadditional registers associated with enhanced PWMoperation and auto-shutdown features:

• ECCP1DEL• ECCP1AS

REGISTER 16-1: CCP1CON REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0

bit 7 bit 0

bit 7-6 P1M1:P1M0: Enhanced PWM Output Configuration bits

If CCP1M<3:2> = 00, 01, 10:xx = P1A assigned as capture/compare input; P1B, P1C, P1D assigned as port pins

If CCP1M<3:2> = 11:00 = Single output; P1A modulated, P1B, P1C, P1D assigned as port pins01 = Full-bridge output forward; P1D modulated; P1A active; P1B, P1C inactive10 = Half-bridge output; P1A, P1B modulated with dead-band control; P1C, P1D assigned as

port pins11 = Full-bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive

bit 5-4 DC1B1:DC1B0: PWM Duty Cycle bit 1 and bit 0Capture mode:Unused.Compare mode: Unused.PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPR1L.

bit 3-0 CCP1M3:CCP1M0: Enhanced CCP Mode Select bits0000 =Capture/Compare/PWM off (resets CCP1 module)0001 =Reserved 0010 =Compare mode, toggle output on match0011 =Capture mode, CAN message time-stamp0100 =Capture mode, every falling edge 0101 =Capture mode, every rising edge0110 =Capture mode, every 4th rising edge 0111 =Capture mode, every 16th rising edge1000 =Compare mode, initialize CCP pin low, on compare match, force CCP pin high 1001 =Compare mode, initialize CCP pin high, on compare match, force CCP pin low 1010 =Compare mode, generate software interrupt only, CCP pin is unaffected1011 =Compare mode, trigger special event, resets TMR1 or TMR3 1100 =PWM mode; P1A, P1C active-high; P1B, P1D active-high1101 =PWM mode; P1A, P1C active-high; P1B, P1D active-low1110 =PWM mode; P1A, P1C active-low; P1B, P1D active-high1111 =PWM mode; P1A, P1C active-low; P1B, P1D active-low

Legend:

PIC18F6585/8585/6680/8680

16.1 ECCP Outputs

The enhanced CCP module may have up to fouroutputs depending on the selected operating mode.These outputs, designated P1A through P1D, aremultiplexed with I/O pins RC2, RE6, RE5 and RG4.The pin assignments are summarized in Table 16-1.

To configure I/O pins as PWM outputs, the proper PWMmode must be selected by setting the P1Mx andCCP1Mx bits (CCP1CON<7:6> and <3:0>, respec-tively). The appropriate TRIS direction bits for the portpins must also be set as outputs.

TABLE 16-1: PIN ASSIGNMENTS FOR VARIOUS ECCP MODES

FIGURE 16-1: COMPARE MODE OPERATION BLOCK DIAGRAM

ECCP ModeCCP1CON

ConfigurationRC2 RE6 RE5 RG4

Compatible CCP 00xx11xx CCP1 RE6 RE5 RG4

Dual PWM 10xx11xx P1A P1B(2) RE5 RG4

Quad PWM x1xx11xx P1A P1B(2) P1C(2) P1D

Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP in a given mode.

Note 1: TRIS register values must be configured appropriately.2: On PIC18F8X8X devices, these pins can be alternately multiplexed with RH7 or RH6 by changing the

ECCPMX configuration bit.

CCPR1H CCPR1L

TMR1H TMR1L

ComparatorQ S

R

OutputLogic

Set Flag bit CCP1IF

MatchRB3/CCP1/P1A pin

TRISB<3>

CCP1CON<3:0>Mode Select

Output Enable

Special Event Trigger will:Reset Timer1 or Timer3, but will not set Timer1 or Timer3 interrupt flag bitand set bit GO/DONE (ADCON0<2>) which starts an A/D conversion.

TMR3H TMR3L

T3CCP2 10

PIC18F6585/8585/6680/8680

16.2 Enhanced PWM Mode

The Enhanced PWM mode provides additional PWMoutput options for a broader range of control applica-tions. The module is a backward compatible version ofthe standard CCP module and offers up to four outputs,designated P1A through P1D. Users are also able toselect the polarity of the signal (either active-high oractive-low). The module’s output mode and polarity areconfigured by setting the P1M1:P1M0 andCCP1M3:CCP1M0 bits of the CCP1CON register(CCP1CON<7:6> and CCP1CON<3:0>, respectively).

Figure 16-2 shows a simplified block diagram of PWMoperation. All control registers are double-buffered andare loaded at the beginning of a new PWM cycle (theperiod boundary when Timer2 resets) in order to pre-vent glitches on any of the outputs. The exception is thePWM Delay register, ECCP1DEL, which is loaded ateither the duty cycle boundary or the boundary period(whichever comes first). Because of the buffering, themodule waits until the assigned timer resets instead ofstarting immediately. This means that enhanced PWMwaveforms do not exactly match the standard PWMwaveforms, but are instead offset by one full instructioncycle (4 TOSC).

As before, the user must manually configure theappropriate TRIS bits for output.

16.2.1 PWM PERIOD

The PWM period is specified by writing to the PR2register. The PWM period can be calculated using thefollowing equation.

EQUATION 16-1:

PWM frequency is defined as 1/[PWM period]. WhenTMR2 is equal to PR2, the following three events occuron the next increment cycle:

• TMR2 is cleared

• The CCP1 pin is set (if PWM duty cycle = 0%, the CCP1 pin will not be set)

• The PWM duty cycle is copied from CCPR1L into CCPR1H

16.2.2 PWM DUTY CYCLE

The PWM duty cycle is specified by writing to theCCPR1L register and to the CCP1CON<5:4> bits. Upto 10-bit resolution is available. The CCPR1L containsthe eight MSbs and the CCP1CON<5:4> contains thetwo LSbs. This 10-bit value is represented byCCPR1L:CCP1CON<5:4>. The PWM duty cycle iscalculated by the following equation.

EQUATION 16-2:

CCPR1L and CCP1CON<5:4> can be written to at anytime, but the duty cycle value is not copied intoCCPR1H until a match between PR2 and TMR2 occurs(i.e., the period is complete). In PWM mode, CCPR1His a read-only register.

The CCPR1H register and a 2-bit internal latch areused to double-buffer the PWM duty cycle. Thisdouble-buffering is essential for glitchless PWM opera-tion. When the CCPR1H and 2-bit latch match TMR2,concatenated with an internal 2-bit Q clock or two bitsof the TMR2 prescaler, the CCP1 pin is cleared. Themaximum PWM resolution (bits) for a given PWMfrequency is given by the following equation:

EQUATION 16-3:

16.2.3 PWM OUTPUT CONFIGURATIONS

The P1M1:P1M0 bits in the CCP1CON register allowone of four configurations:

• Single Output• Half-Bridge Output • Full-Bridge Output, Forward mode

• Full-Bridge Output, Reverse mode

The Single Output mode is the standard PWM modediscussed in Section 16.2 “Enhanced PWM Mode”.The Half-Bridge and Full-Bridge Output modes arecovered in detail in the sections that follow.

The general relationship of the outputs in allconfigurations is summarized in Figure 16-3.

Note: The Timer2 postscaler (see Section 13.0“Timer2 Module”) is not used in thedetermination of the PWM frequency. Thepostscaler could be used to have a servoupdate rate at a different frequency thanthe PWM output.

PWM Period = [(PR2) + 1] • 4 • TOSC •(TMR2 Prescale Value) Note: If the PWM duty cycle value is longer than

the PWM period, the CCP1 pin will not becleared.

PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •TOSC • (TMR2 Prescale Value)

PWM Resolution (max) =

FOSC

FPWMlog

log(2)bits

PIC18F6585/8585/6680/8680

TABLE 16-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

FIGURE 16-2: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE

FIGURE 16-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)

PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz

Timer Prescaler (1, 4, 16) 16 4 1 1 1 1

PR2 Value FFh FFh FFh 3Fh 1Fh 17h

Maximum Resolution (bits) 10 10 10 8 7 6.58

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(Note 1)

R Q

S

Duty Cycle RegistersCCP1CON<5:4>

Clear Timer,set CCP1 pin and latch D.C.

Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock or 2 bits of the prescaler to create the 10-bit time base.2: Alternate setting controlled by the ECCPMX bit (PIC18F8X8X devices only).

TRISC<2>

RC2/CCP1/P1A

TRISE<6>

RE6/AD14/P1B or RH7(2)

TRISE<5>

TRISG<4>

RG4/P1D

OutputController

P1M1<1:0>2

CCP1M<3:0>4

CCP1DEL

CCP1/P1A

P1B

P1C

P1D

RE5/AD13/P1C or RH6(2)

0

Period

00

10

01

11

SIGNALPR2 + 1

CCP1CON<7:6>

P1A Modulated

P1A Modulated

P1B Modulated

P1A Active

P1B Inactive

P1C Inactive

P1D Modulated

P1A Inactive

P1B Modulated

P1C Active

P1D Inactive

DutyCycle

(Single Output)

(Half-Bridge)

(Full-Bridge,Forward)

(Full-Bridge,Reverse)

Delay(1) Delay(1)

Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 16.2.6 “Programmable Dead-Band Delay”).

PIC18F6585/8585/6680/8680

FIGURE 16-4: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)

0

Period

00

10

01

11

SIGNALPR2 + 1

CCP1CON<7:6>

P1A Modulated

P1A Modulated

P1B Modulated

P1A Active

P1B Inactive

P1C Inactive

P1D Modulated

P1A Inactive

P1B Modulated

P1C Active

P1D Inactive

DutyCycle

(Single Output)

(Half-Bridge)

(Full-Bridge,Forward)

(Full-Bridge,Reverse)

Delay(1) Delay(1)

Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 16.2.6 “Programmable Dead-Band Delay”).

Relationships:

• Period = 4 * TOSC * (PR2 + 1) * (TMR2 prescale value)• Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 prescale value)• Delay = 4 * TOSC * (PWM1CON<6:0>)

PIC18F6585/8585/6680/8680

16.2.4 HALF-BRIDGE MODE

In the Half-Bridge Output mode, two pins are used asoutputs to drive push-pull loads. The PWM output signalis output on the P1A pin while the complementary PWMoutput signal is output on the P1B pin (Figure 16-5).This mode can be used for half-bridge applications, asshown in Figure 16-6, or for full-bridge applicationswhere four power switches are being modulated withtwo PWM signals.

In Half-Bridge Output mode, the programmable dead-band delay can be used to prevent shoot-throughcurrent in half-bridge power devices. The value of bitsPDC6:PDC0 sets the number of instruction cyclesbefore the output is driven active. If the value is greaterthan the duty cycle, the corresponding output remainsinactive during the entire cycle. See Section 16.2.6“Programmable Dead-Band Delay” for more detailsof the dead-band delay operations.

Since the P1A and P1B outputs are multiplexed withthe PORTC<2> and PORTE<6> data latches, theTRISC<2> and TRISE<6> bits must be cleared toconfigure P1A and P1B as outputs.

FIGURE 16-5: HALF-BRIDGE PWM OUTPUT

FIGURE 16-6: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS

Period

Duty Cycle

td

td

(1)

P1A(2)

P1B(2)

td = Dead-band Delay

Period

(1) (1)

Note 1: At this time, the TMR2 register is equal to thePR2 register.

2: Output signals are shown as active-high.

PIC18FXX80/XX85

P1A

P1B

FETDriver

FETDriver

V+

V-

Load

+V-

+V-

FETDriver

FETDriver

V+

V-

Load

FETDriver

FETDriver

PIC18FXX80/XX85

P1A

P1B

Standard Half-Bridge Circuit (“Push-Pull”)

Half-Bridge Output Driving a Full-Bridge Circuit

PIC18F6585/8585/6680/8680

16.2.5 FULL-BRIDGE MODE

In Full-Bridge Output mode, four pins are used asoutputs; however, only two outputs are active at a time.In the Forward mode, pin P1A is continuously activeand pin P1D is modulated. In the Reverse mode, pinPGC is continuously active and pin P1B is modulated.These are illustrated in Figure 16-7.

P1A, P1B, P1C and P1D outputs are multiplexed withthe PORTC<2>, PORTE<6:5> and PORTG<4> datalatches. The TRISC<2>, TRISC<6:5> and TRISG<4>bits must be cleared to make the P1A, P1B, P1C andP1D pins outputs.

FIGURE 16-7: FULL-BRIDGE PWM OUTPUT

Period

Duty Cycle

P1A(2)

P1B(2)

P1C(2)

P1D(2)

Forward Mode

(1)

Period

Duty Cycle

P1A(2)

P1C(2)

P1D(2)

P1B(2)

Reverse Mode

(1)

(1)(1)

Note 1: At this time, the TMR2 register is equal to the PR2 register.

Note 2: Output signal is shown as active-high.

PIC18F6585/8585/6680/8680

FIGURE 16-8: EXAMPLE OF FULL-BRIDGE APPLICATION

16.2.5.1 Direction Change in Full-Bridge Mode

In the Full-Bridge Output mode, the P1M1 bit in theCCP1CON register allows the user to control theforward/reverse direction. When the applicationfirmware changes this direction control bit, the modulewill assume the new direction on the next PWM cycle.

Just before the end of the current PWM period, the mod-ulated outputs (P1B and P1D) are placed in their inactivestate while the unmodulated outputs (P1A and P1C) areswitched to drive in the opposite direction. This occurs ina time interval of (4 TOSC * (Timer2 Prescale value))before the next PWM period begins. The Timer2prescaler will be either 1, 4 or 16, depending on thevalue of the T2CKPS bit (T2CON<1:0>). During theinterval from the switch of the unmodulated outputs tothe beginning of the next period, the modulated outputs(P1B and P1D) remain inactive. This relationship isshown in Figure 16-9.

Note that in the Full-Bridge Output mode, the CCP1module does not provide any dead-band delay. Ingeneral, since only one output is modulated at all times,dead-band delay is not required. However, there is asituation where a dead-band delay might be required.This situation occurs when both of the followingconditions are true:

1. The direction of the PWM output changes whenthe duty cycle of the output is at or near 100%.

2. The turn off time of the power switch, includingthe power device and driver circuit, is greaterthan the turn on time.

Figure 16-10 shows an example where the PWM direc-tion changes from forward to reverse at a near 100%duty cycle. At time t1, the output P1A and P1D becomeinactive while output P1C becomes active. In thisexample, since the turn off time of the power devices islonger than the turn on time, a shoot-through currentmay flow through power devices QC and QD (seeFigure 16-8) for the duration of ‘t’. The same phenom-enon will occur to power devices QA and QB for PWMdirection change from reverse to forward.

If changing PWM direction at high duty cycle is requiredfor an application, one of the following requirementsmust be met:

1. Reduce PWM for a PWM period beforechanging directions.

2. Use switch drivers that can drive the switches offfaster than they can drive them on.

Other options to prevent shoot-through current mayexist.

PIC18FXX80/XX85

P1A

P1C

FETDriver

FETDriver

V+

V-

Load

FETDriver

FETDriver

P1B

P1D

QA

QB QD

QC

PIC18F6585/8585/6680/8680

FIGURE 16-9: PWM DIRECTION CHANGE

FIGURE 16-10: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE

DC

Period(1)SIGNAL

Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle.2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at inter-

vals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals are inactive at this time.

Period

(Note 2)

P1A (Active-High)

P1B (Active-High)

P1C (Active-High)

P1D (Active-High)

DC

Forward Period Reverse Period

P1A

tON

tOFF

t = tOFF – tON

P1B

P1C

P1D

External Switch D

PotentialShoot-Through

Current

Note 1: All signals are shown as active-high.

2: tON is the turn on delay of power switch QC and its driver.

3: tOFF is the turn off delay of power switch QD and its driver.

External Switch C

t1

DC

DC

PIC18F6585/8585/6680/8680

16.2.6 PROGRAMMABLE DEAD-BAND DELAY

In half-bridge applications where all power switches aremodulated at the PWM frequency at all times, thepower switches normally require more time to turn offthan to turn on. If both the upper and lower powerswitches are switched at the same time (one turned onand the other turned off), both switches may be on fora short period of time until one switch completely turnsoff. During this brief interval, a very high current (shoot-through current) may flow through both powerswitches, shorting the bridge supply. To avoid thispotentially destructive shoot-through current from flow-ing during switching, turning on either of the powerswitches is normally delayed to allow the other switchto completely turn off.

In the Half-Bridge Output mode, a digitally pro-grammable dead-band delay is available to avoidshoot-through current from destroying the bridgepower switches. The delay occurs at the signaltransition from the non-active state to the active state.See Figure 16-5 for an illustration. The lower seven bitsof the ECCP1DEL register (Register 16-2) set thedelay period in terms of microcontroller instructioncycles (TCY or 4 TOSC).

16.2.7 ENHANCED PWM AUTO-SHUTDOWN

When the CCP1 is programmed for any of theenhanced PWM modes, the active output pins may beconfigured for auto-shutdown. Auto-shutdown immedi-ately places the enhanced PWM output pins into adefined shutdown state when a shutdown eventoccurs.

A shutdown event can be caused by either of the twocomparator modules or a low level on the RB0 pin (orany combination of these three sources). The compar-ators may be used to monitor a voltage input propor-tional to a current being monitored in the bridge circuit.If the voltage exceeds a threshold, the comparatorswitches state and triggers a shutdown. Alternatively, alow digital signal on the RB0 pin can also trigger ashutdown. The auto-shutdown feature can be disabledby not selecting any auto-shutdown sources. Theauto-shutdown sources to be used are selected usingthe ECCPAS2:ECCPAS0 bits (bits <6:4> of theECCP1AS register).

When a shutdown occurs, the output pins are asyn-chronously placed in their shutdown states, specifiedby the PSSAC1:PSSAC0 and PSSBD1:PSSBD0 bits(ECCP1AS<3:0>). Each pin pair (P1A/P1C and P1B/P1D) may be set to drive high, drive low, or be tri-stated(not driving). The ECCPASE bit (ECCP1AS<7>) is alsoset to hold the enhanced PWM outputs in theirshutdown states.

The ECCPASE bit is set by hardware when a shutdownevent occurs. If automatic restarts are not enabled, theECCPASE bit is cleared by firmware when the cause ofthe shutdown clears. If automatic restarts are enabled,the ECCPASE bit is automatically cleared when thecause of the auto-shutdown has cleared.

If the ECCPASE bit is set when a PWM period begins,the PWM outputs remain in their shutdown state for thatentire PWM period. When the ECCPASE bit is cleared,the PWM outputs will return to normal operation at thebeginning of the next PWM period.

REGISTER 16-2: ECCP1DEL: ECCP1 DELAY REGISTER

Note: Writing to the ECCPASE bit is disabledwhile a shutdown condition is active.


PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0

bit 7 bit 0

bit 7 PRSEN: PWM Restart Enable bit

1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown eventgoes away; the PWM restarts automatically

0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM

bit 6-0 PDC<6:0>: PWM Delay Count bitsNumber of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active.

Legend:

PIC18F6585/8585/6680/8680

REGISTER 16-3: ECCP1AS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER


ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0

bit 7 bit 0

bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit0 = ECCP outputs are operating 1 = A shutdown event has occurred; ECCP outputs are in shutdown state

bit 6-4 ECCPAS<2:0>: ECCP Auto-Shutdown Source Select bits

000 = Auto-shutdown is disabled001 = Comparator 1 output010 = Comparator 2 output011 = Either Comparator 1 or 2100 = RB0101 = RB0 or Comparator 1110 = RB0 or Comparator 2111 = RB0 or Comparator 1 or Comparator 2

bit 3-2 PSSACn: Pins A and C Shutdown State Control bits00 = Drive pins A and C to ‘0’01 = Drive pins A and C to ‘1’1x = Pins A and C tri-state

bit 1-0 PSSBDn: Pins B and D Shutdown State Control bits

00 = Drive pins B and D to ‘0’01 = Drive pins B and D to ‘1’1x = Pins B and D tri-state

Legend:

PIC18F6585/8585/6680/8680

16.2.7.1 Auto-Shutdown and Automatic Restart

The auto-shutdown feature can be configured to allowautomatic restarts of the module following a shutdownevent. This is enabled by setting the PRSEN bit of theECCP1DEL register (ECCP1DEL<7>).

In Shutdown mode with PRSEN = 1 (Figure 16-11), theECCPASE bit will remain set for as long as the causeof the shutdown continues. When the shutdown condi-tion clears, the ECCPASE bit is cleared. If PRSEN = 0(Figure 16-12), once a shutdown condition occurs, theECCPASE bit will remain set until it is cleared by firm-ware. Once ECCPASE is cleared, the enhanced PWMwill resume at the beginning of the next PWM period.

Independent of the PRSEN bit setting, if the auto-shutdown source is one of the comparators, the shut-down condition is a level. The ECCPASE bit cannot becleared as long as the cause of the shutdown persists.

The Auto-Shutdown mode can be forced by writing a ‘1’to the ECCPASE bit.

16.2.8 START-UP CONSIDERATIONS

When the ECCP module is used in the PWM mode, theapplication hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins.When the microcontroller is released from Reset, all ofthe I/O pins are in the high-impedance state. The exter-nal circuits must keep the power switch devices in theoff state until the microcontroller drives the I/O pins withthe proper signal levels or activates the PWM output(s).

The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allowthe user to choose whether the PWM output signals areactive-high or active-low for each pair of PWM outputpins (P1A/P1C and P1B/P1D). The PWM outputpolarities must be selected before the PWM pins areconfigured as outputs. Changing the polarity configura-tion while the PWM pins are configured as outputs isnot recommended since it may result in damage to theapplication circuits.

The P1A, P1B, P1C and P1D output latches may not bein the proper states when the PWM module is initialized.Enabling the PWM pins for output at the same time asthe ECCP module may cause damage to the applica-tion circuit. The ECCP module must be enabled in theproper Output mode and complete a full PWM cyclebefore configuring the PWM pins as outputs. The com-pletion of a full PWM cycle is indicated by the TMR2IFbit being set as the second PWM period begins.

FIGURE 16-11: PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED)

FIGURE 16-12: PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED)

Note: Writing to the ECCPASE bit is disabledwhile a shutdown condition is active.

Shutdown

PWM

ECCPASE bit

Activity

Event

ShutdownEvent Occurs

ShutdownEvent Clears

PWMResumes

Normal PWM

Start ofPWM Period

PWM Period

Shutdown

PWM

ECCPASE bit

Activity

Event

ShutdownEvent Occurs

ShutdownEvent Clears

PWMResumes

Normal PWM

Start ofPWM Period

ECCPASECleared byFirmware

PWM Period

PIC18F6585/8585/6680/8680

16.2.9 SETUP FOR PWM OPERATION

The following steps should be taken when configuringthe ECCP1 module for PWM operation:

1. Configure the PWM pins, P1A and P1B (andP1C and P1D, if used), as inputs by setting thecorresponding TRISB bits.

2. Set the PWM period by loading the PR2 register.3. Configure the ECCP1 module for the desired

PWM mode and configuration by loading theCCP1CON register with the appropriate values:

• Select one of the available output configurations and direction with the P1M1:P1M0 bits.

• Select the polarities of the PWM output signals with the CCP1M3:CCP1M0 bits.

4. Set the PWM duty cycle by loading the CCPR1Lregister and CCP1CON<5:4> bits.

5. For Half-Bridge Output mode, set the dead-band delay by loading ECCP1DEL<6:0> withthe appropriate value.

6. If auto-shutdown operation is required, load theECCPAS register:• Select the auto-shutdown sources using the

ECCPAS<2:0> bits.• Select the shutdown states of the PWM

output pins using PSSAC1:PSSAC0 and PSSBD1:PSSBD0 bits.

• Set the ECCPASE bit (ECCPAS<7>).• Configure the comparators using the CMCON

register.• Configure the comparator inputs as analog

inputs.

7. If auto-restart operation is required, set thePRSEN bit (ECCP1DEL<7>).

8. Configure and start TMR2:• Clear the TMR2 interrupt flag bit by clearing

the TMR2IF bit (PIR1<1>).• Set the TMR2 prescale value by loading the

T2CKPS bits (T2CON<1:0>).• Enable Timer2 by setting the TMR2ON bit

(T2CON<2>).9. Enable PWM outputs after a new PWM cycle

has started:• Wait until TMR2 overflows (TMR2IF bit is set).

• Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRISB bits.

• Clear the ECCPASE bit (ECCP1AS<7>).

16.2.10 EFFECTS OF A RESET

Both Power-on and subsequent Resets will force allports to Input mode and the CCP registers to theirReset states.

This forces the Enhanced CCP module to reset to astate compatible with the standard CCP module.

TABLE 16-3: REGISTERS ASSOCIATED WITH PWM AND TIMER2


POR, BOR







TRISE PORTE Data Direction Register 1111 1111 1111 1111

TRISG — — — PORTG Data Direction Register ---1 1111 ---1 1111


PR2 Timer2 Module Period Register 1111 1111 1111 1111

T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000




ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 0000 0000

ECCP1DEL PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 uuuu uuuu

Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.

PIC18F6585/8585/6680/8680

NOTES:


PIC18F6585/8585/6680/8680

17.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE

17.1 Master SSP (MSSP) Module Overview

The Master Synchronous Serial Port (MSSP) module isa serial interface, useful for communicating with otherperipheral or microcontroller devices. These peripheraldevices may be serial EEPROMs, shift registers, dis-play drivers, A/D converters, etc. The MSSP modulecan operate in one of two modes:

• Serial Peripheral Interface (SPI)• Inter-Integrated Circuit (I2C)

- Full Master mode- Slave mode (with general address call)

The I2C interface supports the following modes inhardware:

• Master mode• Multi-Master mode• Slave mode

17.2 Control Registers

The MSSP module has three associated registers.These include a status register (SSPSTAT) and twocontrol registers (SSPCON1 and SSPCON2). The useof these registers and their individual configuration bitsdiffer significantly depending on whether the MSSPmodule is operated in SPI or I2C mode.

Additional details are provided under the individualsections.

17.3 SPI Mode

The SPI mode allows 8 bits of data to be synchronouslytransmitted and received simultaneously. All fourmodes of SPI are supported. To accomplishcommunication, typically three pins are used:

• Serial Data Out (SDO) – RC5/SDO

• Serial Data In (SDI) – RC4/SDI/SDA• Serial Clock (SCK) – RC3/SCK/SCL

Additionally, a fourth pin may be used when in a Slavemode of operation:

• Slave Select (SS) – RF7/SS

Figure 17-1 shows the block diagram of the MSSPmodule when operating in SPI mode.

FIGURE 17-1: MSSP BLOCK DIAGRAM (SPI MODE)

( )

Read Write

InternalData Bus

SSPSR Reg

SSPM3:SSPM0

bit0 ShiftClock

SS ControlEnable

EdgeSelect

Clock Select

TMR2 Output

TOSCPrescaler4, 16, 64

2EdgeSelect

2

4

Data to TX/RX in SSPSRTRIS bit

2SMP:CKE

RC5/SDO

SSPBUF Reg

RC4/SDI/SDA

RF7/SS

RC3/SCK/SCL


PIC18F6585/8585/6680/8680

17.3.1 REGISTERS

The MSSP module has four registers for SPI modeoperation. These are:

• MSSP Control Register 1 (SSPCON1)• MSSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer Register (SSPBUF)

• MSSP Shift Register (SSPSR) – Not directly accessible

SSPCON1 and SSPSTAT are the control and statusregisters in SPI mode operation. The SSPCON1 regis-ter is readable and writable. The lower 6 bits of theSSPSTAT are read-only. The upper two bits of theSSPSTAT are read/write.

SSPSR is the shift register used for shifting data in orout. SSPBUF is the buffer register to which data bytesare written to or read from.

In receive operations, SSPSR and SSPBUF togethercreate a double-buffered receiver. When SSPSRreceives a complete byte, it is transferred to SSPBUFand the SSPIF interrupt is set.

During transmission, the SSPBUF is not double-buffered. A write to SSPBUF will write to both SSPBUFand SSPSR.

REGISTER 17-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE)R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0

SMP CKE D/A P S R/W UA BF

bit 7 bit 0

bit 7 SMP: Sample bitSPI Master mode:1 = Input data sampled at end of data output time0 = Input data sampled at middle of data output time

SPI Slave mode:SMP must be cleared when SPI is used in Slave mode.

bit 6 CKE: SPI Clock Edge Select bit When CKP = 0:1 = Data transmitted on rising edge of SCK0 = Data transmitted on falling edge of SCKWhen CKP = 1:1 = Data transmitted on falling edge of SCK0 = Data transmitted on rising edge of SCK

bit 5 D/A: Data/Address bit Used in I2C mode only.

bit 4 P: Stop bit Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.

bit 3 S: Start bitUsed in I2C mode only.

bit 2 R/W: Read/Write bit InformationUsed in I2C mode only.

bit 1 UA: Update Address bitUsed in I2C mode only.

bit 0 BF: Buffer Full Status bit (Receive mode only)1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty

Legend:




PIC18F6585/8585/6680/8680

REGISTER 17-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0

bit 7 bit 0

bit 7 WCOL: Write Collision Detect bit (Transmit mode only)1 = The SSPBUF register is written while it is still transmitting the previous word (must be

cleared in software) 0 = No collision

bit 6 SSPOV: Receive Overflow Indicator bit SPI Slave mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case

of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode.The usermust read the SSPBUF, even if only transmitting data, to avoid setting overflow (must becleared in software).

0 = No overflow

Note: In Master mode, the overflow bit is not set since each new reception (andtransmission) is initiated by writing to the SSPBUF register.

bit 5 SSPEN: Synchronous Serial Port Enable bit 1 = Enables serial port and configures SCK, SDO, SDI, and SS as serial port pins 0 = Disables serial port and configures these pins as I/O port pins

Note: When enabled, these pins must be properly configured as input or output.

bit 4 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level

bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled0011 = SPI Master mode, clock = TMR2 output/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4

Note: Bit combinations not specifically listed here are either reserved or implemented inI2C mode only.

Legend:




PIC18F6585/8585/6680/8680

17.3.2 OPERATION

When initializing the SPI, several options need to bespecified. This is done by programming the appropriatecontrol bits (SSPCON1<5:0> and SSPSTAT<7:6>).These control bits allow the following to be specified:

• Master mode (SCK is the clock output)

• Slave mode (SCK is the clock input)• Clock Polarity (Idle state of SCK)• Data Input Sample Phase (middle or end of data

output time)• Clock Edge (output data on rising/falling edge of

SCK)• Clock Rate (Master mode only)

• Slave Select mode (Slave mode only)

The MSSP consists of a Transmit/Receive Shift regis-ter (SSPSR) and a Buffer register (SSPBUF). TheSSPSR shifts the data in and out of the device, MSbfirst. The SSPBUF holds the data that was written to theSSPSR, until the received data is ready. Once the 8 bitsof data have been received, that byte is moved to theSSPBUF register. Then the Buffer Full detect bit, BF(SSPSTAT<0>) and the interrupt flag bit, SSPIF, areset. This double-buffering of the received data(SSPBUF) allows the next byte to start reception before

reading the data that was just received. Any write to theSSPBUF register during transmission/reception of datawill be ignored and the Write Collision detect bit, WCOL(SSPCON1<7>), will be set. User software must clearthe WCOL bit so that it can be determined if the follow-ing write(s) to the SSPBUF register completedsuccessfully.

When the application software is expecting to receivevalid data, the SSPBUF should be read before the nextbyte of data to transfer is written to the SSPBUF. BufferFull bit, BF (SSPSTAT<0>), indicates when SSPBUFhas been loaded with the received data (transmissionis complete). When the SSPBUF is read, the BF bit iscleared. This data may be irrelevant if the SPI is only atransmitter. Generally, the MSSP interrupt is used todetermine when the transmission/reception has com-pleted. The SSPBUF must be read and/or written. If theinterrupt method is not going to be used, then softwarepolling can be done to ensure that a write collision doesnot occur. Example 17-1 shows the loading of theSSPBUF (SSPSR) for data transmission.

The SSPSR is not directly readable or writable and canonly be accessed by addressing the SSPBUF register.Additionally, the MSSP Status register (SSPSTAT)indicates the various status conditions.

EXAMPLE 17-1: LOADING THE SSPBUF (SSPSR) REGISTER

LOOP BTFSS SSPSTAT, BF ;Has data been received(transmit complete)? BRA LOOP ;No MOVF SSPBUF, W ;WREG reg = contents of SSPBUF

MOVWF RXDATA ;Save in user RAM, if data is meaningful

MOVF TXDATA, W ;W reg = contents of TXDATA MOVWF SSPBUF ;New data to xmit

PIC18F6585/8585/6680/8680

17.3.3 ENABLING SPI I/O

To enable the serial port, SSP Enable bit, SSPEN(SSPCON1<5>), must be set. To reset or reconfigureSPI mode, clear the SSPEN bit, reinitialize theSSPCON registers and then set the SSPEN bit. Thisconfigures the SDI, SDO, SCK and SS pins as serialport pins. For the pins to behave as the serial port func-tion, some must have their data direction bits (in theTRIS register) appropriately programmed as follows:

• SDI is automatically controlled by the SPI module • SDO must have TRISC<5> bit cleared

• SCK (Master mode) must have TRISC<3> bit cleared

• SCK (Slave mode) must have TRISC<3> bit set • SS must have TRISF<7> bit set

Any serial port function that is not desired may beoverridden by programming the corresponding datadirection (TRIS) register to the opposite value.

17.3.4 TYPICAL CONNECTION

Figure 17-2 shows a typical connection between twomicrocontrollers. The master controller (Processor 1)initiates the data transfer by sending the SCK signal.Data is shifted out of both shift registers on their pro-grammed clock edge and latched on the opposite edgeof the clock. Both processors should be programmed tothe same Clock Polarity (CKP), then both controllerswould send and receive data at the same time.Whether the data is meaningful (or dummy data)depends on the application software. This leads tothree scenarios for data transmission:

• Master sends data - Slave sends dummy data• Master sends data - Slave sends data

• Master sends dummy data - Slave sends data

FIGURE 17-2: SPI MASTER/SLAVE CONNECTION

Serial Input Buffer(SSPBUF)

Shift Register(SSPSR)

MSb LSb

SDO

SDI

PROCESSOR 1

SCK

SPI Master SSPM3:SSPM0 = 00xxb

Serial Input Buffer(SSPBUF)

Shift Register(SSPSR)

LSbMSb

SDI

SDO

PROCESSOR 2

SCK

SPI Slave SSPM3:SSPM0 = 010xb

Serial Clock

PIC18F6585/8585/6680/8680

17.3.5 MASTER MODE

The master can initiate the data transfer at any timebecause it controls the SCK. The master determineswhen the slave (Processor 2, Figure 17-2) is tobroadcast data by the software protocol.

In Master mode, the data is transmitted/received assoon as the SSPBUF register is written to. If the SPI isonly going to receive, the SDO output could be dis-abled (programmed as an input). The SSPSR registerwill continue to shift in the signal present on the SDI pinat the programmed clock rate. As each byte isreceived, it will be loaded into the SSPBUF register asif a normal received byte (interrupts and status bitsappropriately set). This could be useful in receiverapplications as a “Line Activity Monitor” mode.

The clock polarity is selected by appropriately program-ming the CKP bit (SSPCON1<4>). This then, wouldgive waveforms for SPI communication, as shown in

Figure 17-3, Figure 17-5 and Figure 17-6, where theMSB is transmitted first. In Master mode, the SPI clockrate (bit rate) is user programmable to be one of thefollowing:

• FOSC/4 (or TCY)• FOSC/16 (or 4 • TCY)

• FOSC/64 (or 16 • TCY)• Timer2 output/2

This allows a maximum data rate (at 40 MHz) of10.00 Mbps.

Figure 17-3 shows the waveforms for Master mode.When the CKE bit is set, the SDO data is valid beforethere is a clock edge on SCK. The change of the inputsample is shown based on the state of the SMP bit. Thetime when the SSPBUF is loaded with the receiveddata is shown.

FIGURE 17-3: SPI MODE WAVEFORM (MASTER MODE)

SCK(CKP = 0

SCK(CKP = 1

SCK(CKP = 0

SCK(CKP = 1

4 ClockModes

InputSample

InputSample

SDI

bit 7 bit 0

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

bit 7 bit 0

SDI

SSPIF

(SMP = 1)

(SMP = 0)

(SMP = 1)

CKE = 1)

CKE = 0)

CKE = 1)

CKE = 0)

(SMP = 0)

Write toSSPBUF

SSPSR toSSPBUF


(CKE = 0)

(CKE = 1)

Next Q4 Cycleafter Q2↓

PIC18F6585/8585/6680/8680

17.3.6 SLAVE MODE

In Slave mode, the data is transmitted and received asthe external clock pulses appear on SCK. When thelast bit is latched, the SSPIF interrupt flag bit is set.

While in Slave mode, the external clock is supplied bythe external clock source on the SCK pin. This externalclock must meet the minimum high and low times asspecified in the electrical specifications.

While in Sleep mode, the slave can transmit/receivedata. When a byte is received, the device will wake-upfrom Sleep.

17.3.7 SLAVE SELECT SYNCHRONIZATION

The SS pin allows a Synchronous Slave mode. The SPImust be in Slave mode with SS pin control enabled(SSPCON1<3:0> = 04h). The pin must not be drivenlow for the SS pin to function as an input. The data latchmust be high. When the SS pin is low, transmission andreception are enabled and the SDO pin is driven. When

the SS pin goes high, the SDO pin is no longer driveneven if in the middle of a transmitted byte and becomesa floating output. External pull-up/pull-down resistorsmay be desirable depending on the application.

When the SPI module resets, the bit counter is forcedto ‘0’. This can be done by either forcing the SS pin toa high level or clearing the SSPEN bit.

To emulate two-wire communication, the SDO pin canbe connected to the SDI pin. When the SPI needs tooperate as a receiver, the SDO pin can be configuredas an input. This disables transmissions from the SDO.The SDI can always be left as an input (SDI function)since it cannot create a bus conflict.

FIGURE 17-4: SLAVE SYNCHRONIZATION WAVEFORM

Note 1: When the SPI is in Slave mode with SS pincontrol enabled (SSPCON<3:0> = 0100),the SPI module will reset if the SS pin is setto VDD.

2: If the SPI is used in Slave mode with CKEset, then the SS pin control must beenabled.

InputSample

SDI

bit 7

SDO bit 7 bit 6 bit 7

SSPIFInterrupt

(SMP = 0)

CKE = 0)

(SMP = 0)

Write toSSPBUF

SSPSR toSSPBUF

Flag

bit 0

bit 7

bit 0


SCK(CKP = 1

SCK(CKP = 0CKE = 0)

SS

PIC18F6585/8585/6680/8680

FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SCK(CKP = 1

SCK(CKP = 0

InputSample

SDI

bit 7 bit 0


SSPIFInterrupt

(SMP = 0)

CKE = 0)

CKE = 0)

(SMP = 0)

Write toSSPBUF

SSPSR toSSPBUF

SS

Flag

Optional


SCK(CKP = 1

SCK(CKP = 0

InputSample

SDI

bit 7 bit 0


SSPIFInterrupt

(SMP = 0)

CKE = 1)

CKE = 1)

(SMP = 0)

Write toSSPBUF

SSPSR toSSPBUF

SS

Flag

Not Optional



PIC18F6585/8585/6680/8680

17.3.8 SLEEP OPERATION

In Master mode, all module clocks are halted and thetransmission/reception will remain in that state until thedevice wakes from Sleep. After the device returns tonormal mode, the module will continue totransmit/receive data.

In Slave mode, the SPI Transmit/Receive Shift registeroperates asynchronously to the device. This allows thedevice to be placed in Sleep mode and data to beshifted into the SPI Transmit/Receive Shift register.When all 8 bits have been received, the MSSP interruptflag bit will be set and if enabled, will wake the devicefrom Sleep.

17.3.9 EFFECTS OF A RESET

A Reset disables the MSSP module and terminates thecurrent transfer.

17.3.10 BUS MODE COMPATIBILITY

Table 17-1 shows the compatibility between thestandard SPI modes and the states of the CKP andCKE control bits.

TABLE 17-1: SPI BUS MODES

There is also a SMP bit which controls when the data issampled.

TABLE 17-2: REGISTERS ASSOCIATED WITH SPI OPERATION

Standard SPI Mode Terminology

Control Bits State

CKP CKE

0, 0 0 1

0, 1 0 0

1, 0 1 1

1, 1 1 0


POR, BOR







TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 uuuu uuuu

SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu

SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.


PIC18F6585/8585/6680/8680

17.4 I2C Mode

The MSSP module in I2C mode fully implements allmaster and slave functions (including general call sup-port) and provides interrupts on Start and Stop bits inhardware to determine a free bus (multi-master func-tion). The MSSP module implements the standardmode specifications, as well as 7-bit and 10-bitaddressing.

Two pins are used for data transfer:

• Serial clock (SCL) – RC3/SCK/SCL

• Serial data (SDA) – RC4/SDI/SDA

The user must configure these pins as inputs or outputsthrough the TRISC<4:3> bits.

FIGURE 17-7: MSSP BLOCK DIAGRAM (I2C MODE)

17.4.1 REGISTERS

The MSSP module has six registers for I2C operation.These are:

• MSSP Control Register 1 (SSPCON1)• MSSP Control Register 2 (SSPCON2)

• MSSP Status Register (SSPSTAT)• Serial Receive/Transmit Buffer (SSPBUF)• MSSP Shift Register (SSPSR) – Not directly

accessible• MSSP Address Register (SSPADD)

SSPCON, SSPCON2 and SSPSTAT are the controland status registers in I2C mode operation. TheSSPCON and SSPCON2 registers are readable andwritable. The lower six bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT areread/write.

SSPSR is the shift register used for shifting data in orout. SSPBUF is the buffer register to which data bytesare written to or read from.

SSPADD register holds the slave device address whenthe SSP is configured in I2C Slave mode. When theSSP is configured in Master mode, the lower seven bitsof SSPADD act as the Baud Rate Generator reloadvalue.

In receive operations, SSPSR and SSPBUF togethercreate a double-buffered receiver. When SSPSRreceives a complete byte, it is transferred to SSPBUFand the SSPIF interrupt is set.

During transmission, the SSPBUF is not double-buffered. A write to SSPBUF will write to both SSPBUFand SSPSR.

Read Write

SSPSR Reg

Match Detect

SSPADD Reg

Start and Stop bit Detect

SSPBUF Reg

InternalData Bus

Addr Match

Set, ResetS, P bits

(SSPSTAT Reg)

RC3/SCK/

RC4/

ShiftClock

MSbSDI/

LSb

SDA

SCL

PIC18F6585/8585/6680/8680

REGISTER 17-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE)R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0

SMP CKE D/A P S R/W UA BF

bit 7 bit 0

bit 7 SMP: Slew Rate Control bit

In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz)

bit 6 CKE: SMBus Select bit

In Master or Slave mode:1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs

bit 5 D/A: Data/Address bit In Master mode:Reserved.In Slave mode:1 = Indicates that the last byte received or transmitted was data0 = Indicates that the last byte received or transmitted was address

bit 4 P: Stop bit1 = Indicates that a Stop bit has been detected last0 = Stop bit was not detected last

Note: This bit is cleared on Reset and when SSPEN is cleared.

bit 3 S: Start bit1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last

Note: This bit is cleared on Reset and when SSPEN is cleared.

bit 2 R/W: Read/Write bit Information (I2C mode only)In Slave mode:1 = Read0 = Write

Note: This bit holds the R/W bit information following the last address match. This bit isonly valid from the address match to the next Start bit, Stop bit or not ACK bit.

In Master mode:1 = Transmit is in progress0 = Transmit is not in progress

Note: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP isin Idle mode.

bit 1 UA: Update Address bit (10-bit Slave mode only)1 = Indicates that the user needs to update the address in the SSPADD register0 = Address does not need to be updated

bit 0 BF: Buffer Full Status bitIn Transmit mode:1 = Receive complete, SSPBUF is full0 = Receive not complete, SSPBUF is emptyIn Receive mode:1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty

Legend:




PIC18F6585/8585/6680/8680

REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C MODE)R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0

bit 7 bit 0

bit 7 WCOL: Write Collision Detect bitIn Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for

a transmission to be started (must be cleared in software)0 = No collisionIn Slave Transmit mode:1 = The SSPBUF register is written while it is still transmitting the previous word (must be

cleared in software)0 = No collision

In Receive mode (Master or Slave modes):This is a “don’t care” bit.

bit 6 SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte (must be

cleared in software)0 = No overflow

In Transmit mode: This is a “don’t care” bit in Transmit mode.

bit 5 SSPEN: Synchronous Serial Port Enable bit 1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins0 = Disables serial port and configures these pins as I/O port pins

Note: When enabled, the SDA and SCL pins must be properly configured as input oroutput.

bit 4 CKP: SCK Release Control bit In Slave mode: 1 = Release clock 0 = Holds clock low (clock stretch), used to ensure data setup timeIn Master mode: Unused in this mode.

bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled1011 = I2C Firmware Controlled Master mode (slave Idle)1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1)) 0111 = I2C Slave mode, 10-bit address0110 = I2C Slave mode, 7-bit address

Note: Bit combinations not specifically listed here are either reserved or implemented inSPI mode only.

Legend:




PIC18F6585/8585/6680/8680

REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN

bit 7 bit 0

bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled

bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only)

1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave

bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only) 1 = Not Acknowledge 0 = Acknowledge

Note: Value that will be transmitted when the user initiates an Acknowledge sequence atthe end of a receive.

bit 4 ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only) 1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.

Automatically cleared by hardware. 0 = Acknowledge sequence Idle

bit 3 RCEN: Receive Enable bit (Master Mode only)

1 = Enables Receive mode for I2C 0 = Receive Idle

bit 2 PEN: Stop Condition Enable bit (Master mode only) 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle

bit 1 RSEN: Repeated Start Condition Enabled bit (Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle

bit 0 SEN: Start Condition Enabled/Stretch Enabled bit

In Master mode:1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.0 = Start condition IdleIn Slave mode:1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled

Legend:



Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode,this bit may not be set (no spooling) and the SSPBUF may not be written (or writesto the SSPBUF are disabled).


PIC18F6585/8585/6680/8680

17.4.2 OPERATION

The MSSP module functions are enabled by settingMSSP Enable bit, SSPEN (SSPCON<5>).

The SSPCON1 register allows control of the I2C oper-ation. Four mode selection bits (SSPCON<3:0>) allowone of the following I2C modes to be selected:

• I2C Master mode, clock = OSC/4 (SSPADD + 1)

• I2C Slave mode (7-bit address)• I2C Slave mode (10-bit address)• I2C Slave mode (7-bit address) with Start and

Stop bit interrupts enabled• I2C Slave mode (10-bit address) with Start and

Stop bit interrupts enabled• I2C Firmware Controlled Master mode, slave is

Idle

Selection of any I2C mode with the SSPEN bit set,forces the SCL and SDA pins to be open-drain, pro-vided these pins are programmed to inputs by settingthe appropriate TRISC bits. To ensure proper operationof the module, pull-up resistors must be providedexternally to the SCL and SDA pins.

17.4.3 SLAVE MODE

In Slave mode, the SCL and SDA pins must be config-ured as inputs (TRISC<4:3> set). The MSSP modulewill override the input state with the output data whenrequired (slave-transmitter).

The I2C Slave mode hardware will always generate aninterrupt on an address match. Through the modeselect bits, the user can also choose to interrupt onStart and Stop bits

When an address is matched or the data transfer afteran address match is received, the hardware automati-cally will generate the Acknowledge (ACK) pulse andload the SSPBUF register with the received valuecurrently in the SSPSR register.

Any combination of the following conditions will causethe MSSP module not to give this ACK pulse:

• The buffer full bit BF (SSPSTAT<0>) was set before the transfer was received.

• The overflow bit SSPOV (SSPCON<6>) was set before the transfer was received.

In this case, the SSPSR register value is not loadedinto the SSPBUF but bit SSPIF (PIR1<3>) is set. TheBF bit is cleared by reading the SSPBUF register whilebit SSPOV is cleared through software.

The SCL clock input must have a minimum high andlow for proper operation. The high and low times of theI2C specification, as well as the requirement of theMSSP module, are shown in timing parameter #100and parameter #101.

17.4.3.1 Addressing

Once the MSSP module has been enabled, it waits fora Start condition to occur. Following the Start condition,the 8 bits are shifted into the SSPSR register. All incom-ing bits are sampled with the rising edge of the clock(SCL) line. The value of register SSPSR<7:1> is com-pared to the value of the SSPADD register. Theaddress is compared on the falling edge of the eighthclock (SCL) pulse. If the addresses match and the BFand SSPOV bits are clear, the following events occur:

1. The SSPSR register value is loaded into theSSPBUF register.

2. The buffer full bit BF is set.3. An ACK pulse is generated.4. MSSP interrupt flag bit, SSPIF (PIR1<3>), is set

(interrupt is generated, if enabled) on the fallingedge of the ninth SCL pulse.

In 10-bit Address mode, two address bytes need to bereceived by the slave. The five Most Significant bits(MSbs) of the first address byte specify if this is a 10-bitaddress. Bit R/W (SSPSTAT<2>) must specify a writeso the slave device will receive the second addressbyte. For a 10-bit address, the first byte would equal‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the twoMSbs of the address. The sequence of events for10-bit address is as follows, with steps 7 through 9 forthe slave-transmitter:

1. Receive first (high) byte of address (bits SSPIF,BF and bit UA (SSPSTAT<1>) are set).

2. Update the SSPADD register with second (low)byte of address (clears bit UA and releases theSCL line).

3. Read the SSPBUF register (clears bit BF) andclear flag bit SSPIF.

4. Receive second (low) byte of address (bitsSSPIF, BF, and UA are set).

5. Update the SSPADD register with the first (high)byte of address. If match releases SCL line, thiswill clear bit UA.

6. Read the SSPBUF register (clears bit BF) andclear flag bit SSPIF.

7. Receive Repeated Start condition.8. Receive first (high) byte of address (bits SSPIF

and BF are set).9. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

PIC18F6585/8585/6680/8680

17.4.3.2 Reception

When the R/W bit of the address byte is clear and anaddress match occurs, the R/W bit of the SSPSTATregister is cleared. The received address is loaded intothe SSPBUF register and the SDA line is held low(ACK).

When the address byte overflow condition exists, thenthe no Acknowledge (ACK) pulse is given. An overflowcondition is defined as either bit BF (SSPSTAT<0>) isset or bit SSPOV (SSPCON1<6>) is set.

An MSSP interrupt is generated for each data transferbyte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-ware. The SSPSTAT register is used to determine thestatus of the byte.

If SEN is enabled (SSPCON2<0> = 1), RC3/SCK/SCLwill be held low (clock stretch) following each datatransfer. The clock must be released by setting bitCKP (SSPCON<4>). See Section 17.4.4 “ClockStretching” for more detail.

17.4.3.3 Transmission

When the R/W bit of the incoming address byte is setand an address match occurs, the R/W bit of theSSPSTAT register is set. The received address isloaded into the SSPBUF register. The ACK pulse willbe sent on the ninth bit and pin RC3/SCK/SCL is heldlow, regardless of SEN (see Section 17.4.4 “ClockStretching” for more detail). By stretching the clock,the master will be unable to assert another clock pulseuntil the slave is done preparing the transmit data. Thetransmit data must be loaded into the SSPBUF registerwhich also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP(SSPCON1<4>). The eight data bits are shifted out onthe falling edge of the SCL input. This ensures that theSDA signal is valid during the SCL high time(Figure 17-9).

The ACK pulse from the master-receiver is latched onthe rising edge of the ninth SCL input pulse. If the SDAline is high (not ACK), then the data transfer is com-plete. In this case, when the ACK is latched by theslave, the slave logic is reset (resets SSPSTAT regis-ter) and the slave monitors for another occurrence ofthe Start bit. If the SDA line was low (ACK), the nexttransmit data must be loaded into the SSPBUF register.Again, pin RC3/SCK/SCL must be enabled by settingbit CKP.

An MSSP interrupt is generated for each data transferbyte. The SSPIF bit must be cleared in software andthe SSPSTAT register is used to determine the statusof the byte. The SSPIF bit is set on the falling edge ofthe ninth clock pulse.

PIC18F6585/8585/6680/8680

FIGURE 17-8: I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)

SD

A

SC

L

SS

PIF

BF

(S

SP

STA

T<0

>)

SS

PO

V (

SS

PC

ON

<6>

)

S1

23

45

67

89

12

34

56

78

91

23

45

78

9P

A7

A6

A5

A4

A3

A2

A1

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D1

D0

AC

KR

ecei

ving

Dat

aA

CK

Rec

eivi

ng D

ata

R/W

= 0 A

CK

Rec

eivi

ng A

ddre

ss

Cle

ared

in s

oftw

are

SS

PB

UF

is r

ead

Bus

mas

ter

term

inat

estr

ansf

er

SS

PO

V is

set

beca

use

SS

PB

UF

isst

ill fu

ll. A

CK

is n

ot s

ent.

D2 6

(PIR

1<3>

)

CK

P(C

KP

doe

s no

t res

et to

‘0’ w

hen

SE

N =

0)

PIC18F6585/8585/6680/8680

FIGURE 17-9: I2C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)

SD

A

SC

L

SS

PIF

(P

IR1<

3>)

BF

(S

SP

STA

T<

0>)

A6

A5

A4

A3

A2

A1

D6

D5

D4

D3

D2

D1

D0

12

34

56

78

23

45

67

89

SS

PB

UF

is w

ritte

n in

sof

twar

e

Cle

ared

in s

oftw

are

Fro

m S

SP

IF IS

R

Dat

a in

sa

mpl

ed

S

AC

KTr

ansm

ittin

g D

ata

R/W

= 1

AC

K

Rec

eivi

ng A

ddre

ss

A7

D7

91

D6

D5

D4

D3

D2

D1

D0

23

45

67

89

SS

PB

UF

is w

ritte

n in

sof

twar

e

Cle

ared

in s

oftw

are

Fro

m S

SP

IF IS

R

Tran

smitt

ing

Dat

a

D7 1

CK

P

P

AC

K

CK

P is

set

in s

oftw

are

CK

P is

set

in s

oftw

are

SC

L he

ld lo

ww

hile

CP

Ure

spon

ds to

SS

PIF

PIC18F6585/8585/6680/8680


SD

A

SC

L

SS

PIF

BF

(S

SP

STA

T<

0>)

S1

23

45

67

89

12

34

56

78

91

23

45

78

9P

11

11

0A

9A

8A

7A

6A

5A

4A

3A

2A

1A

0D

7D

6D

5D

4D

3D

1D

0

Rec

eive

Dat

a B

yte

AC

K

R/W

= 0 AC

K

Rec

eive

Firs

t Byt

e of

Add

ress

Cle

ared

in s

oftw

are

D2 6

(PIR

1<3>

)

Cle

ared

in s

oftw

are

Rec

eive

Sec

ond

Byt

e of

Add

ress

Cle

ared

by

hard

war

ew

hen

SS

PA

DD

is u

pdat

edw

ith lo

w b

yte

of a

ddre

ss

UA

(S

SP

STA

T<

1>)

Clo

ck is

hel

d lo

w u

ntil

upda

te o

f SS

PA

DD

has

ta

ken

plac

e

UA

is s

et in

dica

ting

that

the

SS

PA

DD

nee

ds to

be

upda

ted

UA

is s

et in

dica

ting

that

SS

PA

DD

nee

ds to

be

upda

ted

Cle

ared

by

hard

war

e w

hen

SS

PA

DD

is u

pdat

ed w

ith h

igh

byte

of a

ddre

ss

SS

PB

UF

is w

ritte

n w

ithco

nten

ts o

f SS

PS

RD

umm

y re

ad o

f SS

PB

UF

to c

lear

BF

flag

AC

K

CK

P

12

34

57

89

D7

D6

D5

D4

D3

D1

D0

Rec

eive

Dat

a B

yte

Bus

mas

ter

term

inat

estr

ansf

er

D2 6

AC

K

Cle

ared

in s

oftw

are

Cle

ared

in s

oftw

are

SS

PO

V (

SS

PC

ON

<6>

)

SS

PO

V is

set

beca

use

SS

PB

UF

isst

ill fu

ll. A

CK

is n

ot s

ent.

(CK

P d

oes

not r

eset

to ‘0

’ whe

n S

EN

= 0

)

Clo

ck is

hel

d lo

w u

ntil

upda

te o

f SS

PA

DD

has

ta

ken

plac

e

PIC18F6585/8585/6680/8680

FIGURE 17-11: I2C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)

SD

A

SC

L

SS

PIF

BF

(S

SP

STA

T<

0>)

S1

23

45

67

89

12

34

56

78

91

23

45

78

9P

11

11

0A

9A

8A

7A

6A

5A

4A

3A

2A

1A

01

11

10

A8

R/W

= 1 A

CK

AC

K

R/W

= 0

AC

K

Rec

eive

Firs

t Byt

e of

Add

ress

Cle

ared

in s

oftw

are

Bus

mas

ter

term

inat

estr

ansf

er

A9 6

(PIR

1<3>

)

Rec

eive

Sec

ond

Byt

e of

Add

ress

Cle

ared

by

hard

war

e w

hen

SS

PA

DD

is u

pdat

ed w

ith lo

wby

te o

f add

ress

UA

(S

SP

STA

T<

1>)

Clo

ck is

hel

d lo

w u

ntil

upda

te o

f SS

PA

DD

has

ta

ken

plac

e

UA

is s

et in

dica

ting

that

the

SS

PA

DD

nee

ds to

be

upda

ted

UA

is s

et in

dica

ting

that

SS

PA

DD

nee

ds to

be

upda

ted

Cle

ared

by

hard

war

e w

hen

SS

PA

DD

is u

pdat

ed w

ith h

igh

byte

of a

ddre

ss.

SS

PB

UF

is w

ritte

n w

ithco

nten

ts o

f SS

PS

RD

umm

y re

ad o

f SS

PB

UF

to c

lear

BF

flag

Rec

eive

Firs

t Byt

e of

Add

ress

12

34

57

89

D7

D6

D5

D4

D3

D1

AC

K

D2

6

Tra

nsm

ittin

g D

ata

Byt

e

D0

Dum

my

read

of S

SP

BU

Fto

cle

ar B

F fl

ag

Sr

Cle

ared

in s

oftw

are

Writ

e of

SS

PB

UF

initi

ates

tran

smit

Cle

ared

in s

oftw

are

Com

plet

ion

of

clea

rs B

F fl

ag

CK

P (

SS

PC

ON

<4>

)

CK

P is

set

in s

oftw

are

CK

P is

aut

omat

ical

ly c

lear

ed in

har

dwar

e, h

oldi

ng S

CL

low

Clo

ck is

hel

d lo

w u

ntil

upda

te o

f SS

PA

DD

has

ta

ken

plac

e

data

tran

smis

sion

Clo

ck is

hel

d lo

w u

ntil

CK

P is

set

to ‘1

’

BF

flag

is c

lear

third

add

ress

seq

uenc

eat

the

end

of th

e

PIC18F6585/8585/6680/8680

17.4.4 CLOCK STRETCHING

Both 7- and 10-bit Slave modes implement automaticclock stretching during a transmit sequence.

The SEN bit (SSPCON2<0>) allows clock stretching tobe enabled during receives. Setting SEN will cause theSCL pin to be held low at the end of each data receivesequence.

17.4.4.1 Clock Stretching for 7-bit Slave Receive Mode (SEN = 1)

In 7-bit Slave Receive mode, on the falling edge of theninth clock at the end of the ACK sequence if the BF bitis set, the CKP bit in the SSPCON1 register is automat-ically cleared, forcing the SCL output to be held low.The CKP being cleared to ‘0’ will assert the SCL linelow. The CKP bit must be set in the user’s ISR beforereception is allowed to continue. By holding the SCLline low, the user has time to service the ISR and readthe contents of the SSPBUF before the master devicecan initiate another receive sequence. This will preventbuffer overruns from occurring (see Figure 17-13).

17.4.4.2 Clock Stretching for 10-bit Slave Receive Mode (SEN = 1)

In 10-bit Slave Receive mode, during the addresssequence, clock stretching automatically takes placebut CKP is not cleared. During this time, if the UA bit isset after the ninth clock, clock stretching is initiated.The UA bit is set after receiving the upper byte of the10-bit address and following the receive of the secondbyte of the 10-bit address with the R/W bit cleared to‘0’. The release of the clock line occurs upon updatingSSPADD. Clock stretching will occur on each datareceive sequence as described in 7-bit mode.

17.4.4.3 Clock Stretching for 7-bit Slave Transmit Mode

7-bit Slave Transmit mode implements clock stretchingby clearing the CKP bit after the falling edge of the ninthclock, if the BF bit is clear. This occurs regardless of thestate of the SEN bit.

The user’s ISR must set the CKP bit before transmis-sion is allowed to continue. By holding the SCL line low,the user has time to service the ISR and load the con-tents of the SSPBUF before the master device caninitiate another transmit sequence (see Figure 17-9).

17.4.4.4 Clock Stretching for 10-bit Slave Transmit Mode

In 10-bit Slave Transmit mode, clock stretching iscontrolled during the first two address sequences bythe state of the UA bit, just as it is in 10-bit SlaveReceive mode. The first two addresses are followed bya third address sequence which contains the high orderbits of the 10-bit address and the R/W bit set to ‘1’. Afterthe third address sequence is performed, the UA bit isnot set, the module is now configured in Transmitmode, and clock stretching is controlled by the BF flagas in 7-bit Slave Transmit mode (see Figure 17-11).

Note 1: If the user reads the contents of theSSPBUF before the falling edge of theninth clock, thus clearing the BF bit, theCKP bit will not be cleared and clockstretching will not occur.

2: The CKP bit can be set in softwareregardless of the state of the BF bit. Theuser should be careful to clear the BF bitin the ISR before the next receivesequence in order to prevent an overflowcondition.

Note: If the user polls the UA bit and clears it byupdating the SSPADD register before thefalling edge of the ninth clock occurs and ifthe user hasn’t cleared the BF bit by read-ing the SSPBUF register before that time,then the CKP bit will still NOT be assertedlow. Clock stretching on the basis of thestate of the BF bit only occurs during adata sequence, not an address sequence.

Note 1: If the user loads the contents of SSPBUF,setting the BF bit before the falling edge ofthe ninth clock, the CKP bit will not becleared and clock stretching will not occur.

2: The CKP bit can be set in softwareregardless of the state of the BF bit.

PIC18F6585/8585/6680/8680

17.4.4.5 Clock Synchronization and the CKP bit

When the CKP bit is cleared, the SCL output is forcedto ‘0’. However, setting the CKP bit will not assert theSCL output low until the SCL output is already sampledlow. Therefore, the CKP bit will not assert the SCL line

until an external I2C master device has alreadyasserted the SCL line. The SCL output will remain lowuntil the CKP bit is set and all other devices on the I2Cbus have deasserted SCL. This ensures that a write tothe CKP bit will not violate the minimum high timerequirement for SCL (see Figure 17-12).

FIGURE 17-12: CLOCK SYNCHRONIZATION TIMING

SDA

SCL

DX-1DX

WR

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SSPCON

CKP

Master devicedeasserts clock

Master deviceasserts clock


PIC18F6585/8585/6680/8680


SD

A

SC

L

SS

PIF

BF

(S

SP

STA

T<

0>)

SS

PO

V (

SS

PC

ON

<6>

)

S1

23

45

67

89

12

34

56

78

91

23

45

78

9P

A7

A6

A5

A4

A3

A2

A1

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D1

D0

AC

KR

ecei

ving

Dat

aA

CK

Rec

eivi

ng D

ata

R/W

= 0 AC

K

Rec

eivi

ng A

ddre

ss

Cle

ared

in s

oftw

are

SS

PB

UF

is r

ead

Bus

mas

ter

term

inat

estr

ansf

er

SS

PO

V is

set

beca

use

SS

PB

UF

isst

ill fu

ll. A

CK

is n

ot s

ent.

D2 6

(PIR

1<3>

)

CK

P

CK

Pw

ritte

nto

‘1’ i

nIf

BF

is c

lear

edpr

ior

to th

e fa

lling

edge

of t

he 9

th c

lock

,C

KP

will

not

be

rese

tto

‘0’ a

nd n

o cl

ock

stre

tchi

ng w

ill o

ccur

softw

are

Clo

ck is

hel

d lo

w u

ntil

CK

P is

set

to ‘1

’

Clo

ck is

not

hel

d lo

wbe

caus

e bu

ffer

full

bit i

s cl

ear

prio

r to

falli

ng e

dge

of 9

th c

lock

C

lock

is n

ot h

eld

low

beca

use

AC

K =

1

BF

is s

et a

fter

falli

ng

edge

of t

he 9

th c

lock

,C

KP

is r

eset

to ‘0

’ and

cloc

k st

retc

hing

occ

urs

PIC18F6585/8585/6680/8680

FIGURE 17-14: I2C SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS)

SD

A

SC

L

SS

PIF

BF

(S

SP

STA

T<

0>)

S1

23

45

67

89

12

34

56

78

91

23

45

78

9P

11

11

0A

9A

8A

7A

6A

5A

4A

3A

2A

1A

0D

7D

6D

5D

4D

3D

1D

0

Rec

eive

Dat

a B

yte

AC

K

R/W

= 0

AC

K

Rec

eive

Firs

t Byt

e of

Add

ress

Cle

ared

in s

oftw

are

D2 6

(PIR

1<3>

)

Cle

ared

in s

oftw

are

Rec

eive

Sec

ond

Byt

e of

Add

ress

Cle

ared

by

hard

war

e w

hen

SS

PA

DD

is u

pdat

ed w

ith lo

wby

te o

f add

ress

afte

r fa

lling

edg

e

UA

(S

SP

STA

T<

1>)

Clo

ck is

hel

d lo

w u

ntil

upda

te o

f SS

PA

DD

has

ta

ken

plac

e

UA

is s

et in

dica

ting

that

the

SS

PA

DD

nee

ds to

be

upda

ted

UA

is s

et in

dica

ting

that

SS

PA

DD

nee

ds to

be

upda

ted

Cle

ared

by

hard

war

e w

hen

SS

PA

DD

is u

pdat

ed w

ith h

igh

byte

of a

ddre

ss a

fter

falli

ng e

dge

SS

PB

UF

is w

ritte

n w

ithco

nten

ts o

f SS

PS

RD

umm

y re

ad o

f SS

PB

UF

to c

lear

BF

flag

AC

K

CK

P

12

34

57

89

D7

D6

D5

D4

D3

D1

D0

Rec

eive

Dat

a B

yte

Bus

mas

ter

term

inat

estr

ansf

er

D2 6

AC

K

Cle

ared

in s

oftw

are

Cle

ared

in s

oftw

are

SS

PO

V (

SS

PC

ON

<6>

)

CK

P w

ritte

n to

‘1’

No

te:

An

upda

te o

f the

SS

PA

DD

regi

ster

bef

ore

the

falli

nged

ge o

f the

nin

th c

lock

will

have

no

effe

ct o

n U

A a

ndU

A w

ill r

emai

n se

t.

No

te:

An

upda

te o

f th

e S

SP

AD

Dre

gist

er b

efor

e th

e fa

lling

edge

of

the

nint

h cl

ock

will

have

no

effe

ct o

n U

A a

ndU

A w

ill r

emai

n se

t. in

sof

twar

e

Clo

ck is

hel

d lo

w u

ntil

upda

te o

f SS

PA

DD

has

ta

ken

plac

e of n

inth

clo

ck.

of n

inth

clo

ck

SS

PO

V is

set

beca

use

SS

PB

UF

isst

ill fu

ll. A

CK

is n

ot s

ent.

Dum

my

read

of S

SP

BU

Fto

cle

ar B

F fl

ag

Clo

ck is

hel

d lo

w u

ntil

CK

P is

set

to ‘1

’C

lock

is n

ot h

eld

low

beca

use

AC

K =

1

PIC18F6585/8585/6680/8680

17.4.5 GENERAL CALL ADDRESS SUPPORT

The addressing procedure for the I2C bus is such thatthe first byte after the Start condition usuallydetermines which device will be the slave addressed bythe master. The exception is the general call addresswhich can address all devices. When this address isused, all devices should, in theory, respond with anAcknowledge.

The general call address is one of eight addressesreserved for specific purposes by the I2C protocol. Itconsists of all ‘0’s with R/W = 0.

The general call address is recognized when the Gen-eral Call Enable bit (GCEN) is enabled (SSPCON2<7>is set). Following a Start bit detect, 8 bits are shifted intothe SSPSR and the address is compared against theSSPADD. It is also compared to the general calladdress and fixed in hardware.

If the general call address matches, the SSPSR istransferred to the SSPBUF, the BF flag bit is set (eighthbit) and on the falling edge of the ninth bit (ACK bit), theSSPIF interrupt flag bit is set.

When the interrupt is serviced, the source for the inter-rupt can be checked by reading the contents of theSSPBUF. The value can be used to determine if theaddress was device specific or a general call address.

In 10-bit mode, the SSPADD is required to be updatedfor the second half of the address to match and the UAbit is set (SSPSTAT<1>). If the general call address issampled when the GCEN bit is set while the slave isconfigured in 10-bit Address mode, then the secondhalf of the address is not necessary, the UA bit will notbe set and the slave will begin receiving data after theAcknowledge (Figure 17-15).

FIGURE 17-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS MODE)

SDA

SCL

S

SSPIF

BF (SSPSTAT<0>)

SSPOV (SSPCON1<6>)

Cleared in software

SSPBUF is read

R/W = 0ACKGeneral Call Address

Address is compared to General Call Address

GCEN (SSPCON2<7>)

Receiving Data ACK

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

D7 D6 D5 D4 D3 D2 D1 D0

after ACK, set interrupt

‘0’

‘1’

PIC18F6585/8585/6680/8680

17.4.6 MASTER MODE

Master mode is enabled by setting and clearing theappropriate SSPM bits in SSPCON1 and by setting theSSPEN bit. In Master mode, the SCL and SDA linesare manipulated by the MSSP hardware.

Master mode of operation is supported by interruptgeneration on the detection of the Start and Stopconditions. The Stop (P) and Start (S) bits are clearedfrom a Reset or when the MSSP module is disabled.Control of the I2C bus may be taken when the P bit isset or the bus is Idle, with both the S and P bits clear.

In Firmware Controlled Master mode, user codeconducts all I2C bus operations based on Start andStop bit conditions.

Once Master mode is enabled, the user has sixoptions.

1. Assert a Start condition on SDA and SCL.2. Assert a Repeated Start condition on SDA and

SCL.3. Write to the SSPBUF register initiating

transmission of data/address.4. Configure the I2C port to receive data.5. Generate an Acknowledge condition at the end

of a received byte of data.6. Generate a Stop condition on SDA and SCL.

The following events will cause SSP interrupt flag bit,SSPIF, to be set (SSP interrupt if enabled):

• Start Condition

• Stop Condition• Data Transfer Byte Transmitted/Received• Acknowledge Transmit

• Repeated Start

FIGURE 17-16: MSSP BLOCK DIAGRAM (I2C MASTER MODE)

Note: The MSSP module, when configured inI2C Master mode, does not allow queueingof events. For instance, the user is notallowed to initiate a Start condition andimmediately write the SSPBUF register toinitiate transmission before the Start condi-tion is complete. In this case, the SSPBUFwill not be written to and the WCOL bit willbe set, indicating that a write to theSSPBUF did not occur.

Read Write

SSPSR

Start bit, Stop bit,

Start bit Detect

SSPBUF

InternalData Bus

Set/Reset S, P, WCOL (SSPSTAT)

ShiftClock

MSb LSb

SDA

AcknowledgeGenerate

Stop bit DetectWrite Collision Detect

Clock ArbitrationState Counter forend of XMIT/RCV

SCL

SCL In

Bus Collision

SDA In

Rec

eive

Ena

ble

Clo

ck C

ntl

Clo

ck A

rbitr

ate/

WC

OL

Det

ect

(hol

d of

f clo

ck s

ourc

e)

SSPADD<6:0>

Baud

Set SSPIF, BCLIFReset ACKSTAT, PEN (SSPCON2)

RateGenerator

SSPM3:SSPM0

PIC18F6585/8585/6680/8680

17.4.6.1 I2C Master Mode Operation

The master device generates all of the serial clockpulses and the Start and Stop conditions. A transfer isended with a Stop condition or with a Repeated Startcondition. Since the Repeated Start condition is alsothe beginning of the next serial transfer, the I2C bus willnot be released.

In Master Transmitter mode, serial data is outputthrough SDA while SCL outputs the serial clock. Thefirst byte transmitted contains the slave address of thereceiving device (7 bits) and the Read/Write (R/W) bit.In this case, the R/W bit will be logic ‘0’. Serial data istransmitted 8 bits at a time. After each byte is transmit-ted, an Acknowledge bit is received. Start and Stopconditions are output to indicate the beginning and theend of a serial transfer.

In Master Receive mode, the first byte transmitted con-tains the slave address of the transmitting device(7 bits) and the R/W bit. In this case, the R/W bit will belogic ‘1’. Thus, the first byte transmitted is a 7-bit slaveaddress followed by a ‘1’ to indicate a receive bit. Serialdata is received via SDA while SCL outputs the serialclock. Serial data is received 8 bits at a time. After eachbyte is received, an Acknowledge bit is transmitted.Start and Stop conditions indicate the beginning andend of transmission.

The Baud Rate Generator used for the SPI modeoperation is used to set the SCL clock frequency foreither 100 kHz, 400 kHz or 1 MHz I2C operation. SeeSection 17.4.7 “Baud Rate Generator” for moredetail.

A typical transmit sequence would go as follows:

1. The user generates a Start condition by settingthe Start enable bit, SEN (SSPCON2<0>).

2. SSPIF is set. The MSSP module will wait therequired start time before any other operationtakes place.

3. The user loads the SSPBUF with the slaveaddress to transmit.

4. Address is shifted out the SDA pin until all 8 bitsare transmitted.

5. The MSSP module shifts in the ACK bit from theslave device and writes its value into theSSPCON2 register (SSPCON2<6>).

6. The MSSP module generates an interrupt at theend of the ninth clock cycle by setting the SSPIFbit.

7. The user loads the SSPBUF with eight bits ofdata.

8. Data is shifted out the SDA pin until all 8 bits aretransmitted.

9. The MSSP module shifts in the ACK bit from theslave device and writes its value into theSSPCON2 register (SSPCON2<6>).

10. The MSSP module generates an interrupt at theend of the ninth clock cycle by setting the SSPIFbit.

11. The user generates a Stop condition by settingthe Stop enable bit PEN (SSPCON2<2>).

12. Interrupt is generated once the Stop condition iscomplete.

PIC18F6585/8585/6680/8680

17.4.7 BAUD RATE GENERATOR

In I2C Master mode, the Baud Rate Generator (BRG)reload value is placed in the lower 7 bits of theSSPADD register (Figure 17-17). When a write occursto SSPBUF, the Baud Rate Generator will automaticallybegin counting. The BRG counts down to ‘0’ and stopsuntil another reload has taken place. The BRG count isdecremented twice per instruction cycle (TCY) on theQ2 and Q4 clocks. In I2C Master mode, the BRG isreloaded automatically.

Once the given operation is complete (i.e., transmis-sion of the last data bit is followed by ACK), the internalclock will automatically stop counting and the SCL pinwill remain in its last state.

Table 17-3 demonstrates clock rates based oninstruction cycles and the BRG value loaded intoSSPADD.

FIGURE 17-17: BAUD RATE GENERATOR BLOCK DIAGRAM

TABLE 17-3: I2C CLOCK RATE w/BRG

SSPM3:SSPM0

BRG Down CounterCLKO FOSC/4

SSPADD<6:0>

SSPM3:SSPM0

SCL

Reload

Control

Reload

FCY FCY*2 BRG ValueFSCL

(2 Rollovers of BRG)

10 MHz 20 MHz 19h 400 kHz(1)

10 MHz 20 MHz 20h 312.5 kHz

10 MHz 20 MHz 64h 100 kHz

4 MHz 8 MHz 0Ah 400 kHz(1)

4 MHz 8 MHz 0Dh 308 kHz

4 MHz 8 MHz 28h 100 kHz

1 MHz 2 MHz 03h 333 kHz(1)

1 MHz 2 MHz 0Ah 100 kHz

1 MHz 2 MHz 00h 1 MHz(1)

Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100 kHz) in all details but may be used with care where higher rates are required by the application.

PIC18F6585/8585/6680/8680

17.4.7.1 Clock Arbitration

Clock arbitration occurs when the master, during anyreceive, transmit or Repeated Start/Stop condition,deasserts the SCL pin (SCL allowed to float high).When the SCL pin is allowed to float high, the BaudRate Generator (BRG) is suspended from countinguntil the SCL pin is actually sampled high. When the

SCL pin is sampled high, the Baud Rate Generator isreloaded with the contents of SSPADD<6:0> andbegins counting. This ensures that the SCL high timewill always be at least one BRG rollover count in theevent that the clock is held low by an external device(Figure 17-18).

FIGURE 17-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

SDA

SCL

SCL deasserted but slave holds

DX-1DX

BRG

SCL is sampled high, reload takesplace and BRG starts its count

03h 02h 01h 00h (hold off) 03h 02h

Reload

BRGValue

SCL low (clock arbitration)SCL allowed to transition high

BRG decrements onQ2 and Q4 cycles

PIC18F6585/8585/6680/8680

17.4.8 I2C MASTER MODE START CONDITION TIMING

To initiate a Start condition, the user sets the Start Con-dition Enable bit, SEN (SSPCON2<0>). If the SDA andSCL pins are sampled high, the Baud Rate Generatoris reloaded with the contents of SSPADD<6:0> andstarts its count. If SCL and SDA are both sampled highwhen the Baud Rate Generator times out (TBRG), theSDA pin is driven low. The action of the SDA beingdriven low while SCL is high is the Start condition andcauses the S bit (SSPSTAT<3>) to be set. Followingthis, the Baud Rate Generator is reloaded with thecontents of SSPADD<6:0> and resumes its count.When the Baud Rate Generator times out (TBRG), theSEN bit (SSPCON2<0>) will be automatically clearedby hardware, the Baud Rate Generator is suspended,leaving the SDA line held low and the Start condition iscomplete.

17.4.8.1 WCOL Status Flag

If the user writes the SSPBUF when a Start sequenceis in progress, the WCOL is set and the contents of thebuffer are unchanged (the write doesn’t occur).

FIGURE 17-19: FIRST START BIT TIMING

Note: If at the beginning of the Start condition,the SDA and SCL pins are already sam-pled low or if during the Start condition, theSCL line is sampled low before the SDAline is driven low, a bus collision occurs,the Bus Collision Interrupt Flag, BCLIF, isset, the Start condition is aborted and theI2C module is reset into its Idle state.

Note: Because queueing of events is notallowed, writing to the lower 5 bits ofSSPCON2 is disabled until the Startcondition is complete.

SDA

SCL

S

TBRG

1st bit 2nd bit

TBRG

SDA = 1, At completion of Start bit,SCL = 1

Write to SSPBUF occurs hereTBRG

hardware clears SEN bit

TBRG

Write to SEN bit occurs hereSet S bit (SSPSTAT<3>)

and sets SSPIF bit

PIC18F6585/8585/6680/8680

17.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING

A Repeated Start condition occurs when the RSEN bit(SSPCON2<1>) is programmed high and the I2C logicmodule is in the Idle state. When the RSEN bit is set,the SCL pin is asserted low. When the SCL pin issampled low, the Baud Rate Generator is loaded withthe contents of SSPADD<5:0> and begins counting.The SDA pin is released (brought high) for one BaudRate Generator count (TBRG). When the Baud RateGenerator times out, if SDA is sampled high, the SCLpin will be deasserted (brought high). When SCL issampled high, the Baud Rate Generator is reloadedwith the contents of SSPADD<6:0> and begins count-ing. SDA and SCL must be sampled high for one TBRG.This action is then followed by assertion of the SDA pin(SDA = 0) for one TBRG while SCL is high. Followingthis, the RSEN bit (SSPCON2<1>) will be automaticallycleared and the Baud Rate Generator will not bereloaded, leaving the SDA pin held low. As soon as aStart condition is detected on the SDA and SCL pins,the S bit (SSPSTAT<3>) will be set. The SSPIF bit willnot be set until the Baud Rate Generator has timed out.

Immediately following the SSPIF bit getting set, theuser may write the SSPBUF with the 7-bit address in7-bit mode, or the default first address in 10-bit mode.After the first eight bits are transmitted and an ACK isreceived, the user may then transmit an additional eightbits of address (10-bit mode) or eight bits of data (7-bitmode).


If the user writes the SSPBUF when a Repeated Startsequence is in progress, the WCOL is set and the con-tents of the buffer are unchanged (the write doesn’toccur).

FIGURE 17-20: REPEAT START CONDITION WAVEFORM

Note 1: If RSEN is programmed while any otherevent is in progress, it will not take effect.

2: A bus collision during the Repeated Startcondition occurs if:

• SDA is sampled low when SCL goes from low-to-high.

• SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data ‘1’.

Note: Because queueing of events is notallowed, writing of the lower 5 bits ofSSPCON2 is disabled until the RepeatedStart condition is complete.

SDA

SCL

Sr = Repeated Start

Write to SSPCON2

Write to SSPBUF occurs hereFalling edge of ninth clock,end of Xmit

At completion of Start bit, hardware clears RSEN bit

1st bit

Set S (SSPSTAT<3>)

TBRG

TBRG

SDA = 1,

SDA = 1,

SCL (no change).

SCL = 1occurs here.

TBRG TBRG TBRG

and sets SSPIF

PIC18F6585/8585/6680/8680

17.4.10 I2C MASTER MODE TRANSMISSION

Transmission of a data byte, a 7-bit address, or theother half of a 10-bit address is accomplished by simplywriting a value to the SSPBUF register. This action willset the Buffer Full flag bit, BF and allow the Baud RateGenerator to begin counting and start the next trans-mission. Each bit of address/data will be shifted outonto the SDA pin after the falling edge of SCL isasserted (see data hold time specification parameter#106). SCL is held low for one Baud Rate Generatorrollover count (TBRG). Data should be valid before SCLis released high (see data setup time specificationparameter #107). When the SCL pin is released high, itis held that way for TBRG. The data on the SDA pinmust remain stable for that duration and some holdtime after the next falling edge of SCL. After the eighthbit is shifted out (the falling edge of the eighth clock),the BF flag is cleared and the master releases SDA.This allows the slave device being addressed torespond with an ACK bit during the ninth bit time if anaddress match occurred, or if data was receivedproperly. The status of ACK is written into the ACKDTbit on the falling edge of the ninth clock. If the masterreceives an Acknowledge, the Acknowledge Status bit,ACKSTAT, is cleared. If not, the bit is set. After the ninthclock, the SSPIF bit is set and the master clock (BaudRate Generator) is suspended until the next data byteis loaded into the SSPBUF, leaving SCL low and SDAunchanged (Figure 17-21).

After the write to the SSPBUF, each bit of the addresswill be shifted out on the falling edge of SCL until allseven address bits and the R/W bit are completed. Onthe falling edge of the eighth clock, the master willdeassert the SDA pin, allowing the slave to respondwith an Acknowledge. On the falling edge of the ninthclock, the master will sample the SDA pin to see if theaddress was recognized by a slave. The status of theACK bit is loaded into the ACKSTAT status bit(SSPCON2<6>). Following the falling edge of the ninthclock transmission of the address, the SSPIF is set, theBF flag is cleared and the Baud Rate Generator isturned off until another write to the SSPBUF takesplace, holding SCL low and allowing SDA to float.

17.4.10.1 BF Status Flag

In Transmit mode, the BF bit (SSPSTAT<0>) is setwhen the CPU writes to SSPBUF and is cleared whenall 8 bits are shifted out.


If the user writes the SSPBUF when a transmit isalready in progress (i.e., SSPSR is still shifting out adata byte), the WCOL is set and the contents of thebuffer are unchanged (the write doesn’t occur).

WCOL must be cleared in software.

17.4.10.3 ACKSTAT Status Flag

In Transmit mode, the ACKSTAT bit (SSPCON2<6>) iscleared when the slave has sent an Acknowledge(ACK = 0) and is set when the slave does not Acknowl-edge (ACK = 1). A slave sends an Acknowledge whenit has recognized its address (including a general call)or when the slave has properly received its data.

17.4.11 I2C MASTER MODE RECEPTION

Master mode reception is enabled by programming thereceive enable bit, RCEN (SSPCON2<3>).

The Baud Rate Generator begins counting and on eachrollover, the state of the SCL pin changes (high-to-low/low-to-high) and data is shifted into the SSPSR. After thefalling edge of the eighth clock, the receive enable flag isautomatically cleared, the contents of the SSPSR areloaded into the SSPBUF, the BF flag bit is set, the SSPIFflag bit is set and the Baud Rate Generator is suspendedfrom counting, holding SCL low. The MSSP is now in Idlestate awaiting the next command. When the buffer isread by the CPU, the BF flag bit is automatically cleared.The user can then send an Acknowledge bit at the endof reception by setting the Acknowledge sequenceenable bit, ACKEN (SSPCON2<4>).

17.4.11.1 BF Status Flag

In receive operation, the BF bit is set when an addressor data byte is loaded into SSPBUF from SSPSR. It iscleared when the SSPBUF register is read.

17.4.11.2 SSPOV Status Flag

In receive operation, the SSPOV bit is set when 8 bitsare received into the SSPSR and the BF flag bit isalready set from a previous reception.


If the user writes the SSPBUF when a receive isalready in progress (i.e., SSPSR is still shifting in a databyte), the WCOL bit is set and the contents of the bufferare unchanged (the write doesn’t occur).

Note: The MSSP module must be in an Idle statebefore the RCEN bit is set or the RCEN bitwill be disregarded.

PIC18F6585/8585/6680/8680

FIGURE 17-21: I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)

SD

A

SC

L

SS

PIF

BF

(S

SP

STA

T<

0>)

SE

N

A7

A6

A5

A4

A3

A2

A1

AC

K =

0D

7D

6D

5D

4D

3D

2D

1D

0

AC

KT

rans

mitt

ing

Dat

a or

Sec

ond

Hal

fR

/W =

0Tr

ansm

it A

ddre

ss to

Sla

ve

12

34

56

78

91

23

45

67

89

P

Cle

ared

in s

oftw

are

serv

ice

rout

ine

SS

PB

UF

is w

ritte

n in

sof

twar

e

from

SS

P in

terr

upt

Afte

r S

tart

con

ditio

n, S

EN

cle

ared

by

hard

war

e

S

SS

PB

UF

writ

ten

with

7-b

it ad

dres

s an

d R

/Wst

art t

rans

mit

SC

L he

ld lo

ww

hile

CP

Ure

spon

ds to

SS

PIF

SE

N =

0

of 1

0-bi

t Add

ress

Writ

e S

SP

CO

N2<

0> S

EN

= 1

, S

tart

con

ditio

n be

gins

Fro

m s

lave

cle

ar A

CK

STA

T b

it S

SP

CO

N2<

6>

AC

KS

TAT

in

SS

PC

ON

2 =

1

Cle

ared

in s

oftw

are

SS

PB

UF

writ

ten

PE

N

Cle

ared

in s

oftw

are

R/W

PIC18F6585/8585/6680/8680

FIGURE 17-22: I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)

P9

87

65

D0

D1

D2

D3

D4

D5

D6

D7

S

A7

A6

A5

A4

A3

A2

A1

SD

A

SC

L1

23

45

67

89

12

34

56

78

91

23

4

Bus

mas

ter

term

inat

estr

ansf

er

AC

K

Rec

eivi

ng D

ata

from

Sla

veR

ecei

ving

Dat

a fr

om S

lave

D0

D1

D2

D3

D4

D5

D6

D7

AC

K

R/W

= 1

Tra

nsm

it A

ddre

ss to

Sla

ve

SS

PIF

BF

AC

K is

not

sen

t

Writ

e to

SS

PC

ON

2<0>

(SE

N =

1),

Writ

e to

SS

PB

UF

occ

urs

here

,A

CK

from

Sla

veMas

ter

conf

igur

ed a

s a

rece

iver

by p

rogr

amm

ing

SS

PC

ON

2<3>

(R

CE

N =

1)

PE

N b

it =

1w

ritte

n he

re

Dat

a sh

ifted

in o

n fa

lling

edg

e of

CLK

Cle

ared

in s

oftw

are

star

t XM

IT

SE

N =

0

SS

PO

V

SD

A =

0, S

CL

= 1

whi

le C

PU

(SS

PS

TAT

<0>

)

AC

K

Last

bit

is s

hifte

d in

to S

SP

SR

and

cont

ents

are

unl

oade

d in

to S

SP

BU

F

Cle

ared

in s

oftw

are

Cle

ared

in s

oftw

are

Set

SS

PIF

inte

rrup

tat

end

of r

ecei

ve

Set

P b

it (S

SP

STA

T<

4>)

and

SS

PIF

Cle

ared

inso

ftwar

e

AC

K fr

om M

aste

r

Set

SS

PIF

at e

nd

Set

SS

PIF

inte

rrup

tat

end

of A

ckno

wle

dge

sequ

ence

Set

SS

PIF

inte

rrup

tat

end

of A

ckno

w-

ledg

e se

quen

ce

of r

ecei

ve

Set

AC

KE

N, s

tart

Ack

now

ledg

e se

quen

ce,

SS

PO

V is

set

bec

ause

SS

PB

UF

is s

till f

ull

SD

A =

AC

KD

T =

1

RC

EN

cle

ared

auto

mat

ical

lyR

CE

N =

1,

star

t nex

t rec

eive

Writ

e to

SS

PC

ON

2<4>

to s

tart

Ack

now

ledg

e se

quen

ce,

SD

A =

AC

KD

T (

SS

PC

ON

2<5>

) =

0

RC

EN

cle

ared

auto

mat

ical

ly

resp

onds

to S

SP

IF

AC

KE

Nbegi

n S

tart

Con

ditio

n

Cle

ared

in s

oftw

are

SD

A =

AC

KD

T =

0

PIC18F6585/8585/6680/8680

17.4.12 ACKNOWLEDGE SEQUENCE TIMING

An Acknowledge sequence is enabled by settingthe Acknowledge Sequence Enable bit, ACKEN(SSPCON2<4>). When this bit is set, the SCL pin ispulled low and the contents of the Acknowledge data bitare presented on the SDA pin. If the user wishes to gen-erate an Acknowledge, then the ACKDT bit should becleared. If not, the user should set the ACKDT bit beforestarting an Acknowledge sequence. The Baud RateGenerator then counts for one rollover period (TBRG)and the SCL pin is deasserted (pulled high). When theSCL pin is sampled high (clock arbitration), the BaudRate Generator counts for TBRG. The SCL pin is thenpulled low. Following this, the ACKEN bit is automaticallycleared, the Baud Rate Generator is turned off and theMSSP module then goes into Idle mode (Figure 17-23).


If the user writes the SSPBUF when an Acknowledgesequence is in progress, then WCOL is set and thecontents of the buffer are unchanged (the write doesn’toccur).

17.4.13 STOP CONDITION TIMING

A Stop bit is asserted on the SDA pin at the end of areceive/transmit by setting the Stop Sequence Enablebit, PEN (SSPCON2<2>). At the end of a receive/transmit, the SCL line is held low after the falling edgeof the ninth clock. When the PEN bit is set, the masterwill assert the SDA line low. When the SDA line issampled low, the Baud Rate Generator is reloaded andcounts down to ‘0’. When the Baud Rate Generatortimes out, the SCL pin will be brought high and oneTBRG (Baud Rate Generator rollover count) later, theSDA pin will be deasserted. When the SDA pin is sam-pled high while SCL is high, the P bit (SSPSTAT<4>) isset. A TBRG later, the PEN bit is cleared and the SSPIFbit is set (Figure 17-24).


If the user writes the SSPBUF when a Stop sequenceis in progress, then the WCOL bit is set and the con-tents of the buffer are unchanged (the write doesn’toccur).

FIGURE 17-23: ACKNOWLEDGE SEQUENCE WAVEFORM

FIGURE 17-24: STOP CONDITION RECEIVE OR TRANSMIT MODE

Note: TBRG = one Baud Rate Generator period.

SDA

SCL

Set SSPIF at the end

Acknowledge sequence starts here,write to SSPCON2

ACKEN automatically cleared

Cleared in

TBRG TBRG

of receive

ACK

8

ACKEN = 1, ACKDT = 0

D0

9

SSPIF

software Set SSPIF at the endof Acknowledge sequence

Cleared insoftware

SCL

SDA

SDA asserted low before rising edge of clock

Write to SSPCON2,set PEN

Falling edge of

SCL = 1 for TBRG, followed by SDA = 1 for TBRG

9th clock

SCL brought high after TBRG

Note: TBRG = one Baud Rate Generator period.

TBRG TBRG

after SDA sampled high. P bit (SSPSTAT<4>) is set.

TBRG

to setup Stop condition

ACK

PTBRG

PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set

PIC18F6585/8585/6680/8680

17.4.14 SLEEP OPERATION

While in Sleep mode, the I2C module can receiveaddresses or data and when an address match or com-plete byte transfer occurs, wake the processor fromSleep (if the MSSP interrupt is enabled).

17.4.15 EFFECT OF A RESET

A Reset disables the MSSP module and terminates thecurrent transfer.

17.4.16 MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on thedetection of the Start and Stop conditions allows thedetermination of when the bus is free. The Stop (P) andStart (S) bits are cleared from a Reset or when theMSSP module is disabled. Control of the I2C bus maybe taken when the P bit (SSPSTAT<4>) is set or thebus is Idle, with both the S and P bits clear. When thebus is busy, enabling the SSP interrupt will generatethe interrupt when the Stop condition occurs.

In multi-master operation, the SDA line must be moni-tored for arbitration to see if the signal level is theexpected output level. This check is performed inhardware with the result placed in the BCLIF bit.

The states where arbitration can be lost are:

• Address Transfer

• Data Transfer• A Start Condition • A Repeated Start Condition

• An Acknowledge Condition

17.4.17 MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION

Multi-Master mode support is achieved by bus arbitra-tion. When the master outputs address/data bits ontothe SDA pin, arbitration takes place when the masteroutputs a ‘1’ on SDA by letting SDA float high andanother master asserts a ‘0’. When the SCL pin floatshigh, data should be stable. If the expected data onSDA is a ‘1’ and the data sampled on the SDA pin = 0,then a bus collision has taken place. The master will setthe Bus Collision Interrupt Flag, BCLIF and reset theI2C port to its Idle state (Figure 17-25).

If a transmit was in progress when the bus collisionoccurred, the transmission is halted, the BF flag iscleared, the SDA and SCL lines are deasserted and theSSPBUF can be written to. When the user services thebus collision Interrupt Service Routine and if the I2Cbus is free, the user can resume communication byasserting a Start condition.

If a Start, Repeated Start, Stop, or Acknowledge condi-tion was in progress when the bus collision occurred,the condition is aborted, the SDA and SCL lines aredeasserted, and the respective control bits in theSSPCON2 register are cleared. When the user ser-vices the bus collision Interrupt Service Routine and ifthe I2C bus is free, the user can resume communicationby asserting a Start condition.

The master will continue to monitor the SDA and SCLpins. If a Stop condition occurs, the SSPIF bit will be set.

A write to the SSPBUF will start the transmission ofdata at the first data bit regardless of where thetransmitter left off when the bus collision occurred.

In Multi-Master mode, the interrupt generation on thedetection of Start and Stop conditions allows the determi-nation of when the bus is free. Control of the I2C bus canbe taken when the P bit is set in the SSPSTAT register orthe bus is Idle and the S and P bits are cleared.

FIGURE 17-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

SDA

SCL

BCLIF

SDA released

SDA line pulled lowby another source

Sample SDA. While SCL is high,data doesn’t match what is driven

Bus collision has occurred.

Set bus collisioninterrupt (BCLIF)

by the master.

by master

Data changeswhile SCL = 0

PIC18F6585/8585/6680/8680

17.4.17.1 Bus Collision During a Start Condition

During a Start condition, a bus collision occurs if:

a) SDA or SCL are sampled low at the beginning ofthe Start condition (Figure 17-26).

b) SCL is sampled low before SDA is asserted low(Figure 17-27).

During a Start condition, both the SDA and the SCLpins are monitored.

If the SDA pin is already low or the SCL pin is alreadylow, then all of the following occur:

• the Start condition is aborted,

• the BCLIF flag is set, and• the MSSP module is reset to its Idle state

(Figure 17-26).

The Start condition begins with the SDA and SCL pinsdeasserted. When the SDA pin is sampled high, theBaud Rate Generator is loaded from SSPADD<6:0>and counts down to ‘0’. If the SCL pin is sampled lowwhile SDA is high, a bus collision occurs because it isassumed that another master is attempting to drive adata ‘1’ during the Start condition.

If the SDA pin is sampled low during this count, theBRG is reset and the SDA line is asserted early(Figure 17-28). If, however, a ‘1’ is sampled on the SDApin, the SDA pin is asserted low at the end of the BRGcount. The Baud Rate Generator is then reloaded andcounts down to ‘0’ and during this time, if the SCL pinsare sampled as ‘0’, a bus collision does not occur. Atthe end of the BRG count, the SCL pin is asserted low.

FIGURE 17-26: BUS COLLISION DURING START CONDITION (SDA ONLY)

Note: The reason that bus collision is not a factorduring a Start condition is that no two busmasters can assert a Start condition at theexact same time. Therefore, one masterwill always assert SDA before the other.This condition does not cause a buscollision because the two masters must beallowed to arbitrate the first address follow-ing the Start condition. If the address is thesame, arbitration must be allowed tocontinue into the data portion, RepeatedStart or Stop conditions.

SDA

SCL

SEN

SDA sampled low before

SDA goes low before the SEN bit is set.

S bit and SSPIF set because

SSP module reset into Idle state.SEN cleared automatically because of bus collision.

S bit and SSPIF set because

Set SEN, enable Startcondition if SDA = 1, SCL = 1

SDA = 0, SCL = 1.

BCLIF

S

SSPIF

SDA = 0, SCL = 1.

SSPIF and BCLIF arecleared in software

SSPIF and BCLIF arecleared in software

Set BCLIF;

Start condition. Set BCLIF;

PIC18F6585/8585/6680/8680

FIGURE 17-27: BUS COLLISION DURING START CONDITION (SCL = 0)

FIGURE 17-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION

SDA

SCL

SENbus collision occurs. Set BCLIF.SCL = 0 before SDA = 0,

Set SEN, enable Startsequence if SDA = 1, SCL = 1

TBRG TBRG

SDA = 0, SCL = 1

BCLIF

S

SSPIF

Interrupt clearedin software

bus collision occurs. Set BCLIF.SCL = 0 before BRG time-out,

‘0’ ‘0’

‘0’‘0’

SDA

SCL

SEN

Set S

Set SEN, enable STARTsequence if SDA = 1, SCL = 1

Less than TBRGTBRG

SDA = 0, SCL = 1

BCLIF

S

SSPIF

S

Interrupts clearedin softwareset SSPIF

SDA = 0, SCL = 1,

SDA pulled low by other master.Reset BRG and assert SDA.

SCL pulled low after BRGTime-out

Set SSPIF

‘0’


PIC18F6585/8585/6680/8680

17.4.17.2 Bus Collision During a Repeated Start Condition

During a Repeated Start condition, a bus collisionoccurs if:

a) A low level is sampled on SDA when SCL goesfrom low level to high level.

b) SCL goes low before SDA is asserted low,indicating that another master is attempting totransmit a data ‘1’.

When the user deasserts SDA and the pin is allowed tofloat high, the BRG is loaded with SSPADD<6:0> andcounts down to ‘0’. The SCL pin is then deasserted andwhen sampled high, the SDA pin is sampled.

If SDA is low, a bus collision has occurred (i.e., anothermaster is attempting to transmit a data ‘0’, seeFigure 17-29). If SDA is sampled high, the BRG is

reloaded and begins counting. If SDA goes from high tolow before the BRG times out, no bus collision occursbecause no two masters can assert SDA at exactly thesame time.

If SCL goes from high to low before the BRG times outand SDA has not already been asserted, a bus collisionoccurs. In this case, another master is attempting totransmit a data ‘1’ during the Repeated Start condition(see Figure 17-30).

If, at the end of the BRG time-out, both SCL and SDAare still high, the SDA pin is driven low and the BRG isreloaded and begins counting. At the end of the count,regardless of the status of the SCL pin, the SCL pin isdriven low and the Repeated Start condition iscomplete.

FIGURE 17-29: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

FIGURE 17-30: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

SDA

SCL

RSEN

BCLIF

S

SSPIF

Sample SDA when SCL goes high.If SDA = 0, set BCLIF and release SDA and SCL.

Cleared in software

‘0’

‘0’

SDA

SCL

BCLIF

RSEN

S

SSPIF

Interrupt clearedin software

SCL goes low before SDA,set BCLIF. Release SDA and SCL.

TBRG TBRG

‘0’

PIC18F6585/8585/6680/8680

17.4.17.3 Bus Collision During a Stop Condition

Bus collision occurs during a Stop condition if:

a) After the SDA pin has been deasserted andallowed to float high, SDA is sampled low afterthe BRG has timed out.

b) After the SCL pin is deasserted, SCL is sampledlow before SDA goes high.

The Stop condition begins with SDA asserted low.When SDA is sampled low, the SCL pin is allowed tofloat. When the pin is sampled high (clock arbitration),the Baud Rate Generator is loaded with SSPADD<6:0>and counts down to ‘0’. After the BRG times out, SDAis sampled. If SDA is sampled low, a bus collision hasoccurred. This is due to another master attempting todrive a data ‘0’ (Figure 17-31). If the SCL pin issampled low before SDA is allowed to float high, a buscollision occurs. This is another case of another masterattempting to drive a data ‘0’ (Figure 17-32).

FIGURE 17-31: BUS COLLISION DURING A STOP CONDITION (CASE 1)

FIGURE 17-32: BUS COLLISION DURING A STOP CONDITION (CASE 2)

SDA

SCL

BCLIF

PEN

P

SSPIF

TBRG TBRG TBRG

SDA asserted low

SDA sampledlow after TBRG,set BCLIF

‘0’

‘0’

SDA

SCL

BCLIF

PEN

P

SSPIF

TBRG TBRG TBRG

Assert SDASCL goes low before SDA goes high,set BCLIF

‘0’

‘0’

PIC18F6585/8585/6680/8680

NOTES:


PIC18F6585/8585/6680/8680

18.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART)

The Universal Synchronous Asynchronous ReceiverTransmitter (USART) module is one of the two serialI/O modules. (USART is also known as a SerialCommunications Interface or SCI.) The USART can beconfigured as a full-duplex asynchronous system thatcan communicate with peripheral devices, such asCRT terminals and personal computers. It can also beconfigured as a half-duplex synchronous system thatcan communicate with peripheral devices, such as A/Dor D/A integrated circuits, serial EEPROMs, etc.

The Enhanced USART module implements additionalfeatures, including automatic baud rate detection andcalibration, automatic wake-up on sync break receptionand 12-bit break character transmit. These make itideally suited for use in Local Interconnect Network bus(LIN bus) systems.

The USART can be configured in the following modes:

• Asynchronous (full-duplex) with:- Auto-wake-up on character reception

- Auto-baud calibration- 12-bit break character transmission

• Synchronous – Master (half-duplex) with selectable clock polarity

• Synchronous – Slave (half-duplex) with selectable clock polarity

In order to configure pins RC6/TX/CK and RC7/RX/DTas the Universal Synchronous Asynchronous ReceiverTransmitter:

• SPEN (RCSTA<7>) bit must be set (= 1),

• TRISC<6> bit must be set (= 1), and• TRISC<7> bit must be set (= 1).

The operation of the Enhanced USART module iscontrolled through three registers:

• Transmit Status and Control (TXSTA)• Receive Status and Control (RCSTA)

• Baud Rate Control (BAUDCON)

These are detailed on the following pages inRegister 18-1, Register 18-2 and Register 18-3,respectively.

Note: The USART control will automaticallyreconfigure the pin from input to output asneeded.

PIC18F6585/8585/6680/8680

REGISTER 18-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D

bit 7 bit 0

bit 7 CSRC: Clock Source Select bitAsynchronous mode: Don’t care.Synchronous mode: 1 = Master mode (clock generated internally from BRG)0 = Slave mode (clock from external source)

bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission

bit 5 TXEN: Transmit Enable bit 1 = Transmit enabled0 = Transmit disabled

Note: SREN/CREN overrides TXEN in Sync mode.

bit 4 SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode

bit 3 SENDB: Send Break Character bitAsynchronous mode:1 = Send sync break on next transmission (cleared by hardware upon completion)0 = Sync break transmission completed

Synchronous mode:Don’t care.

bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speedSynchronous mode: Unused in this mode.

bit 1 TRMT: Transmit Shift Register Status bit

1 = TSR empty 0 = TSR full

bit 0 TX9D: 9th bit of Transmit DataCan be address/data bit or a parity bit.

Legend:




PIC18F6585/8585/6680/8680

REGISTER 18-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x

SPEN RX9 SREN CREN ADDEN FERR OERR RX9D

bit 7 bit 0

bit 7 SPEN: Serial Port Enable bit1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)0 = Serial port disabled (held in Reset)

bit 6 RX9: 9-bit Receive Enable bit

1 = Selects 9-bit reception 0 = Selects 8-bit reception

bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care.Synchronous mode – Master: 1 = Enables single receive0 = Disables single receive This bit is cleared after reception is complete.

Synchronous mode – Slave: Don’t care.

bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver0 = Disables receiverSynchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive

bit 3 ADDEN: Address Detect Enable bitAsynchronous mode 9-bit (RX9 = 1):1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8>

is set0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit

Asynchronous mode 9-bit (RX9 = 0):Don’t care.

bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receiving next valid byte)0 = No framing error

bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error

bit 0 RX9D: 9th bit of Received Data

This can be an address/data bit or a parity bit and must be calculated by user firmware.

Legend:

PIC18F6585/8585/6680/8680

REGISTER 18-3: BAUDCON: BAUD RATE CONTROL REGISTER U-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

— RCIDL — SCKP BRG16 — WUE ABDEN

bit 7 bit 0


bit 6 RCIDL: Receive Operation Idle Status bit

1 = Receive operation is Idle0 = Receive operation is active


bit 4 SCKP: Synchronous Clock Polarity Select bitAsynchronous mode:Unused in this mode. Synchronous mode:1 = Idle state for clock (CK) is a high level0 = Idle state for clock (CK) is a low level

bit 3 BRG16: 16-bit Baud Rate Register Enable bit1 = 16-bit Baud Rate Generator – SPBRGH and SPBRG0 = 8-bit Baud Rate Generator – SPBRG only (Compatible mode), SPBRGH value ignored


bit 1 WUE: Wake-up Enable bit

Asynchronous mode:1 = USART will continue to sample the RX pin – interrupt generated on falling edge; bit cleared

in hardware on following rising edge0 = RX pin not monitored or rising edge detectedSynchronous mode:Unused in this mode.

bit 0 ABDEN: Auto-Baud Detect Enable bit

Asynchronous mode:1 = Enable baud rate measurement on the next character – requires reception of a sync field

(55h); cleared in hardware upon completion0 = Baud rate measurement disabled or completedSynchronous mode:Unused in this mode.

Legend:




PIC18F6585/8585/6680/8680

18.1 USART Baud Rate Generator (BRG)

The BRG is a dedicated 8-bit or 16-bit generator thatsupports both the Asynchronous and Synchronousmodes of the USART. By default, the BRG operates in8-bit mode; setting the BRG16 bit (BAUDCON<3>)selects 16-bit mode.

The SPBRGH:SPBRG register pair controls the periodof a free-running timer. In Asynchronous mode, bitsBRGH (TXSTA<2>) and BRG16 also control the baudrate. In Synchronous mode, bit BRGH is ignored.Table 18-1 shows the formula for computation of thebaud rate for different USART modes which only applyin Master mode (internally generated clock).

Given the desired baud rate and FOSC, the nearestinteger value for the SPBRGH:SPBRG registers can becalculated using the formulas in Table 18-1. From this,

the error in baud rate can be determined. An examplecalculation is shown in Example 18-1. Typical baudrates and error values for the various Asynchronousmodes are shown in Table 18-2. It may be advantageousto use the high baud rate (BRGH = 1) or the 16-bit BRGto reduce the baud rate error, or achieve a slow baudrate for a fast oscillator frequency.

Writing a new value to the SPBRGH:SPBRG registerscauses the BRG timer to be reset (or cleared). Thisensures the BRG does not wait for a timer overflowbefore outputting the new baud rate.

18.1.1 SAMPLING

The data on the RC7/RX/DT pin is sampled three timesby a majority detect circuit to determine if a high or alow level is present at the RX pin.

TABLE 18-1: BAUD RATE FORMULAS

EXAMPLE 18-1: CALCULATING BAUD RATE ERROR

TABLE 18-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

Configuration BitsBRG/USART Mode Baud Rate Formula

SYNC BRG16 BRGH

0 0 0 8-bit/Asynchronous FOSC/[64 (n + 1)]

0 0 1 8-bit/AsynchronousFOSC/[16 (n + 1)]

0 1 0 16-bit/Asynchronous

0 1 1 16-bit/Asynchronous

FOSC/[4 (n + 1)]1 0 x 8-bit/Synchronous

1 1 x 16-bit/Synchronous

Legend: x = Don’t care, n = Value of SPBRGH:SPBRG register pair


POR, BORValue on allother Resets

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

BAUDCON — RCIDL — SCKP BRG16 — WUE ABDEN -1-0 0-00 -1-0 0-00

SPBRGH Baud Rate Generator Register, High Byte 0000 0000 0000 0000

SPBRG Baud Rate Generator Register, Low Byte 0000 0000 0000 0000

Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.

For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:Desired Baud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1)) Solving for SPBRGH:SPBRG:

X = ((FOSC/Desired Baud Rate)/64) – 1= ((16000000/9600)/64) – 1 = [25.042] = 25

Calculated Baud Rate= 16000000/(64 (25 + 1)) = 9615

Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate= (9615 – 9600)/9600 = 0.16%

PIC18F6585/8585/6680/8680

TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES

BAUDRATE

(K)

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz

Actual Rate (K)

%Error

SPBRGvalue

(decimal)

Actual Rate (K)

%Error

SPBRGvalue

(decimal)

Actual Rate (K)

%Error

SPBRGvalue

(decimal)

Actual Rate (K)

%Error

SPBRGvalue

(decimal)

0.3 — — — — — — — — — — — —

1.2 — — — 1.221 1.73 255 1.202 0.16 129 1201 -0.16 103

2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2403 -0.16 51

9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9615 -0.16 12

19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — —

57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — —

115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — —

BAUDRATE

(K)

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz

Actual Rate (K)

%Error

SPBRGvalue

(decimal)

Actual Rate (K)

%Error

SPBRGvalue

(decimal)

Actual Rate (K)

%Error

SPBRGvalue

(decimal)

0.3 0.300 0.16 207 300 -0.16 103 300 -0.16 51

1.2 1.202 0.16 51 1201 -0.16 25 1201 -0.16 12

2.4 2.404 0.16 25 2403 -0.16 12 — — —

9.6 8.929 -6.99 6 — — — — — —

19.2 20.833 8.51 2 — — — — — —

57.6 62.500 8.51 0 — — — — — —

115.2 62.500 -45.75 0 — — — — — —

BAUDRATE

(K)

SYNC = 0, BRGH = 1, BRG16 = 0


Actual Rate (K)

%Error

SPBRGvalue

(decimal)

Actual Rate (K)

%Error

SPBRGvalue

(decimal)

Actual Rate (K)

%Error

SPBRGvalue

(decimal)

Actual Rate (K)

%Error

SPBRGvalue

(decimal)

0.3 — — — — — — — — — — — —

1.2 — — — — — — — — — — — —

2.4 — — — — — — 2.441 1.73 255 2403 -0.16 207

9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51

19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25

57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8

115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —

BAUDRATE

(K)

SYNC = 0, BRGH = 1, BRG16 = 0


Actual Rate (K)

%Error

SPBRGvalue

(decimal)

Actual Rate (K)

%Error

SPBRGvalue

(decimal)

Actual Rate (K)

%Error

SPBRGvalue

(decimal)

0.3 — — — — — — 300 -0.16 207

1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51

2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25

9.6 9.615 0.16 25 9615 -0.16 12 — — —

19.2 19.231 0.16 12 — — — — — —

57.6 62.500 8.51 3 — — — — — —

115.2 125.000 8.51 1 — — — — — —


PIC18F6585/8585/6680/8680

BAUDRATE

(K)

SYNC = 0, BRGH = 0, BRG16 = 1


Actual Rate (K)

%Error

SPBRGvalue

(decimal)

Actual Rate (K)

%Error

SPBRGvalue

(decimal)

Actual Rate (K)

%Error

SPBRGvalue

(decimal)

Actual Rate (K)

%Error

SPBRGvalue

(decimal)

0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 300 -0.04 1665

1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1201 -0.16 415

2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2403 -0.16 207

9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51

19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25

57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8

115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —

BAUDRATE

(K)

SYNC = 0, BRGH = 0, BRG16 = 1


Actual Rate (K)

%Error

SPBRGvalue

(decimal)

Actual Rate (K)

%Error

SPBRGvalue

(decimal)

Actual Rate (K)

%Error

SPBRGvalue

(decimal)

0.3 0.300 0.04 832 300 -0.16 415 300 -0.16 207

1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51

2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25

9.6 9.615 0.16 25 9615 -0.16 12 — — —

19.2 19.231 0.16 12 — — — — — —

57.6 62.500 8.51 3 — — — — — —

115.2 125.000 8.51 1 — — — — — —

BAUDRATE

(K)

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1


Actual Rate (K)

%Error

SPBRGvalue

(decimal)

Actual Rate (K)

%Error

SPBRGvalue

(decimal)

Actual Rate (K)

%Error

SPBRGvalue

(decimal)

Actual Rate (K)

%Error

SPBRGvalue

(decimal)

0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 300 -0.01 6665

1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1200 -0.04 1665

2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2400 -0.04 832

9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9615 -0.16 207

19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19230 -0.16 103

57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57142 0.79 34

115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117647 -2.12 16

BAUDRATE

(K)

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1


Actual Rate (K)

%Error

SPBRGvalue

(decimal)

Actual Rate (K)

%Error

SPBRGvalue

(decimal)

Actual Rate (K)

%Error

SPBRGvalue

(decimal)

0.3 0.300 0.01 3332 300 -0.04 1665 300 -0.04 832

1.2 1.200 0.04 832 1201 -0.16 415 1201 -0.16 207

2.4 2.404 0.16 415 2403 -0.16 207 2403 -0.16 103

9.6 9.615 0.16 103 9615 -0.16 51 9615 -0.16 25

19.2 19.231 0.16 51 19230 -0.16 25 19230 -0.16 12

57.6 58.824 2.12 16 55555 3.55 8 — — —

115.2 111.111 -3.55 8 — — — — — —

TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)


PIC18F6585/8585/6680/8680

18.1.2 AUTO-BAUD RATE DETECT

The enhanced USART module supports the automaticdetection and calibration of baud rate. This feature isactive only in Asynchronous mode and while the WUEbit is clear.

The automatic baud rate measurement sequence(Figure 18-1) begins whenever a Start bit is receivedand the ABDEN bit is set. The calculation isself-averaging.

In the Auto-Baud Rate Detect (ABD) mode, the clock tothe BRG is reversed. Rather than the BRG clocking theincoming RX signal, the RX signal is timing the BRG. InABD mode, the internal Baud Rate Generator is usedas a counter to time the bit period of the incoming serialbyte stream.

Once the ABDEN bit is set, the state machine will clearthe BRG and look for a Start bit. The auto-baud detectmust receive a byte with the value 55h (ASCII “U”,which is also the LIN bus sync character) in order tocalculate the proper bit rate. The measurement is takenover both a low and a high bit time in order to minimizeany effects caused by asymmetry of the incomingsignal. After a Start bit, the SPBRG begins counting upusing the preselected clock source on the first risingedge of RX. After eight bits on the RX pin or the fifthrising edge, an accumulated value totalling the properBRG period is left in the SPBRGH:SPBRG registers.Once the 5th edge is seen (should correspond to theStop bit), the ABDEN bit is automatically cleared.

While calibrating the baud rate period, the BRG regis-ters are clocked at 1/8th the preconfigured clock rate.Note that the BRG clock will be configured by theBRG16 and BRGH bits. Independent of the BRG16 bitsetting, both the SPBRG and SPBRGH will be used asa 16-bit counter. This allows the user to verify that no

carry occurred for 8-bit modes by checking for 00h inthe SPBRGH register. Refer to Table 18-4 for counterclock rates to the BRG.

While the ABD sequence takes place, the USART statemachine is held in Idle. The RCIF interrupt is set oncethe fifth rising edge on RX is detected. The value in theRCREG needs to be read to clear the RCIF interrupt.RCREG content should be discarded.

TABLE 18-4: BRG COUNTER CLOCK RATES

FIGURE 18-1: AUTOMATIC BAUD RATE CALCULATION

Note 1: If the WUE bit is set with the ABDEN bit,auto-baud rate detection will occur on thebyte following the break character.

2: It is up to the user to determine that theincoming character baud rate is within therange of the selected BRG clock source.Some combinations of oscillator fre-quency and USART baud rates are notpossible due to bit error rates. Overallsystem timing and communication baudrates must be taken into considerationwhen using the auto-baud rate detectionfeature.

BRG16 BRGH BRG Counter Clock

0 0 FOSC/512

0 1 FOSC/128

1 0 FOSC/128

1 1 FOSC/32

Note: During the ABD sequence, SPBRG andSPBRGH are both used as a 16-bitcounter independent of BRG16 setting.

BRG Value

RX pin

ABDEN bit

RCIF bit

Bit 0 Bit 1

(Interrupt)

ReadRCREG

BRG Clock

Start

Auto-ClearedSet by User

XXXXh 0000h

Edge #1

Bit 2 Bit 3Edge #2

Bit 4 Bit 5Edge #3

Bit 6 Bit 7Edge #4

Stop Bit

Edge #5

001Ch

Note 1: The ABD sequence requires the USART module to be configured in Asynchronous mode and WUE = 0.

SPBRG XXXXh 1Ch

SPBRGH XXXXh 00h


PIC18F6585/8585/6680/8680

18.2 USART Asynchronous Mode

The Asynchronous mode of operation is selected byclearing the SYNC bit (TXSTA<4>). In this mode, theUSART uses standard Non-Return-to-Zero (NRZ) for-mat (one Start bit, eight or nine data bits and one Stopbit). The most common data format is 8 bits. An on-chipdedicated 8-bit/16-bit Baud Rate Generator can beused to derive standard baud rate frequencies from theoscillator.

The USART transmits and receives the LSb first. TheUSART’s transmitter and receiver are functionally inde-pendent but use the same data format and baud rate.The Baud Rate Generator produces a clock, either x16or x64 of the bit shift rate depending on the BRGH andBRG16 bits (TXSTA<2> and BAUDCON<3>). Parity isnot supported by the hardware but can be implementedin software and stored as the 9th data bit.

Asynchronous mode is available in all low-powermodes; it is available in Sleep mode only when auto-wake-up on sync break is enabled. When in PRI_IDLEmode, no changes to the Baud Rate Generator valuesare required; however, other low-power mode clocksmay operate at another frequency than the primaryclock. Therefore, the Baud Rate Generator values mayneed to be adjusted.

When operating in Asynchronous mode, the USARTmodule consists of the following important elements:

• Baud Rate Generator• Sampling Circuit

• Asynchronous Transmitter• Asynchronous Receiver• Auto-Wake-up on Sync Break Character

• 12-bit Break Character Transmit• Auto-Baud Rate Detection

18.2.1 USART ASYNCHRONOUS TRANSMITTER

The USART transmitter block diagram is shown inFigure 18-2. The heart of the transmitter is the Transmit(Serial) Shift register (TSR). The Shift register obtainsits data from the read/write transmit buffer, TXREG. TheTXREG register is loaded with data in software. TheTSR register is not loaded until the Stop bit has beentransmitted from the previous load. As soon as the Stopbit is transmitted, the TSR is loaded with new data fromthe TXREG register (if available).

Once the TXREG register transfers the data to the TSRregister (occurs in one TCY), the TXREG register isempty and flag bit TXIF (PIR1<4>) is set. This interruptcan be enabled/disabled by setting/clearing enable bitTXIE (PIE1<4>). Flag bit TXIF will be set regardless ofthe state of enable bit TXIE and cannot be cleared insoftware. Flag bit TXIF is not cleared immediately uponloading the Transmit Buffer register, TXREG. TXIFbecomes valid in the second instruction cycle followingthe load instruction. Polling TXIF immediately followinga load of TXREG will return invalid results.

While flag bit TXIF indicates the status of the TXREGregister, another bit, TRMT (TXSTA<1>), shows thestatus of the TSR register. Status bit TRMT is a read-only bit which is set when the TSR register is empty. Nointerrupt logic is tied to this bit, so the user has to pollthis bit in order to determine if the TSR register isempty.

To set up an Asynchronous Transmission:

1. Initialize the SPBRGH:SPBRG registers for theappropriate baud rate. Set or clear the BRGHand BRG16 bits, as required, to achieve thedesired baud rate.

2. Enable the asynchronous serial port by clearingbit SYNC and setting bit SPEN.

3. If interrupts are desired, set enable bit TXIE.4. If 9-bit transmission is desired, set transmit bit

TX9. Can be used as address/data bit.5. Enable the transmission by setting bit TXEN

which will also set bit TXIF.6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.7. Load data to the TXREG register (starts

transmission).

If using interrupts, ensure that the GIE and PEIE bits inthe INTCON register (INTCON<7:6>) are set.

Note 1: The TSR register is not mapped in datamemory so it is not available to the user.

2: Flag bit TXIF is set when enable bit TXENis set.

Note: When BRGH and BRG16 bits are set,SPBRGH:SPBRG must be more than ‘1’.

PIC18F6585/8585/6680/8680

FIGURE 18-2: USART TRANSMIT BLOCK DIAGRAM

FIGURE 18-3: ASYNCHRONOUS TRANSMISSION

FIGURE 18-4: ASYNCHRONOUS TRANSMISSION (BACK TO BACK)

TXIFTXIE

Interrupt

TXEN Baud Rate CLK

SPBRG

Baud Rate GeneratorTX9D

MSb LSb

Data Bus

TXREG Register

TSR Register

(8) 0

TX9

TRMT SPEN

RC6/TX/CK pin

Pin Bufferand Control

8

• • •

SPBRGHBRG16

Word 1

Word 1Transmit Shift Reg

Start bit bit 0 bit 1 bit 7/8

Write to TXREGWord 1

BRG Output(Shift Clock)

RC6/TX/CK

TXIF bit(Transmit Buffer

Reg. Empty Flag)

TRMT bit(Transmit Shift

Reg. Empty Flag)

1 TCY

(pin) Stop bit

Transmit Shift Reg.

Write to TXREG


RC6/TX/CK

TXIF bit(Interrupt Reg. Flag)


Reg. Empty Flag)

Word 1 Word 2

Word 1 Word 2

Stop bit Start bit

Transmit Shift Reg.

Word 1 Word 2bit 0 bit 1 bit 7/8 bit 0

Note: This timing diagram shows two consecutive transmissions.

1 TCY

1 TCY

(pin) Start bit


PIC18F6585/8585/6680/8680

TABLE 18-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION


POR, BOR







TXREG USART Transmit Register 0000 0000 0000 0000





Legend: x = unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.


PIC18F6585/8585/6680/8680

18.2.2 USART ASYNCHRONOUS RECEIVER

The receiver block diagram is shown in Figure 18-5.The data is received on the RC7/RX/DT pin and drivesthe data recovery block. The data recovery block isactually a high-speed shifter operating at x16 times thebaud rate, whereas the main receive serial shifter oper-ates at the bit rate or at FOSC. This mode wouldtypically be used in RS-232 systems.

To set up an asynchronous reception:



3. If interrupts are desired, set enable bit RCIE.4. If 9-bit reception is desired, set bit RX9.5. Enable the reception by setting bit CREN.

6. Flag bit RCIF will be set when reception is com-plete and an interrupt will be generated if enablebit RCIE was set.

7. Read the RCSTA register to get the 9th bit (ifenabled) and determine if any error occurredduring reception.

8. Read the 8-bit received data by reading theRCREG register.

9. If any error occurred, clear the error by clearingenable bit CREN.

10. If using interrupts, ensure that the GIE and PEIEbits in the INTCON register (INTCON<7:6>) areset.

18.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT

This mode would typically be used in RS-485 systems.To set up an asynchronous reception with addressdetect enable:

1. Initialize the SPBRGH:SPBRG registers for theappropriate baud rate. Set or clear the BRGHand BRG16 bits, as required, to achieve thedesired baud rate..

2. Enable the asynchronous serial port by clearingthe SYNC bit and setting the SPEN bit.

3. If interrupts are required, set the RCEN bit andselect the desired priority level with the RCIP bit.

4. Set the RX9 bit to enable 9-bit reception. 5. Set the ADDEN bit to enable address detect.

6. Enable reception by setting the CREN bit.7. The RCIF bit will be set when reception is com-

plete. The interrupt will be Acknowledged if theRCIE and GIE bits are set.

8. Read the RCSTA register to determine if anyerror occurred during reception, as well as readbit 9 of data (if applicable).

9. Read RCREG to determine if the device is beingaddressed.

10. If any error occurred, clear the CREN bit.

11. If the device has been addressed, clear theADDEN bit to allow all received data into thereceive buffer and interrupt the CPU.

FIGURE 18-5: USART RECEIVE BLOCK DIAGRAM

Note: When BRGH and BRG16 bits are set,SPBRGH:SPBRG must be more than ‘1’.

x64 Baud Rate CLK

Baud Rate Generator

RC7/RX/DT

Pin Bufferand Control

SPEN

DataRecovery

CREN OERR FERR

RSR RegisterMSb LSb

RX9D RCREG RegisterFIFO

Interrupt RCIF

RCIE

Data Bus

8

÷ 64

÷ 16or

Stop Start(8) 7 1 0

RX9

• • •SPBRGSPBRGHBRG16

or÷ 4

PIC18F6585/8585/6680/8680

To set up an asynchronous transmission:

1. Initialize the SPBRG register for the appropriatebaud rate. If a high-speed baud rate is desired,set bit BRGH (see Section 18.1 “USART BaudRate Generator (BRG)”).


3. If interrupts are desired, set enable bit TXIE.

4. If 9-bit transmission is desired, set transmit bitTX9. Can be used as address/data bit.

5. Enable the transmission by setting bit TXENwhich will also set bit TXIF.

6. If 9-bit transmission is selected, the ninth bitshould be loaded in bit TX9D.

7. Load data to the TXREG register (startstransmission).

If using interrupts, ensure that the GIE and PEIE bits inthe INTCON register (INTCON<7:6>) are set.

FIGURE 18-6: ASYNCHRONOUS RECEPTION

TABLE 18-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Startbit bit 7/8bit 1bit 0 bit 7/8 bit 0Stop

bit

Startbit

Startbitbit 7/8 Stop

bitRX (pin)

RegRcv Buffer Reg

Rcv Shift

Read RcvBuffer RegRCREG

RCIF(Interrupt Flag)

OERR bit

CREN

Word 1RCREG

Word 2RCREG

Stopbit

Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word causingthe OERR (overrun) bit to be set.


POR, BOR







RCREG USART Receive Register 0000 0000 0000 0000





Legend: x = unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.

PIC18F6585/8585/6680/8680

18.2.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER

During Sleep mode, all clocks to the USART aresuspended. Because of this, the Baud Rate Generatoris inactive and a proper byte reception cannot be per-formed. The auto-wake-up feature allows the controllerto wake-up due to activity on the RX/DT line while theUSART is operating in Asynchronous mode.

The auto-wake-up feature is enabled by setting theWUE bit (BAUDCON<1>). Once set, the typical receivesequence on RX/DT is disabled and the USARTremains in an Idle state monitoring for a wake-up eventindependent of the CPU mode. A wake-up event con-sists of a high-to-low transition on the RX/DT line. (Thiscoincides with the start of a sync break or a wake-upsignal character for the LIN protocol.)

Following a wake-up event, the module generates anRCIF interrupt. The interrupt is generated synchro-nously to the Q clocks in normal operating modes(Figure 18-7) and asynchronously, if the device is inSleep mode (Figure 18-8). The interrupt condition iscleared by reading the RCREG register.

The WUE bit is automatically cleared once a low-to-high transition is observed on the RX line following thewake-up event. At this point, the USART module is inIdle mode and returns to normal operation. This signalsto the user that the sync break event is over.

18.2.4.1 Special Considerations Using Auto-Wake-up

Since auto-wake-up functions by sensing rising edgetransitions on RX/DT, information with any state changesbefore the Stop bit may signal a false end-of-character

and cause data or framing errors. To work properly,therefore, the initial character in the transmission mustbe all ‘0’s. This can be 00h (8 bytes) for standard RS-232devices or 000h (12 bits) for LIN bus.

Oscillator start-up time must also be considered,especially in applications using oscillators with longerstart-up intervals (i.e., XT or HS mode). The sync break(or wake-up signal) character must be of sufficientlength and be followed by a sufficient interval to allowenough time for the selected oscillator to start andprovide proper initialization of the USART.

18.2.4.2 Special Considerations Using the WUE Bit

The timing of WUE and RCIF events may cause someconfusion when it comes to determining the validity ofreceived data. As noted, setting the WUE bit places theUSART in an Idle mode. The wake-up event causes areceive interrupt by setting the RCIF bit. The WUE bitis cleared after this when a rising edge is seen onRX/DT. The interrupt condition is then cleared by read-ing the RCREG register. Ordinarily, the data in RCREGwill be dummy data and should be discarded.

The fact that the WUE bit has been cleared (or is stillset) and the RCIF flag is set should not be used as anindicator of the integrity of the data in RCREG. Usersshould consider implementing a parallel method infirmware to verify received data integrity.

To assure that no actual data is lost, check the RCIDLbit to verify that a receive operation is not in process. Ifa receive operation is not occurring, the WUE bit maythen be set just prior to entering the Sleep mode.

FIGURE 18-7: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION

FIGURE 18-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

WUE bit

RX/DT Line

RCIF

Cleared due to User Read of RCREG

Note: The USART remains in Idle while the WUE bit is set.

Auto-ClearedBit Set by User

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

WUE bit

RX/DT Line

RCIF

Cleared due to User Read of RCREGSleep Command Executed

Note 1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur while the stposc signal is still active.This sequence should not depend on the presence of Q clocks.

2: The USART remains in Idle while the WUE bit is set.

Sleep Ends

Auto-Cleared

Note 1

Bit Set by User

PIC18F6585/8585/6680/8680

18.2.5 BREAK CHARACTER SEQUENCE

The enhanced USART module has the capability ofsending the special break character sequences thatare required by the LIN bus standard. The break char-acter transmit consists of a Start bit, followed by twelve‘0’ bits and a Stop bit. The frame break character is sentwhenever the SENDB and TXEN bits (TXSTA<3> andTXSTA<5>) are set while the Transmit Shift register isloaded with data. Note that the value of data written toTXREG will be ignored and all ‘0’s will be transmitted.

The SENDB bit is automatically reset by hardware afterthe corresponding Stop bit is sent. This allows the userto preload the transmit FIFO with the next transmit bytefollowing the break character (typically, the synccharacter in the LIN specification).

Note that the data value written to the TXREG for thebreak character is ignored. The write simply serves thepurpose of initiating the proper sequence.

The TRMT bit indicates when the transmit operation isactive or Idle, just as it does during normal transmis-sion. See Figure 18-9 for the timing of the breakcharacter sequence.

18.2.5.1 Break and Sync Transmit Sequence

The following sequence will send a message frameheader made up of a break, followed by an auto-baudsync byte. This sequence is typical of a LIN bus master.

1. Configure the USART for the desired mode.2. Set the TXEN and SENDB bits to set up the

break character.3. Load the TXREG with a dummy character to

initiate transmission (the value is ignored).4. Write ‘55h’ to TXREG to load the sync character

into the transmit FIFO buffer.5. After the break has been sent, the SENDB bit is

reset by hardware. The sync character nowtransmits in the preconfigured mode.

When the TXREG becomes empty, as indicated by theTXIF, the next data byte can be written to TXREG.

18.2.6 RECEIVING A BREAK CHARACTER

The enhanced USART module can receive a breakcharacter in two ways.

The first method forces the configuration of the baudrate at a frequency of 9/13 the typical speed. Thisallows for the Stop bit transition to be at the correctsampling location (13 bits for break versus Start bit and8 data bits for typical data).

The second method uses the auto-wake-up featuredescribed in Section 18.2.4 “Auto-Wake-up on SyncBreak Character”. By enabling this feature, theUSART will sample the next two transitions on RX/DT,cause an RCIF interrupt, and receive the next data bytefollowed by another interrupt.

Note that following a break character, the user will typ-ically want to enable the auto-baud rate detect feature.For both methods, the user can set the ABD bit oncethe TXIF interrupt is observed.

FIGURE 18-9: SEND BREAK CHARACTER SEQUENCE

Write to TXREG


Start Bit Bit 0 Bit 1 Bit 11 Stop Bit

Break

TXIF bit(Transmit Buffer

Reg. Empty Flag)

TX (pin)


Reg. Empty Flag)

SENDB(Transmit Shift

Reg. Empty Flag)

SENDB Sampled Here Auto-Cleared

Dummy Write

PIC18F6585/8585/6680/8680

18.3 USART Synchronous Master Mode

The Synchronous Master mode is entered by settingthe CSRC bit (TXSTA<7>). In this mode, the data istransmitted in a half-duplex manner (i.e., transmissionand reception do not occur at the same time). Whentransmitting data, the reception is inhibited and viceversa. Synchronous mode is entered by setting bitSYNC (TXSTA<4>). In addition, enable bit, SPEN(RCSTA<7>), is set in order to configure theRC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) andDT (data) lines, respectively.

The Master mode indicates that the processor trans-mits the master clock on the CK line. Clock polarity isselected with the SCKP bit (BAUDCON<5>); settingSCKP sets the Idle state on CK as high, while clearingthe bit sets the Idle state as low. This option is providedto support Microwire devices with this module.

18.3.1 USART SYNCHRONOUS MASTER TRANSMISSION

The USART transmitter block diagram is shown inFigure 18-2. The heart of the transmitter is the Transmit(Serial) Shift Register (TSR). The Shift register obtainsits data from the Read/Write Transmit Buffer register,TXREG. The TXREG register is loaded with data insoftware. The TSR register is not loaded until the lastbit has been transmitted from the previous load. Assoon as the last bit is transmitted, the TSR is loadedwith new data from the TXREG (if available).

Once the TXREG register transfers the data to the TSRregister (occurs in one TCYCLE), the TXREG is emptyand interrupt bit TXIF (PIR1<4>) is set. The interruptcan be enabled/disabled by setting/clearing enable bit,TXIE (PIE1<4>). Flag bit TXIF will be set regardless ofthe state of enable bit TXIE and cannot be cleared insoftware. It will reset only when new data is loaded intothe TXREG register.

While flag bit TXIF indicates the status of the TXREGregister, another bit, TRMT (TXSTA<1>), shows the sta-tus of the TSR register. TRMT is a read-only bit which isset when the TSR is empty. No interrupt logic is tied tothis bit so the user must poll this bit in order to determineif the TSR register is empty. The TSR is not mapped indata memory so it is not available to the user.

To set up a synchronous master transmission:


2. Enable the synchronous master serial port bysetting bits SYNC, SPEN and CSRC.

3. If interrupts are desired, set enable bit TXIE.4. If 9-bit transmission is desired, set bit TX9.

5. Enable the transmission by setting bit TXEN.6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.7. Start transmission by loading data to the TXREG

register.8. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) areset.

FIGURE 18-10: SYNCHRONOUS TRANSMISSION

bit 0 bit 1 bit 7

Word 1

Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3Q4 Q1 Q2Q3Q4 Q1 Q2Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

bit 2 bit 0 bit 1 bit 7RC7/RX/DT

RC6/TX/CK

Write toTXREG Reg

TXIF bit(Interrupt Flag)

TXEN bit‘1’ ‘1’

Word 2

TRMT bit

Write Word 1 Write Word 2

Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.

pin

pin

RC6/TX/CKpin

(SCKP = 0)

(SCKP = 1)

PIC18F6585/8585/6680/8680

FIGURE 18-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

TABLE 18-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

RC7/RX/DT pin

RC6/TX/CK pin

Write toTXREG Reg

TXIF bit

TRMT bit

bit 0 bit 1 bit 2 bit 6 bit 7

TXEN bit


POR, BOR












Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.


PIC18F6585/8585/6680/8680

18.3.2 USART SYNCHRONOUS MASTER RECEPTION

Once Synchronous mode is selected, reception isenabled by setting either the Single Receive Enable bit,SREN (RCSTA<5>), or the Continuous ReceiveEnable bit, CREN (RCSTA<4>). Data is sampled on theRC7/RX/DT pin on the falling edge of the clock.

If enable bit SREN is set, only a single word is received.If enable bit CREN is set, the reception is continuousuntil CREN is cleared. If both bits are set, then CRENtakes precedence.

To set up a synchronous master reception:


2. Enable the synchronous master serial port bysetting bits SYNC, SPEN and CSRC.

3. Ensure bits CREN and SREN are clear.4. If interrupts are desired, set enable bit RCIE.

5. If 9-bit reception is desired, set bit RX9.6. If a single reception is required, set bit SREN.

For continuous reception, set bit CREN.7. Interrupt flag bit RCIF will be set when reception

is complete and an interrupt will be generated ifthe enable bit RCIE was set.



10. If any error occurred, clear the error by clearingbit CREN.


FIGURE 18-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION


POR, BOR












Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.

CREN bit

RC7/RX/DT pin

RC7/TX/CK pin

Write tobit SREN

SREN bit

RCIF bit(Interrupt)

ReadRXREG

Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

‘0’

bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7

‘0’

Q1 Q2 Q3 Q4

Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.

RC7/TX/CK pin

(SCKP = 0)

(SCKP = 1)

PIC18F6585/8585/6680/8680

18.4 USART Synchronous Slave Mode

Synchronous Slave mode is entered by clearing bitCSRC (TXSTA<7>). This mode differs from theSynchronous Master mode in that the shift clock is sup-plied externally at the RC6/TX/CK pin (instead of beingsupplied internally in Master mode). This allows thedevice to transfer or receive data while in any low-powermode.

18.4.1 USART SYNCHRONOUS SLAVE TRANSMIT

The operation of the Synchronous Master and Slavemodes are identical except in the case of the Sleepmode.

If two words are written to the TXREG and then theSLEEP instruction is executed, the following will occur:

a) The first word will immediately transfer to theTSR register and transmit.

b) The second word will remain in TXREG register.

c) Flag bit TXIF will not be set. d) When the first word has been shifted out of TSR,

the TXREG register will transfer the second wordto the TSR and flag bit TXIF will now be set.

e) If enable bit TXIE is set, the interrupt will wakethe chip from Sleep. If the global interrupt isenabled, the program will branch to the interruptvector.

To set up a synchronous slave transmission:

1. Enable the synchronous slave serial port bysetting bits SYNC and SPEN and clearing bitCSRC.

2. Clear bits CREN and SREN.3. If interrupts are desired, set enable bit TXIE.4. If 9-bit transmission is desired, set bit TX9.

5. Enable the transmission by setting enable bitTXEN.

6. If 9-bit transmission is selected, the ninth bitshould be loaded in bit TX9D.

7. Start transmission by loading data to the TXREGregister.


TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION


POR, BOR












Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.

PIC18F6585/8585/6680/8680

18.4.2 USART SYNCHRONOUS SLAVE RECEPTION

The operation of the Synchronous Master and Slavemodes is identical, except in the case of Sleep or anyIdle mode and bit SREN, which is a “don’t care” inSlave mode.

If receive is enabled by setting the CREN bit prior toentering Sleep or any Idle mode, then a word may bereceived while in this low-power mode. Once the wordis received, the RSR register will transfer the data to theRCREG register; if the RCIE enable bit is set, the inter-rupt generated will wake the chip from low-powermode. If the global interrupt is enabled, the program willbranch to the interrupt vector.

To set up a synchronous slave reception:

1. Enable the synchronous master serial port bysetting bits SYNC and SPEN and clearing bitCSRC.

2. If interrupts are desired, set enable bit RCIE.3. If 9-bit reception is desired, set bit RX9.4. To enable reception, set enable bit CREN.

5. Flag bit RCIF will be set when reception iscomplete. An interrupt will be generated ifenable bit RCIE was set.



8. If any error occurred, clear the error by clearingbit CREN.


TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION


POR, BOR












Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.


PIC18F6585/8585/6680/8680

19.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE

The Analog-to-Digital (A/D) converter module has 12inputs for the PIC18F6X8X devices and 16 inputs forthe PIC18F8X8X devices. This module allows conver-sion of an analog input signal to a corresponding 10-bitdigital number.

A new feature for the A/D converter is the addition of pro-grammable acquisition time. This feature allows the userto select a new channel for conversion and to set theGO/DONE bit immediately. When the GO/DONE bit isset, the selected channel is sampled for theprogrammed acquisition time before a conversion isactually started. This removes the firmware overheadthat may have been required to allow for an acquisition(sampling) period (see Register 19-3 and Section 19.4“Selecting the A/D Conversion Clock”).

The module has five registers:

• A/D Result High Register (ADRESH)• A/D Result Low Register (ADRESL)

• A/D Control Register 0 (ADCON0)• A/D Control Register 1 (ADCON1)• A/D Control Register 2 (ADCON2)

The ADCON0 register, shown in Register 19-1,controls the operation of the A/D module. TheADCON1 register, shown in Register 19-2, configuresthe functions of the port pins. The ADCON2 register,shown in Register 19-3, configures the A/D clocksource, programmed acquisition time and justification.

REGISTER 19-1: ADCON0 REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON

bit 7 bit 0


bit 5-2 CHS3:CHS0: Analog Channel Select bits

0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Channel 5 (AN5) 0110 = Channel 6 (AN6)0111 = Channel 7 (AN7)1000 = Channel 8 (AN8)1001 = Channel 9 (AN9)1010 = Channel 10 (AN10)1011 = Channel 11 (AN11)1100 = Channel 12 (AN12)(1)

1101 = Channel 13 (AN13)(1)

1110 = Channel 14 (AN14)(1)

1111 = Channel 15 (AN15)(1)

bit 1 GO/DONE: A/D Conversion Status bit

When ADON = 1: 1 = A/D conversion in progress. This bit is automatically cleared when the A/D conversion is

complete.0 = A/D Idle

bit 0 ADON: A/D On bit

1 = A/D converter module is enabled0 = A/D converter module is disabled and consumes no current

Note 1: These channels are only available on PIC18F8X8X devices.

Legend:




PIC18F6585/8585/6680/8680

REGISTER 19-2: ADCON1 REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0

bit 7 bit 0


bit 5-4 VCFG1:VCFG0: Voltage Reference Configuration bits

bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits

Legend:



Note: Channels AN15 through AN12 are not available on the 68-pin devices.

A/D VREF+ A/D VREF-

00 AVDD AVSS

01 External VREF+ AVSS

10 AVDD External VREF-

11 External VREF+ External VREF-

A = Analog input D = Digital I/O Shaded cells = Additional channels available on the PIC18F8X8X devices

AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0

0000 A A A A A A A A A A A A A A A A

0001 D D A A A A A A A A A A A A A A

0010 D D D A A A A A A A A A A A A A

0011 D D D D A A A A A A A A A A A A

0100 D D D D D A A A A A A A A A A A

0101 D D D D D D A A A A A A A A A A

0110 D D D D D D D A A A A A A A A A

0111 D D D D D D D D A A A A A A A A

1000 D D D D D D D D D A A A A A A A

1001 D D D D D D D D D D A A A A A A

1010 D D D D D D D D D D D A A A A A

1011 D D D D D D D D D D D D A A A A

1100 D D D D D D D D D D D D D A A A

1101 D D D D D D D D D D D D D D A A

1110 D D D D D D D D D D D D D D D A

1111 D D D D D D D D D D D D D D D D


PIC18F6585/8585/6680/8680

REGISTER 19-3: ADCON2 REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0

bit 7 bit 0

bit 7 ADFM: A/D Result Format Select bit1 = Right justified 0 = Left justified


bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits000 = 0 TAD(1)

001 = 2 TAD

010 = 4 TAD

011 = 6 TAD

100 = 8 TAD

101 = 12 TAD

110 = 16 TAD

111 = 20 TAD

bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Select bits000 = FOSC/2001 = FOSC/8 010 = FOSC/32 011 = FRC (clock derived from A/D RC oscillator)(1) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC (clock derived from A/D RC oscillator)(1)

Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) isadded before the A/D clock starts. This allows the SLEEP instruction to be executedbefore starting a conversion.

Legend:




PIC18F6585/8585/6680/8680

The analog reference voltage is software selectable toeither the device’s positive and negative supply voltage(AVDD and AVSS) or the voltage level on the RA3/AN3/VREF+ and RA2/AN2/VREF- pins.

The A/D converter has a unique feature of being ableto operate while the device is in Sleep mode. To oper-ate in Sleep, the A/D conversion clock must be derivedfrom the A/D’s internal RC oscillator.

The output of the sample and hold is the input into theconverter which generates the result via successiveapproximation.

A device Reset forces all registers to their Reset state.This forces the A/D module to be turned off and anyconversion in progress is aborted.

Each port pin associated with the A/D converter can beconfigured as an analog input or as a digital I/O. TheADRESH and ADRESL registers contain the result ofthe A/D conversion. When the A/D conversion is com-plete, the result is loaded into the ADRESH/ADRESLregisters, the GO/DONE bit (ADCON0 register) iscleared and A/D interrupt flag bit ADIF is set. The blockdiagram of the A/D module is shown in Figure 19-1.

FIGURE 19-1: A/D BLOCK DIAGRAM

(Input Voltage)

VAIN

VREF+ReferenceVoltage

VDD

VCFG1:VCFG0

CHS3:CHS0

AN7

AN6

AN5

AN4

AN3

AN2

AN1

AN0

0111

0110

0101

0100

0011

0010

0001

0000

10-bitConverter

VREF-

VSS

A/D

AN15(1)

AN14(1)

AN13(1)

AN12(1)

AN11

AN10

AN9

AN8

1111

1110

1101

1100

1011

1010

1001

1000

Note 1: Channels AN15 through AN12 are not available on the PIC18F6X8X.2: I/O pins have diode protection to VDD and VSS.


PIC18F6585/8585/6680/8680

The value in the ADRESH/ADRESL registers is notmodified for a Power-on Reset. The ADRESH/ADRESL registers will contain unknown data after aPower-on Reset.

After the A/D module has been configured as desired,the selected channel must be acquired before the con-version is started. The analog input channels musthave their corresponding TRIS bits selected as aninput. To determine acquisition time, see Section 19.1“A/D Acquisition Requirements”. After this acquisi-tion time has elapsed, the A/D conversion can bestarted. An acquisition time can be programmed tooccur between setting the GO/DONE bit and the actualstart of the conversion.

The following steps should be followed to do an A/Dconversion:

1. Configure the A/D module:• Configure analog pins, voltage reference and

digital I/O (ADCON1)• Select A/D input channel (ADCON0)• Select A/D acquisition time (ADCON2)

• Select A/D conversion clock (ADCON2)• Turn on A/D module (ADCON0)

2. Configure A/D interrupt (if desired):

• Clear ADIF bit • Set ADIE bit • Set GIE bit

3. Wait the required acquisition time (if required).4. Start conversion:

• Set GO/DONE bit (ADCON0 register)

5. Wait for A/D conversion to complete by either:• Polling for the GO/DONE bit to be cleared

or

• Waiting for the A/D interrupt6. Read A/D Result registers (ADRESH:ADRESL);

clear bit ADIF if required.7. For next conversion, go to step 1 or step 2 as

required. The A/D conversion time per bit isdefined as TAD. A minimum wait of 2 TAD isrequired before next acquisition starts.

FIGURE 19-2: ANALOG INPUT MODEL

VAIN CPIN

Rs ANx

5 pF

VDD

VT = 0.6V

VT = 0.6VILEAKAGE

RIC ≤ 1k

SamplingSwitch

SS RSS

CHOLD = 120 pF

VSS

6V

Sampling Switch

5V4V3V2V

5 6 7 8 9 10 11

(kΩ)

VDD

± 500 nA

Legend: CPIN

VT

ILEAKAGE

RIC

SSCHOLD

= input capacitance

= threshold voltage= leakage current at the pin due to

= interconnect resistance= sampling switch= sample/hold capacitance (from DAC)

various junctions

= sampling switch resistanceRSS


PIC18F6585/8585/6680/8680

19.1 A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,the charge holding capacitor (CHOLD) must be allowedto fully charge to the input channel voltage level. Theanalog input model is shown in Figure 19-2. Thesource impedance (RS) and the internal samplingswitch (RSS) impedance directly affect the timerequired to charge the capacitor CHOLD. The samplingswitch (RSS) impedance varies over the device voltage(VDD). The source impedance affects the offset voltageat the analog input (due to pin leakage current). Themaximum recommended impedance for analogsources is 2.5 kΩ. After the analog input channel isselected (changed), this acquisition must be donebefore the conversion can be started.

To calculate the minimum acquisition time,Equation 19-1 may be used. This equation assumesthat 1/2 LSb error is used (1024 steps for the A/D). The1/2 LSb error is the maximum error allowed for the A/Dto meet its specified resolution.

Example 19-1 shows the calculation of the minimumrequired acquisition time, TACQ. This calculation is basedon the following application system assumptions:

CHOLD = 120 pF Rs = 2.5 kΩ Conversion Error ≤ 1/2 LSb VDD = 5V → Rss = 7 kΩ Temperature = 50°C (system max.) VHOLD = 0V @ time = 0

19.2 A/D VREF+ and VREF- References

If external voltage references are used instead of theinternal AVDD and AVSS sources, the source impedanceof the VREF+ and VREF- voltage sources must be consid-ered. During acquisition, currents supplied by thesesources are insignificant. However, during conversion,the A/D module sinks and sources current through thereference sources. The effect of this current, as specifiedin parameter A50, along with source impedance must beconsidered to meet specified A/D resolution.

EQUATION 19-1: ACQUISITION TIME

EQUATION 19-2: A/D MINIMUM CHARGING TIME

EXAMPLE 19-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME

Note: When the conversion is started, theholding capacitor is disconnected from theinput pin.

Note: When using external voltage referenceswith the A/D converter, the source imped-ance of the external voltage referencesmust be less than 20Ω to obtain the spec-ified A/D resolution. Higher referencesource impedances will increase bothoffset and gain errors. Resistive voltagedividers will not provide a sufficiently lowsource impedance.

To maintain the best possible performancein A/D conversions, external VREF inputsshould be buffered with an operationalamplifier or other low output impedancecircuit.

TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient

= TAMP + TC + TCOFF

VHOLD = (VREF – (VREF/2048)) • (1 – e(-Tc/CHOLD(RIC + RSS + RS))) or TC = -(120 pF)(1 kΩ + RSS + RS) ln(1/2047)

TACQ = TAMP + TC + TCOFF

Temperature coefficient is only required for temperatures > 25°C.

TACQ = 2 µs + TC + [(Temp – 25°C)(0.05 µs/°C)]

TC = -CHOLD (RIC + RSS + RS) ln(1/2047) -120 pF (1 kΩ + 7 kΩ + 2.5 kΩ) ln(0.0004885) -120 pF (10.5 kΩ) ln(0.0004885) -1.26 µs (-7.6241) 9.61 µs

TACQ = 2 µs + 9.61 µs + [(50°C – 25°C)(0.05 µs/°C)] 11.61 µs + 1.25 µs 12.86 µs


PIC18F6585/8585/6680/8680

19.3 Selecting and Configuring Automatic Acquisition Time

The ADCON2 register allows the user to select anacquisition time that occurs each time the GO/DONEbit is set.

When the GO/DONE bit is set, sampling is stopped anda conversion begins. The user is responsible for ensur-ing the required acquisition time has passed betweenselecting the desired input channel and setting theGO/DONE bit. This occurs when the ACQT2:ACQT0bits (ADCON2<5:3>) remain in their Reset state (‘000’)and is compatible with devices that do not offerprogrammable acquisition times.

If desired, the ACQT bits can be set to select a pro-grammable acquisition time for the A/D module. Whenthe GO/DONE bit is set, the A/D module continues tosample the input for the selected acquisition time, thenautomatically begins a conversion. Since the acquisi-tion time is programmed, there may be no need to waitfor an acquisition time between selecting a channel andsetting the GO/DONE bit.

In either case, when the conversion is completed, theGO/DONE bit is cleared, the ADIF flag is set, and theA/D begins sampling the currently selected channelagain. If an acquisition time is programmed, there isnothing to indicate if the acquisition time has ended orif the conversion has begun.

19.4 Selecting the A/D Conversion Clock

The A/D conversion time per bit is defined as TAD. TheA/D conversion requires 11 TAD per 10-bit conversion.The source of the A/D conversion clock is softwareselectable. There are seven possible options for TAD:

For correct A/D conversions, the A/D conversion clock(TAD) must be as short as possible but greater than theminimum TAD (approximately 2 µs, see parameter 130for more information).

Table 19-1 shows the resultant TAD times derived fromthe device operating frequencies and the A/D clocksource selected.

19.5 Configuring Analog Port Pins

The ADCON1, TRISA, TRISF and TRISH registers con-trol the operation of the A/D port pins. The port pinsneeded as analog inputs must have their correspondingTRIS bits set (input). If the TRIS bit is cleared (output),the digital output level (VOH or VOL) will be converted.

The A/D operation is independent of the state of theCHS3:CHS0 bits and the TRIS bits.

TABLE 19-1: TAD vs. DEVICE OPERATING FREQUENCIES

• 2 TOSC • 4 TOSC



• Internal RC Oscillator

Note 1: When reading the port register, all pinsconfigured as analog input channels willread as cleared (a low level). Pins config-ured as digital inputs will convert ananalog input. Analog levels on a digitallyconfigured input will not affect theconversion accuracy.

2: Analog levels on any pin defined as a dig-ital input may cause the input buffer toconsume current out of the device’sspecification limits.

AD Clock Source (TAD) Maximum Device Frequency

Operation ADCS2:ADCS0 PIC18FXX80/XX85 PIC18LFXX80/XX85

2 TOSC 000 1.25 MHz 666 kHz

4 TOSC 100 2.50 MHz 1.33 MHz

8 TOSC 001 5.00 MHz 2.66 MHz

16 TOSC 101 10.0 MHz 5.33 MHz

32 TOSC 010 20.0 MHz 10.65 MHz

64 TOSC 110 40.0 MHz 21.33 MHz

RC(3) x11 1.00 MHz(1) 1.00 MHz(2)

Note 1: The RC source has a typical TAD time of 4 µs.

2: The RC source has a typical TAD time of 6 µs.3: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D

accuracy may be out of specification.

PIC18F6585/8585/6680/8680

19.6 A/D Conversions

Figure 19-3 shows the operation of the A/D converterafter the GO bit has been set and the ACQT2:ACQT0bits are cleared. A conversion is started after the follow-ing instruction to allow entry into Sleep mode before theconversion begins.

Figure 19-4 shows the operation of the A/D converterafter the GO bit has been set, the ACQT2:ACQT0 bitsare set to ‘010’ and selecting a 4 TAD acquisition timebefore the conversion starts.

Clearing the GO/DONE bit during a conversion willabort the current conversion. The A/D Result registerpair will not be updated with the partially completed A/Dconversion sample. This means the ADRESH:ADRESLregisters will continue to contain the value of the lastcompleted conversion (or the last value written to theADRESH:ADRESL registers).

After the A/D conversion is completed or aborted, a2 TAD wait is required before the next acquisition canbe started. After this wait, acquisition on the selectedchannel is automatically started.

19.7 Use of the CCP2 Trigger

An A/D conversion can be started by the “special eventtrigger” of the CCP2 module. This requires that theCCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-grammed as ‘1011’ and that the A/D module is enabled(ADON bit is set). When the trigger occurs, theGO/DONE bit will be set, starting the A/D conversionand the Timer1 (or Timer3) counter will be reset to zero.Timer1 (or Timer3) is reset to automatically repeat theA/D acquisition period with minimal software overhead(moving ADRESH/ADRESL to the desired location).The appropriate analog input channel must be selectedand the minimum acquisition done before the “specialevent trigger” sets the GO/DONE bit (starts aconversion).

If the A/D module is not enabled (ADON is cleared), the“special event trigger” will be ignored by the A/Dmodule but will still reset the Timer1 (or Timer3)counter.

FIGURE 19-3: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)

FIGURE 19-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)

Note: The GO/DONE bit should NOT be set inthe same instruction that turns on the A/D.

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD11

Set GO bit

Holding capacitor is disconnected from analog input (typically 100 ns)

TAD9 TAD10TCY - TAD

Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input.

Conversion starts

b0b9 b6 b5 b4 b3 b2 b1b8 b7

1 2 3 4 5 6 7 8 11

Set GO bit

(Holding capacitor is disconnected)

9 10

Next Q4: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is reconnected to analog input.

Conversion starts

1 2 3 4

(Holding capacitor continuesacquiring input)

TACQT Cycles TAD Cycles

AutomaticAcquisition

Time

b0b9 b6 b5 b4 b3 b2 b1b8 b7

PIC18F6585/8585/6680/8680

TABLE 19-2: SUMMARY OF A/D REGISTERS


POR, BOR









ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu

ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu

ADCON0 — — CHS3 CHS3 CHS1 CHS0 GO/DONE ADON --00 0000 --00 0000


ADCON2 ADFM — — — — ADCS2 ADCS1 ADCS0 0--- -000 0--- -000

PORTA — RA6 RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu

TRISA — PORTA Data Direction Register --11 1111 --11 1111

PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 xxxx xxxx uuuu uuuu

LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx xxxx uuuu uuuu

TRISF PORTF Data Direction Control Register 1111 1111 1111 1111

PORTH(1) RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 xxxx xxxx uuuu uuuu

LATH(1) LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 xxxx xxxx uuuu uuuu

TRISH(1) PORTH Data Direction Control Register 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.Note 1: Only available on PIC18F8X8X devices.


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NOTES:


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20.0 COMPARATOR MODULE

The comparator module contains two analogcomparators. The inputs to the comparators aremultiplexed with the RF1 through RF6 pins. The on-chip voltage reference (Section 21.0 “ComparatorVoltage Reference Module”) can also be an input tothe comparators.

The CMCON register, shown in Register 20-1, controlsthe comparator input and output multiplexers. A blockdiagram of the various comparator configurations isshown in Figure 20-1.

REGISTER 20-1: CMCON REGISTER R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0

bit 7 bit 0

bit 7 C2OUT: Comparator 2 Output bit

When C2INV = 0:1 = C2 VIN+ > C2 VIN-0 = C2 VIN+ < C2 VIN-When C2INV = 1:1 = C2 VIN+ < C2 VIN-0 = C2 VIN+ > C2 VIN-

bit 6 C1OUT: Comparator 1 Output bit

When C1INV = 0:1 = C1 VIN+ > C1 VIN-0 = C1 VIN+ < C1 VIN-When C1INV = 1:1 = C1 VIN+ < C1 VIN-0 = C1 VIN+ > C1 VIN-

bit 5 C2INV: Comparator 2 Output Inversion bit

1 = C2 output inverted0 = C2 output not inverted

bit 4 C1INV: Comparator 1 Output Inversion bit1 = C1 output inverted0 = C1 output not inverted

bit 3 CIS: Comparator Input Switch bitWhen CM2:CM0 = 110:1 = C1 VIN- connects to RF5/AN10

C2 VIN- connects to RF3/AN80 = C1 VIN- connects to RF6/AN11

C2 VIN- connects to RF4/AN9

bit 2-0 CM2:CM0: Comparator Mode bits

Figure 20-1 shows the Comparator modes and CM2:CM0 bit settings.

Legend:

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20.1 Comparator Configuration

There are eight modes of operation for the compara-tors. The CMCON register is used to select thesemodes. Figure 20-1 shows the eight possible modes.The TRISF register controls the data direction of thecomparator pins for each mode. If the Comparator

mode is changed, the comparator output level may notbe valid for the specified mode change delay shown inSection 27.0 “Electrical Characteristics”.

FIGURE 20-1: COMPARATOR I/O OPERATING MODES

Note: Comparator interrupts should be disabledduring a Comparator mode change.Otherwise, a false interrupt may occur.

C1RF6/AN11 VIN-

VIN+RF5/AN10Off (Read as ‘0’)

Comparators Reset (POR Default Value)

A

A

CM2:CM0 = 000

C2RF4/AN9 VIN-


A

A

C1RF6/AN11 VIN-

VIN+RF5/AN10C1OUT

Two Independent Comparators

A

A

CM2:CM0 = 010

C2RF4/AN9 VIN-

VIN+RF3/AN8C2OUT

A

A

C1RF6/AN11 VIN-

VIN+RF5/AN10C1OUT

Two Common Reference Comparators

A

A

CM2:CM0 = 100

C2RF4/AN9 VIN-

VIN+RF3/AN8C2OUT

A

D

C2RF4/AN9 VIN-


One Independent Comparator with Output

D

D

CM2:CM0 = 001

C1RF6/AN11 VIN-

VIN+RF5/AN10C1OUT

A

A

C1RF6/AN11 VIN-


Comparators Off

D

D

CM2:CM0 = 111

C2RF4/AN9 VIN-


D

D

C1

RF6/AN11 VIN-

VIN+RF5/AN10 C1OUT

Four Inputs Multiplexed to Two Comparators

A

A

CM2:CM0 = 110

C2

RF4/AN9 VIN-

VIN+RF3/AN8 C2OUT

A

A

From VREF Module

CIS = 0CIS = 1

CIS = 0CIS = 1

C1RF6/AN11 VIN-

VIN+RF5/AN10C1OUT

Two Common Reference Comparators with Outputs

A

A

CM2:CM0 = 101

C2RF4/AN9 VIN-

VIN+RF3/AN8C2OUT

A

D

A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) = Comparator Input Switch

CVREF

C1RF6/AN11 VIN-

VIN+RF5/AN10C1OUT

Two Independent Comparators with Outputs

A

A

CM2:CM0 = 011

C2RF4/AN9 VIN-

VIN+RF3/AN8C2OUT

A

A

RF2/AN7/C1OUT

RF1/AN6/C2OUT

RF2/AN7/C1OUT

RF1/AN6/C2OUT

RF2/AN7/C1OUT

PIC18F6585/8585/6680/8680

20.2 Comparator Operation

A single comparator is shown in Figure 20-2, along withthe relationship between the analog input levels andthe digital output. When the analog input at VIN+ is lessthan the analog input VIN-, the output of the comparatoris a digital low level. When the analog input at VIN+ isgreater than the analog input VIN-, the output of thecomparator is a digital high level. The shaded areas ofthe output of the comparator in Figure 20-2 representthe uncertainty due to input offsets and response time.

20.3 Comparator Reference

An external or internal reference signal may be useddepending on the Comparator Operating mode. Theanalog signal present at VIN- is compared to the signalat VIN+ and the digital output of the comparator isadjusted accordingly (Figure 20-2).

FIGURE 20-2: SINGLE COMPARATOR

20.3.1 EXTERNAL REFERENCE SIGNAL

When external voltage references are used, thecomparator module can be configured to have the com-parators operate from the same or different referencesources. However, threshold detector applications mayrequire the same reference. The reference signal mustbe between VSS and VDD and can be applied to eitherpin of the comparator(s).

20.3.2 INTERNAL REFERENCE SIGNAL

The comparator module also allows the selection of aninternally generated voltage reference for the compara-tors. Section 21.0 “Comparator Voltage ReferenceModule” contains a detailed description of the compar-ator voltage reference module that provides this signal.The internal reference signal is used when comparatorsare in mode CM<2:0> = 110 (Figure 20-1). In this mode,the internal voltage reference is applied to the VIN+ pinof both comparators.

20.4 Comparator Response Time

Response time is the minimum time, after selecting anew reference voltage or input source, before thecomparator output has a valid level. If the internalreference is changed, the maximum delay of the inter-nal voltage reference must be considered when usingthe comparator outputs. Otherwise, the maximumdelay of the comparators should be used (Section 27.0“Electrical Characteristics”).

20.5 Comparator Outputs

The comparator outputs are read through the CMCONregister. These bits are read-only. The comparatoroutputs may also be directly output to the RF1 and RF2I/O pins. When enabled, multiplexors in the output pathof the RF1 and RF2 pins will switch and the output ofeach pin will be the unsynchronized output of the com-parator. The uncertainty of each of the comparators isrelated to the input offset voltage and the response timegiven in the specifications. Figure 20-3 shows thecomparator output block diagram.

The TRISA bits will still function as an outputenable/disable for the RF1 and RF2 pins while in thismode.

The polarity of the comparator outputs can be changedusing the C2INV and C1INV bits (CMCON<4:5>).

–

+VIN+

VIN-Output

VIN–

VIN+

OutputOutput

VIN+

VIN-

Note 1: When reading the Port register, all pinsconfigured as analog inputs will read as a‘0’. Pins configured as digital inputs willconvert an analog input according to theSchmitt Trigger input specification.

2: Analog levels on any pin defined as a dig-ital input may cause the input buffer toconsume more current than is specified.

PIC18F6585/8585/6680/8680

FIGURE 20-3: COMPARATOR OUTPUT BLOCK DIAGRAM

20.6 Comparator Interrupts

The comparator interrupt flag is set whenever there isa change in the output value of either comparator.Software will need to maintain information about thestatus of the output bits, as read from CMCON<7:6>, todetermine the actual change that occurred. The CMIFbit (PIR registers) is the Comparator Interrupt Flag. TheCMIF bit must be reset by clearing it to ‘0’. Since it isalso possible to write a ‘1’ to this register, a simulatedinterrupt may be initiated.

The CMIE bit (PIE registers) and the PEIE bit (INTCONregister) must be set to enable the interrupt. In addition,the GIE bit must also be set. If any of these bits areclear, the interrupt is not enabled, though the CMIF bitwill still be set if an interrupt condition occurs.

The user, in the Interrupt Service Routine, can clear theinterrupt in the following manner:

a) Any read or write of CMCON will end themismatch condition.

b) Clear flag bit CMIF.

A mismatch condition will continue to set flag bit CMIF.Reading CMCON will end the mismatch condition andallow flag bit CMIF to be cleared.

DQ

EN

To RF1 orRF2 pin

BusData

Read CMCON

Set

MULTIPLEX

CMIFbit

-+

DQ

EN

CL

Port pins

Read CMCON

RESET

FromotherComparator

CxINV

Note: If a change in the CMCON register(C1OUT or C2OUT) should occur when aread operation is being executed (start ofthe Q2 cycle), then the CMIF (PIRregisters) interrupt flag may not get set.

PIC18F6585/8585/6680/8680

20.7 Comparator Operation During Sleep

When a comparator is active and the device is placedin Sleep mode, the comparator remains active and theinterrupt is functional if enabled. This interrupt willwake-up the device from Sleep mode when enabled.While the comparator is powered up, higher Sleepcurrents than shown in the power-down currentspecification will occur. Each operational comparatorwill consume additional current as shown in the com-parator specifications. To minimize power consumptionwhile in Sleep mode, turn off the comparators(CM<2:0> = 111) before entering Sleep. If the devicewakes up from Sleep, the contents of the CMCONregister are not affected.

20.8 Effects of a Reset

A device Reset forces the CMCON register to its Resetstate, causing the comparator module to be in theComparator Reset mode (CM<2:0> = 000). Thisensures that all potential inputs are analog inputs.Device current is minimized when analog inputs arepresent at Reset time. The comparators will bepowered down during the Reset interval.

20.9 Analog Input ConnectionConsiderations

A simplified circuit for an analog input is shown inFigure 20-4. Since the analog pins are connected to adigital output, they have reverse biased diodes to VDD

and VSS. The analog input, therefore, must be betweenVSS and VDD. If the input voltage deviates from thisrange by more than 0.6V in either direction, one of thediodes is forward biased and a latch-up condition mayoccur. A maximum source impedance of 10 kΩ isrecommended for the analog sources. Any externalcomponent connected to an analog input pin, such asa capacitor or a Zener diode, should have very littleleakage current.

FIGURE 20-4: COMPARATOR ANALOG INPUT MODEL

VA

RS < 10k

AIN

CPIN5 pF

VDD

VT = 0.6V

VT = 0.6V

RIC

ILEAKAGE±500 nA

VSS

Legend: CPIN = Input CapacitanceVT = Threshold VoltageILEAKAGE = Leakage Current at the pin due to various junctionsRIC = Interconnect ResistanceRS = Source ImpedanceVA = Analog Voltage

ComparatorInput

PIC18F6585/8585/6680/8680

TABLE 20-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE


POR








PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 xxxx xxxx uuuu uuuu

LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx xxxx uuuu uuuu

TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.


PIC18F6585/8585/6680/8680

21.0 COMPARATOR VOLTAGE REFERENCE MODULE

The comparator voltage reference is a 16-tap resistorladder network that provides a selectable voltagereference. The resistor ladder is segmented to providetwo ranges of CVREF values and has a power-downfunction to conserve power when the reference is notbeing used. The CVRCON register controls theoperation of the reference as shown in Register 21-1.The block diagram is given in Figure 21-1.

The comparator reference supply voltage can comefrom either VDD or VSS, or the external VREF+ andVREF- that are multiplexed with RA3 and RA2. Thecomparator reference supply voltage is controlled bythe CVRSS bit.

21.1 Configuring the Comparator Voltage Reference

The comparator voltage reference can output 16 distinctvoltage levels for each range. The equations used tocalculate the output of the comparator voltage referenceare as follows:

If CVRR = 1: CVREF = (CVR<3:0>/24) x CVRSRC

If CVRR = 0: CVREF = (CVDD x 1/4) + (CVR<3:0>/32) x CVRSRC

The settling time of the comparator voltage referencemust be considered when changing the CVREF output(Section 27.0 “Electrical Characteristics”).

REGISTER 21-1: CVRCON REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0

bit 7 bit 0

bit 7 CVREN: Comparator Voltage Reference Enable bit1 = CVREF circuit powered on 0 = CVREF circuit powered down

bit 6 CVROE: Comparator VREF Output Enable bit(1)

1 = CVREF voltage level is also output on the RF5/AN10/C1IN+/CVREF pin 0 = CVREF voltage is disconnected from the RF5/AN10/C1IN+/CVREF pin

bit 5 CVRR: Comparator VREF Range Selection bit

1 = 0.00 CVRSRC to 0.625 CVRSRC with CVRSRC/24 step size 0 = 0.25 CVRSRC to 0.71875 CVRSRC with CVRSRC/32 step size

bit 4 CVRSS: Comparator VREF Source Selection bit1 = Comparator reference source, CVRSRC = VREF+ – VREF-0 = Comparator reference source, CVRSRC = VDD – VSS

Note: To select (VREF+ – VREF-) as the comparator voltage reference source, the voltagereference configuration bits in the ADCON1 register (ADCON1<5:4>) must also beset to ‘11’.

bit 3-0 CVR3:CVR0: Comparator VREF Value Selection bits (0 ≤ VR3:VR0 ≤ 15) When CVRR = 1: CVREF = (CVR<3:0>/24) • (CVRSRC)When CVRR = 0: CVREF = 1/4 • (CVRSRC) + (CVR3:CVR0/32) • (CVRSRC)

Note 1: If enabled for output, RF5 must also be configured as an input by setting TRISF<5>to ‘1’.

Legend:

PIC18F6585/8585/6680/8680

FIGURE 21-1: VOLTAGE REFERENCE BLOCK DIAGRAM

21.2 Voltage Reference Accuracy/Error

The full range of voltage reference cannot be realizeddue to the construction of the module. The transistorson the top and bottom of the resistor ladder network(Figure 21-1) keep CVREF from approaching the refer-ence source rails. The voltage reference is derivedfrom the reference source; therefore, the CVREF outputchanges with fluctuations in that source. The testedabsolute accuracy of the voltage reference can befound in Section 27.0 “Electrical Characteristics”.

21.3 Operation During Sleep

When the device wakes up from Sleep through aninterrupt or a Watchdog Timer time-out, the contents ofthe CVRCON register are not affected. To minimizecurrent consumption in Sleep mode, the voltagereference should be disabled.


A device Reset disables the voltage reference byclearing bit CVREN (CVRCON<7>). This Reset alsodisconnects the reference from the RA2 pin by clearingbit CVROE (CVRCON<6>) and selects the high-voltage range by clearing bit CVRR (CVRCON<5>).The VRSS value select bits, CVRCON<3:0>, are alsocleared.

21.5 Connection Considerations

The voltage reference module operates independentlyof the comparator module. The output of the referencegenerator may be connected to the RF5 pin if theTRISF<5> bit is set and the CVROE bit is set. Enablingthe voltage reference output onto the RF5 pin with aninput signal present will increase current consumption.Connecting RF5 as a digital output with VRSS enabledwill also increase current consumption.

The RF5 pin can be used as a simple D/A output withlimited drive capability. Due to the limited current drivecapability, a buffer must be used on the voltage refer-ence output for external connections to VREF.Figure 21-2 shows an example buffering technique.

Note: R is defined in Section 27.0 “Electrical Characteristics”.

CVRR8R

CVR3

CVR0(From CVRCON<3:0>)16-1 Analog Mux

8R R R R RCVREN

CVREF

16 StagesCVRSS = 0

VDD VREF+

CVRSS = 0

CVRSS = 1

VREF-

CVRSS = 1

PIC18F6585/8585/6680/8680

FIGURE 21-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

TABLE 21-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE

CVREF Output+–

CVREF

Module

Voltage Reference

Output Impedance

R(1) RF5

Note 1: R is dependent upon the voltage reference configuration bits CVRCON<3:0> and CVRCON<5>.


POR




TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used with the comparator voltage reference.

PIC18F6585/8585/6680/8680

NOTES:


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22.0 LOW-VOLTAGE DETECT

In many applications, the ability to determine if thedevice voltage (VDD) is below a specified voltage levelis a desirable feature. A window of operation for theapplication can be created where the application soft-ware can do “housekeeping tasks” before the devicevoltage exits the valid operating range. This can bedone using the Low-Voltage Detect module.

This module is a software programmable circuitrywhere a device voltage trip point can be specified.When the voltage of the device becomes lower then thespecified point, an interrupt flag is set. If the interrupt isenabled, the program execution will branch to the inter-rupt vector address and the software can then respondto that interrupt source.

The Low-Voltage Detect circuitry is completely undersoftware control. This allows the circuitry to be “turnedoff” by the software which minimizes the currentconsumption for the device.

Figure 22-1 shows a possible application voltage curve(typically for batteries). Over time, the device voltagedecreases. When the device voltage equals voltage VA,the LVD logic generates an interrupt. This occurs attime TA. The application software then has the time,until the device voltage is no longer in valid operatingrange, to shut down the system. Voltage point VB is theminimum valid operating voltage specification. Thisoccurs at time TB. The difference, TB – TA, is the totaltime for shutdown.

FIGURE 22-1: TYPICAL LOW-VOLTAGE DETECT APPLICATION

The block diagram for the LVD module is shown inFigure 22-2. A comparator uses an internally gener-ated reference voltage as the set point. When theselected tap output of the device voltage crosses theset point (is lower than), the LVDIF bit is set.

Each node in the resistor divider represents a “trippoint” voltage. The “trip point” voltage is the minimumsupply voltage level at which the device can operatebefore the LVD module asserts an interrupt. When the

supply voltage is equal to the trip point, the voltagetapped off of the resistor array is equal to the 1.2Vinternal reference voltage generated by the voltagereference module. The comparator then generates aninterrupt signal setting the LVDIF bit. This voltage issoftware programmable to any one of 16 values (seeFigure 22-2). The trip point is selected byprogramming the LVDL3:LVDL0 bits (LVDCON<3:0>).

Time

Volta

ge

VAVB

TA TB

VA = LVD trip pointVB = Minimum valid device operating voltage

Legend:

PIC18F6585/8585/6680/8680

FIGURE 22-2: LOW-VOLTAGE DETECT (LVD) BLOCK DIAGRAM

The LVD module has an additional feature that allowsthe user to supply the trip voltage to the module from anexternal source. This mode is enabled when bitsLVDL3:LVDL0 are set to ‘1111’. In this state, the com-parator input is multiplexed from the external input pin,

LVDIN (Figure 22-3). This gives users flexibilitybecause it allows them to configure the Low-VoltageDetect interrupt to occur at any voltage in the validoperating range.

FIGURE 22-3: LOW-VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM

LVDIF

VDD

16 to

1 M

UX

LVDEN

LVDCON

Internally GeneratedReference Voltage

LVDIN

(Parameter #D423)

LVD3:LVD0Register

LVD

EN

16 to

1 M

UX

BGAP

BODEN

LVDEN

VxEN

LVDIN

VDDVDD

Externally GeneratedTrip Point

LVD3:LVD0 LVDCONRegister


PIC18F6585/8585/6680/8680

22.1 Control Register

The Low-Voltage Detect Control register controls theoperation of the Low-Voltage Detect circuitry.

REGISTER 22-1: LVDCON REGISTER U-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1

— — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0

bit 7 bit 0


bit 5 IRVST: Internal Reference Voltage Stable Flag bit1 = Indicates that the Low-Voltage Detect logic will generate the interrupt flag at the specified

voltage range0 = Indicates that the Low-Voltage Detect logic will not generate the interrupt flag at the

specified voltage range and the LVD interrupt should not be enabled

bit 4 LVDEN: Low-Voltage Detect Power Enable bit1 = Enables LVD, powers up LVD circuit 0 = Disables LVD, powers down LVD circuit

bit 3-0 LVDL3:LVDL0: Low-Voltage Detection Limit bits1111 = External analog input is used (input comes from the LVDIN pin) 1110 = 4.5V-4.77V 1101 = 4.2V-4.45V 1100 = 4.0V-4.24V 1011 = 3.8V-4.03V 1010 = 3.6V-3.82V1001 = 3.5V-3.71V 1000 = 3.3V-3.50V 0111 = 3.0V-3.18V 0110 = 2.8V-2.97V0101 = 2.7V-2.86V 0100 = 2.5V-2.65V 0011 = 2.4V-2.54V 0010 = 2.2V-2.33V 0001 = 2.0V-2.12V 0000 = Reserved

Note: LVDL3:LVDL0 modes which result in a trip point below the valid operating voltageof the device are not tested.

Legend:




PIC18F6585/8585/6680/8680

22.2 Operation

Depending on the power source for the device voltage,the voltage normally decreases relatively slowly. Thismeans that the LVD module does not need to beconstantly operating. To decrease the current require-ments, the LVD circuitry only needs to be enabled forshort periods where the voltage is checked. After doingthe check, the LVD module may be disabled.

Each time that the LVD module is enabled, the circuitryrequires some time to stabilize. After the circuitry hasstabilized, all status flags may be cleared. The modulewill then indicate the proper state of the system.

The following steps are needed to set up the LVDmodule:

1. Write the value to the LVDL3:LVDL0 bits(LVDCON register) which selects the desiredLVD trip point.

2. Ensure that LVD interrupts are disabled (theLVDIE bit is cleared or the GIE bit is cleared).

3. Enable the LVD module (set the LVDEN bit inthe LVDCON register).

4. Wait for the LVD module to stabilize (the IRVSTbit to become set).

5. Clear the LVD interrupt flag which may havefalsely become set until the LVD module hasstabilized (clear the LVDIF bit).

6. Enable the LVD interrupt (set the LVDIE and theGIE bits).

Figure 22-4 shows typical waveforms that the LVDmodule may be used to detect.

FIGURE 22-4: LOW-VOLTAGE DETECT WAVEFORMS

VLVD

VDD

LVDIF

VLVD

VDD

Enable LVD

Internally Generated TIVRST

LVDIF may not be set

Enable LVD

LVDIF

LVDIF cleared in software

LVDIF cleared in software

LVDIF cleared in software,

CASE 1:

CASE 2:

LVDIF remains set since LVD condition still exists

Reference Stable

Internally GeneratedReference Stable

TIVRST


PIC18F6585/8585/6680/8680

22.2.1 REFERENCE VOLTAGE SET POINT

The internal reference voltage of the LVD module,specified in electrical specification parameter #D423,may be used by other internal circuitry (the Program-mable Brown-out Reset). If these circuits are disabled(lower current consumption), the reference voltagecircuit requires a time to become stable before a low-voltage condition can be reliably detected. This time isinvariant of system clock speed. This start-up time isspecified in electrical specification parameter #36. Thelow-voltage interrupt flag will not be enabled until astable reference voltage is reached. Refer to thewaveform in Figure 22-4.

22.2.2 CURRENT CONSUMPTION

When the module is enabled, the LVD comparator andvoltage divider are enabled and will consume static cur-rent. The voltage divider can be tapped from multipleplaces in the resistor array. Total current consumption,when enabled, is specified in electrical specificationparameter #D022B.

22.3 Operation During Sleep

When enabled, the LVD circuitry continues to operateduring Sleep. If the device voltage crosses the trippoint, the LVDIF bit will be set and the device willwake-up from Sleep. Device execution will continuefrom the interrupt vector address if interrupts havebeen globally enabled.


A device Reset forces all registers to their Reset state.This forces the LVD module to be turned off.


PIC18F6585/8585/6680/8680

NOTES:


PIC18F6585/8585/6680/8680

23.0 ECAN MODULE

PIC18F6585/8585/6680/8680 devices contain anEnhanced Controller Area Network (ECAN) module.The ECAN module is fully backward compatible withthe CAN module available in PIC18CXX8 andPIC18FXX8 devices.

The Controller Area Network (CAN) module is a serialinterface which is useful for communicating with otherperipherals or microcontroller devices. This interface,or protocol, was designed to allow communicationswithin noisy environments.

The ECAN module is a communication controller,implementing the CAN 2.0A or B protocol as defined inthe BOSCH specification. The module will supportCAN 1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0BActive versions of the protocol. The module implemen-tation is a full CAN system; however, the CAN specifi-cation is not covered within this data sheet. Refer to theBOSCH CAN specification for further details.

The module features are as follows:

• Implementation of the CAN protocol CAN 1.2, CAN 2.0A and CAN 2.0B

• DeviceNetTM data bytes filter support• Standard and extended data frames• 0-8 bytes data length• Programmable bit rate up to 1 Mbit/sec• Fully backward compatible with PIC18XX8 CAN

module• Three modes of operation:

- Mode 0 – Legacy mode- Mode 1 – Enhanced Legacy mode with

DeviceNet support- Mode 2 – FIFO mode with DeviceNet support

• Support for remote frames with automated handling• Double-buffered receiver with two prioritized

received message storage buffers• Six buffers programmable as RX and TX

message buffers• 16 full (standard/extended identifier) acceptance

filters that can be linked to one of four masks• Two full acceptance filter masks that can be

assigned to any filter• One full acceptance filter that can be used as either

an acceptance filter or acceptance filter mask• Three dedicated transmit buffers with application

specified prioritization and abort capability• Programmable wake-up functionality with

integrated low-pass filter• Programmable Loopback mode supports self-test

operation• Signaling via interrupt capabilities for all CAN

receiver and transmitter error states• Programmable clock source• Programmable link to timer module for

time-stamping and network synchronization• Low-Power Sleep mode

23.1 Module Overview

The CAN bus module consists of a protocol engine andmessage buffering and control. The CAN protocolengine automatically handles all functions for receivingand transmitting messages on the CAN bus. Messagesare transmitted by first loading the appropriate dataregisters. Status and errors can be checked by readingthe appropriate registers. Any message detected onthe CAN bus is checked for errors and then matchedagainst filters to see if it should be received and storedin one of the two receive registers.

The CAN module supports the following frame types:

• Standard Data Frame

• Extended Data Frame• Remote Frame• Error Frame

• Overload Frame Reception• Interframe Space Generation/Detection

The CAN module uses the RG0/CANTX1,RG1/CANTX2 and RG2/CANRX pins to interface withthe CAN bus. In Normal mode, the CAN moduleautomatically overrides the TRISG0 and TRISG1 bitsof the CAN module pins.

23.1.1 MODULE FUNCTIONALITY

The CAN bus module consists of a protocol engine,message buffering and control (see Figure 23-1). Theprotocol engine can best be understood by defining thetypes of data frames to be transmitted and received bythe module.

The following sequence illustrates the necessary initial-ization steps before the ECAN module can be used totransmit or receive a message. Steps can be added orremoved depending on the requirements of theapplication.

1. Ensure that the ECAN module is in Configurationmode.

2. Select ECAN Operational mode.3. Set up the baud rate registers.

4. Set up the filter and mask registers.5. Set the ECAN module to Normal mode or any

other mode required by the application logic.


PIC18F6585/8585/6680/8680

FIGURE 23-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM

MS

GR

EQ

TXB2

AB

TF

MLO

AT

XE

RR

MT

XB

UF

F

ME

SS

AG

E

MessageQueueControl

Transmit Byte Sequencer

MS

GR

EQ

TXB1

AB

TF

MLO

A

TX

ER

RM

TX

BU

FF

ME

SS

AG

E

MS

GR

EQ

TXB0

AB

TF

MLO

AT

XE

RR

MT

XB

UF

F

ME

SS

AG

EAcceptance Filters(RXF0 – RXF05)

Accept

Data Field

Identifier

Acc

epta

nce

Mas

kR

XM

1Acceptance Filters(RXF06 – RXF15)

MAB

Acc

epta

nce

Mas

kR

XM

0

Rcv Byte

16-4 to 1 muxs

PROTOCOL

MESSAGEBUFFERS

Transmit Option

MODE 0

MODE 1, 26 TX/RXBuffers

2 RXBuffers

CRC<14:0>

Comparator

Receive<8:0>Transmit<7:0>

ReceiveError

TransmitError

Protocol

REC

TEC

Err-Pas

Bus-Off

FiniteState

Machine

Counter

Counter

Shift<14:0>Transmit<5:0>, Receive<8:0>

TransmitLogic

BitTimingLogic

TX RXConfiguration

Registers

ClockGenerator

BUFFERS

ENGINE

MODE 0

MODE 1, 2

RXF15

VCC

PIC18F6585/8585/6680/8680

23.2 CAN Module Registers

There are many control and data registers associatedwith the CAN module. For convenience, theirdescriptions have been grouped into the followingsections:

• Control and Status Registers

• Dedicated Transmit Buffer Registers• Dedicated Receive Buffer Registers• Programmable TX/RX and Auto RTR Buffers

• Baud Rate Control Registers• I/O Control Register• Interrupt Status and Control Registers

Detailed descriptions of each register and their usageare described in the following sections.

23.2.1 CAN CONTROL AND STATUS REGISTERS

The registers described in this section control theoverall operation of the CAN module and show itsoperational status.

Note: Not all CAN registers are available in theAccess Bank.


PIC18F6585/8585/6680/8680

REGISTER 23-1: CANCON: CAN CONTROL REGISTER

Mode 0R/W-1 R/W-0 R/W-0 R/S-0 R/W-0 R/W-0 R/W-0 U-0

REQOP2 REQOP1 REQOP0 ABAT WIN2 WIN1 WIN0 —

Mode 1R/W-1 R/W-0 R/W-0 R/S-0 U-0 U-0 U-0 U-0

REQOP2 REQOP1 REQOP0 ABAT — — — —

Mode 2R/W-1 R/W-0 R/W-0 R/S-0 R-0 R-0 R-0 R-0

REQOP2 REQOP1 REQOP0 ABAT FP3 FP2 FP1 FP0

bit 7 bit 0

bit 7-5 REQOP2:REQOP0: Request CAN Operation Mode bits1xx = Request Configuration mode 011 = Request Listen Only mode 010 = Request Loopback mode 001 = Request Disable mode 000 = Request Normal mode

bit 4 ABAT: Abort All Pending Transmissions bit

1 = Abort all pending transmissions (in all transmit buffers) 0 = Transmissions proceeding as normal

bit 3-1 Mode 0:WIN2:WIN0: Window Address bitsThis selects which of the CAN buffers to switch into the access bank area. This allows access to the buffer registers from any data memory bank. After a frame has caused an interrupt, the ICODE2:ICODE0 bits can be copied to the WIN2:WIN0 bits to select the correct buffer. See Example 23-2 for a code example.

111 = Receive Buffer 0 110 = Receive Buffer 0 101 = Receive Buffer 1 100 = Transmit Buffer 0 011 = Transmit Buffer 1 010 = Transmit Buffer 2 001 = Receive Buffer 0 000 = Receive Buffer 0


bit 3-0 Mode 1:Unimplemented: Read as ‘0’Mode 2:FP3:FP0: FIFO Read Pointer bitsThese bits point to the message buffer to be read.0111:0000 = Message buffer to be read1111:1000 = Reserved

Legend:




PIC18F6585/8585/6680/8680

REGISTER 23-2: CANSTAT: CAN STATUS REGISTER

Mode 0R-1 R-0 R-0 R-0 R-0 R-0 R-0 U-0

OPMODE2(1) OPMODE1(1) OPMODE0(1) — ICODE2 ICODE1 ICODE0 —

Mode 1, 2R-1 R-0 R-0 R-0 R-0 R-0 R-0 R-0

OPMODE2(1) OPMODE1(1) OPMODE0(1) EICODE4 EICODE3 EICODE2 EICODE1 EICODE0

bit 7 bit 0

bit 7-5 OPMODE2:OPMODE0: Operation Mode Status bits(1)

111 = Reserved 110 = Reserved 101 = Reserved 100 = Configuration mode 011 = Listen Only mode 010 = Loopback mode 001 = Disable/Sleep mode 000 = Normal mode

bit 4 Mode 0:

Unimplemented: Read as ‘0’

bit 3-1 ICODE2:ICODE0: Interrupt Code bits in Mode 0

When an interrupt occurs, a prioritized coded interrupt value will be present in these bits. This code indicates the source of the interrupt. By copying ICODE2:ICODE0 to WIN2:WIN0, it is pos-sible to select the correct buffer to map into the Access Bank area. See Example 23-2 for a code example.


Legend:



ICODE2:ICODE0 ValueNo interrupt 000

Error interrupt 001

TXB2 interrupt 010

TXB1 interrupt 011

TXB0 interrupt 100

RXB1 interrupt 101

RXB0 interrupt 110

Wake-up interrupt 111


PIC18F6585/8585/6680/8680

REGISTER 23-2: CANSTAT: CAN STATUS REGISTER (CONTINUED)

bit 4-0 Mode 1,2:EICODE4:EICODE0: Interrupt Code bits in Mode 1 and Mode 2When an interrupt occurs, a prioritized coded interrupt value will be present in these bits. This code indicates the source of the interrupt. Unlike ICODE bits in Mode 0, these bits may not be copied directly to EWIN bits to map interrupted buffer to Access Bank area. If required, user software may maintain a table in program memory to map EICODE bits to EWIN bits and access interrupt buffer in Access Bank area.

Note 1: To achieve maximum power saving and/or able to wake-up on CAN bus activity,switch CAN module to Disable mode before putting the device to Sleep.

2: In Mode 2, if the buffer is configured as a receiver, EICODE bits will always contain‘10000’ upon interrupt.

Legend: U = Unimplemented bit, read as ‘0’ - n = Value at POR

C = Clearable bit R = Readable bit W = Writable bit x = Bit is unknown

‘1’ = Bit is set ‘0’ = Bit is cleared

EICODE4:EICODE0 ValueNo interrupt 00000

Error interrupt 00010

TXB2 interrupt 00100



RXB1 interrupt 10001/10000(2)

RXB0 interrupt 10000

Wake-up interrupt 01110

RX/TX B0 interrupt 10010(2)







PIC18F6585/8585/6680/8680

EXAMPLE 23-1: CHANGING TO CONFIGURATION MODE

EXAMPLE 23-2: WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS TX/RX BUFFERS

; Request Configuration mode.MOVLW B’10000000’ ; Set to Configuration Mode.MOVWF CANCON; A request to switch to Configuration mode may not be immediately honored. ; Module will wait for CAN bus to be idle before switching to Configuration Mode.; Request for other modes such as Loopback, Disable etc. may be honored immediately. ; It is always good practice to wait and verify before continuing.

ConfigWait:MOVF CANSTAT, W ; Read current mode state.ANDLW B’10000000’ ; Interested in OPMODE bits only.TSTFSZ WREG ; Is it Configuration mode yet?BRA ConfigWait ; No. Continue to wait...; Module is in Configuration mode now.; Modify configuration registers as required.; Switch back to Normal mode to be able to communicate.

; Save application required context.; Poll interrupt flags and determine source of interrupt; This was found to be CAN interrupt; TempCANCON and TempCANSTAT are variables defined in Access Bank lowMOVFF CANCON, TempCANCON ; Save CANCON.WIN bits

; This is required to prevent CANCON; from corrupting CAN buffer access; in-progress while this interrupt; occurred

MOVFF CANSTAT, TempCANSTAT ; Save CANSTAT register; This is required to make sure that; we use same CANSTAT value rather; than one changed by another CAN; interrupt.

MOVF TempCANSTAT, W ; Retrieve ICODE bitsANDLW B’00001110’ADDWF PCL, F ; Perform computed GOTO

; to corresponding interrupt causeBRA NoInterrupt ; 000 = No interruptBRA ErrorInterrupt ; 001 = Error interruptBRA TXB2Interrupt ; 010 = TXB2 interruptBRA TXB1Interrupt ; 011 = TXB1 interruptBRA TXB0Interrupt ; 100 = TXB0 interruptBRA RXB1Interrupt ; 101 = RXB1 interruptBRA RXB0Interrupt ; 110 = RXB0 interrupt

; 111 = Wake-up on interruptWakeupInterrupt

BCF PIR3, WAKIF ; Clear the interrupt flag;; User code to handle wake-up procedure;;; Continue checking for other interrupt source or return from here…

NoInterrupt… ; PC should never vector here. User may

; place a trap such as infinite loop or pin/port; indication to catch this error.


PIC18F6585/8585/6680/8680

EXAMPLE 23-2: WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS TX/RX BUFFERS (CONTINUED)

ErrorInterruptBCF PIR3, ERRIF ; Clear the interrupt flag… ; Handle error.RETFIE

TXB2InterruptBCF PIR3, TXB2IF ; Clear the interrupt flagGOTO AccessBuffer



RXB1InterruptBCF PIR3, RXB1IF ; Clear the interrupt flagGOTO Accessbuffer

RXB0InterruptBCF PIR3, RXB0IF ; Clear the interrupt flagGOTO AccessBuffer

AccessBuffer ; This is either TX or RX interrupt; Copy CANSTAT.ICODE bits to CANCON.WIN bitsMOVF TempCANCON, W ; Clear CANCON.WIN bits before copying

; new ones.ANDLW B’11110001’ ; Use previously saved CANCON value to

; make sure same value.MOVWF TempCANCON ; Copy masked value back to TempCANCONMOVF TempCANSTAT, W ; Retrieve ICODE bitsANDLW B’00001110’ ; Use previously saved CANSTAT value

; to make sure same value.IORWF TempCANCON ; Copy ICODE bits to WIN bits.MOVFF TempCANCON, CANCON ; Copy the result to actual CANCON; Access current buffer…; User code; Restore CANCON.WIN bitsMOVF CANCON, W ; Preserve current non WIN bitsANDLW B’11110001’IORWF TempCANCON ; Restore original WIN bits; Do not need to restore CANSTAT - it is read-only register.; Return from interrupt or check for another module interrupt source


PIC18F6585/8585/6680/8680

REGISTER 23-3: ECANCON: ENHANCED CAN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0

MDSEL1(1, 2) MDSEL0(1, 2) FIFOWM EWIN4 EWIN3 EWIN2 EWIN1 EWIN0

bit 7 bit 0

bit 7-6 MDSEL1:MDSEL0: Mode Select bits00 = Legacy mode (Mode 0, default)01 = Enhanced Legacy mode (Mode 1)10 = Enhanced FIFO mode (Mode 2)11 = Reserved

bit 5 FIFOWM: FIFO High Water Mark bit(3)

1 = Will cause FIFO interrupt when one receive buffer remains(4)

0 = Will cause FIFO interrupt when four receive buffers remain

bit 4-0 EWIN4:EWIN0: Enhanced Window Address bits

These bits map the group of 16 banked CAN SFRs into access bank addresses 0F60-0F6Dh.Exact group of registers to map is determined by binary value of these bits.

Mode 0:Unimplemented: Read as ‘0’

Mode 1, 2:00000 = Acceptance Filters 0, 1, 2 and BRGCON3, 200001 = Acceptance Filters 3, 4, 5 and BRGCON1, CIOCON00010 = Acceptance Filter Masks, Error and Interrupt Control00011 = Transmit Buffer 000100 = Transmit Buffer 100101 = Transmit Buffer 200110 = Acceptance Filters 6, 7, 800111 = Acceptance Filters 9, 10, 1101000 = Acceptance Filters 12, 13, 1401001 = Acceptance Filters 1501010-01111 = Reserved10000 = Receive Buffer 010001 = Receive Buffer 110010 = TX/RX Buffer 010011 = TX/RX Buffer 110100 = TX/RX Buffer 210101 = TX/RX Buffer 310110 = TX/RX Buffer 410111 = TX/RX Buffer 511000-11111 = Reserved

Note 1: These bits can only be changed in Configuration mode. See Register 19-2 tochange to Configuration mode.

2: A new mode takes into effect only after Configuration mode is exited.

3: This bit is used in Mode 2 only.

4: FIFO length of 4 or less will cause this bit to be set.

Legend:




PIC18F6585/8585/6680/8680

REGISTER 23-4: COMSTAT: COMMUNICATION STATUS REGISTER

Mode 0R/C-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0

RXB0OVFL RXB1OVFL TXBO TXBP RXBP TXWARN RXWARN EWARN

Mode 1U-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0

— RXBnOVFL TXB0 TXBP RXBP TXWARN RXWARN EWARN

Mode 2R/C-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0

FIFOEMPTY RXBnOVFL TXBO TXBP RXBP TXWARN RXWARN EWARN

bit 7 bit 0

bit 7 Mode 0:RXB0OVFL: Receive Buffer 0 Overflow bit1 = Receive Buffer 0 overflowed 0 = Receive Buffer 0 has not overflowedMode 1:Unimplemented: Read as ‘0’

Mode 2:FIFOEMPTY: FIFO Not Empty bit1 = Receive FIFO is not empty 0 = Receive FIFO is empty

bit 6 Mode 0:RXB1OVFL: Receive Buffer 1 Overflow bit1 = Receive Buffer 1 overflowed 0 = Receive Buffer 1 has not overflowed Mode 1, 2:RXBnOVFL: Receive Buffer Overflow bit1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed

bit 5 TXBO: Transmitter Bus-Off bit1 = Transmit error counter > 255 0 = Transmit error counter ≤ 255

bit 4 TXBP: Transmitter Bus Passive bit

1 = Transmit error counter > 127 0 = Transmit error counter ≤ 127

bit 3 RXBP: Receiver Bus Passive bit1 = Receive error counter > 127 0 = Receive error counter ≤ 127

bit 2 TXWARN: Transmitter Warning bit1 = 127 ≥ Transmit error counter > 95 0 = Transmit error counter ≤ 95

bit 1 RXWARN: Receiver Warning bit

1 = 127 ≥ Receive error counter > 95 0 = Receive error counter ≤ 95

bit 0 EWARN: Error Warning bitThis bit is a flag of the RXWARN and TXWARN bits.

1 = The RXWARN or the TXWARN bits are set 0 = Neither the RXWARN or the TXWARN bits are set

Legend:

C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’



PIC18F6585/8585/6680/8680

23.2.2 DEDICATED CAN TRANSMIT BUFFER REGISTERS

This section describes the dedicated CAN TransmitBuffer registers and their associated control registers.

REGISTER 23-5: TXBnCON: TRANSMIT BUFFER n CONTROL REGISTERS [0 ≤ n ≤ 2]

Mode 0U-0 R-0 R-0 R-0 R/W-0 U-0 R/W-0 R/W-0

— TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0

Mode 1, 2R/C-0 R-0 R-0 R-0 R/W-0 U-0 R/W-0 R/W-0

TXBIF TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0

bit 7 bit 0

bit 7 Mode 0:

Unimplemented: Read as ‘0’Mode 1, 2:TXBIF: Transmit Buffer Interrupt Flag bit

1 = Transmit buffer has completed transmission of message and may be reloaded0 = Transmit buffer has not completed transmission of a message

bit 6 TXABT: Transmission Aborted Status bit(1)

1 = Message was aborted 0 = Message was not aborted

bit 5 TXLARB: Transmission Lost Arbitration Status bit(1)

1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent

bit 4 TXERR: Transmission Error Detected Status bit(1) 1 = A bus error occurred while the message was being sent 0 = A bus error did not occur while the message was being sent

bit 3 TXREQ: Transmit Request Status bit(2)

1 = Requests sending a message. Clears the TXABT, TXLARB, and TXERR bits.0 = Automatically cleared when the message is successfully sent

Note: Clearing this bit in software while the bit is set, will request a message abort.


bit 1-0 TXPRI1:TXPRI0: Transmit Priority bits(3)

11 = Priority Level 3 (highest priority) 10 = Priority Level 2 01 = Priority Level 1 00 = Priority Level 0 (lowest priority)

Note 1: This bit is automatically cleared when TXREQ is set.

2: While TXREQ is set, Transmit Buffer registers remain read-only.

3: These bits define the order in which transmit buffers will be transferred. They do notalter the CAN message identifier.





PIC18F6585/8585/6680/8680

REGISTER 23-6: TXBnSIDH: TRANSMIT BUFFER n STANDARD IDENTIFIER REGISTERS, HIGH BYTE [0 ≤ n ≤ 2]

REGISTER 23-7: TXBnSIDL: TRANSMIT BUFFER n STANDARD IDENTIFIER REGISTERS, LOW BYTE [0 ≤ n ≤ 2]

REGISTER 23-8: TXBnEIDH: TRANSMIT BUFFER n EXTENDED IDENTIFIER REGISTERS, HIGH BYTE [0 ≤ n ≤ 2]

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3

bit 7 bit 0

bit 7-0 SID10:SID3: Standard Identifier bits, if EXIDE (TXBnSIDL<3>) = 0;Extended Identifier bits EID28:EID21, if EXIDE = 1.

Legend:



R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x

SID2 SID1 SID0 — EXIDE — EID17 EID16

bit 7 bit 0

bit 7-5 SID2:SID0: Standard Identifier bits, if EXIDE (TXBnSIDL<3>) = 0;

Extended Identifier bits EID20:EID18, if EXIDE = 1.


bit 3 EXIDE: Extended Identifier Enable bit1 = Message will transmit extended ID, SID10:SID0 becomes EID28:EID18 0 = Message will transmit standard ID, EID17:EID0 are ignored


bit 1-0 EID17:EID16: Extended Identifier bits

Legend:




EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8

bit 7 bit 0

bit 7-0 EID15:EID8: Extended Identifier bits (not used when transmitting standard identifier message)

Legend:

PIC18F6585/8585/6680/8680

REGISTER 23-9: TXBnEIDL: TRANSMIT BUFFER n EXTENDED IDENTIFIER REGISTERS, LOW BYTE [0 ≤ n ≤ 2]

REGISTER 23-10: TXBnDm: TRANSMIT BUFFER n DATA FIELD BYTE m REGISTERS [0 ≤ n ≤ 2, 0 ≤ m ≤ 7]



bit 7 bit 0

bit 7-0 EID7:EID0: Extended Identifier bits (not used when transmitting standard identifier message)

Legend:




TXBnDm7 TXBnDm6 TXBnDm5 TXBnDm4 TXBnDm3 TXBnDm2 TXBnDm1 TXBnDm0

bit 7 bit 0

bit 7-0 TXBnDm7:TXBnDm0: Transmit Buffer n Data Field Byte m bits (where 0 ≤ n < 3 and 0 ≤ m < 8)

Each transmit buffer has an array of registers. For example, Transmit Buffer 0 has 7 registers: TXB0D0 to TXB0D7.

Legend:

PIC18F6585/8585/6680/8680

REGISTER 23-11: TXBnDLC: TRANSMIT BUFFER n DATA LENGTH CODE REGISTERS [0 ≤ n ≤ 2]

REGISTER 23-12: TXERRCNT: TRANSMIT ERROR COUNT REGISTER

U-0 R/W-x U-0 U-0 R/W-x R/W-x R/W-x R/W-x

— TXRTR — — DLC3 DLC2 DLC1 DLC0

bit 7 bit 0


bit 6 TXRTR: Transmit Remote Frame Transmission Request bit

1 = Transmitted message will have TXRTR bit set 0 = Transmitted message will have TXRTR bit cleared


bit 3-0 DLC3:DLC0: Data Length Code bits1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Data length = 8 bytes 0111 = Data length = 7 bytes 0110 = Data length = 6 bytes 0101 = Data length = 5 bytes 0100 = Data length = 4 bytes 0011 = Data length = 3 bytes 0010 = Data length = 2 bytes 0001 = Data length = 1 bytes 0000 = Data length = 0 bytes

Legend:



R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0

bit 7 bit 0

bit 7-0 TEC7:TEC0: Transmit Error Counter bits

This register contains a value which is derived from the rate at which errors occur. When the error count overflows, the bus-off state occurs. When the bus has 128 occurrences of 11 consecutive recessive bits, the counter value is cleared.

Legend:




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EXAMPLE 23-3: TRANSMITTING A CAN MESSAGE USING BANKED METHOD; Need to transmit Standard Identifier message 123h using TXB0 buffer.; To successfully transmit, CAN module must be either in Normal or Loopback mode.; TXB0 buffer is not in access bank. And since we want banked method, we need to make sure; that correct bank is selected.BANKSEL TXB0CON ; One BANKSEL in beginning will make sure that we are

; in correct bank for rest of the buffer access.; Now load transmit data into TXB0 buffer.MOVLW MY_DATA_BYTE1 ; Load first data byte into bufferMOVWF TXB0D0 ; Compiler will automatically set “BANKED” bit; Load rest of data bytes - up to 8 bytes into TXB0 buffer....; Load message identifierMOVLW 60H ; Load SID2:SID0, EXIDE = 0MOVWF TXB0SIDLMOVLW 24H ; Load SID10:SID3MOVWF TXB0SIDH; No need to load TXB0EIDL:TXB0EIDH, as we are transmitting Standard Identifier Message only.

; Now that all data bytes are loaded, mark it for transmission.MOVLW B’00001000’ ; Normal priority; Request transmissionMOVWF TXB0CON

; If required, wait for message to get transmittedBTFSC TXB0CON, TXREQ ; Is it transmitted?BRA $-2 ; No. Continue to wait...

; Message is transmitted.


PIC18F6585/8585/6680/8680

EXAMPLE 23-4: TRANSMITTING A CAN MESSAGE USING WIN BITS; Need to transmit Standard Identifier message 123h using TXB0 buffer.; To successfully transmit, CAN module must be either in Normal or Loopback mode.; TXB0 buffer is not in access bank. Use WIN bits to map it to RXB0 area.MOVF CANCON, W ; WIN bits are in lower 4 bits only. Read CANCON

; register to preserve all other bits. If operation; mode is already known, there is no need to preserve; other bits.

ANDLW B’11110000’ ; Clear WIN bits.IORLW B’00001000’ ; Select Transmit Buffer 0MOVWF CANCON ; Apply the changes.; Now TXB0 is mapped in place of RXB0. All future access to RXB0 registers will actually; yield TXB0 register values.

; Load transmit data into TXB0 buffer.MOVLW MY_DATA_BYTE1 ; Load first data byte into bufferMOVWF RXB0D0 ; Access TXB0D0 via RXB0D0 address.; Load rest of the data bytes - up to 8 bytes into “TXB0” buffer using RXB0 registers....; Load message identifierMOVLW 60H ; Load SID2:SID0, EXIDE = 0MOVWF RXB0SIDLMOVLW 24H ; Load SID10:SID3MOVWF RXB0SIDH; No need to load RXB0EIDL:RXB0EIDH, as we are transmitting Standard Identifier Message only.

; Now that all data bytes are loaded, mark it for transmission.MOVLW B’00001000’ ; Normal priority; Request transmissionMOVWF RXB0CON

; If required, wait for message to get transmittedBTFSC RXB0CON, TXREQ ; Is it transmitted?BRA $-2 ; No. Continue to wait...

; Message is transmitted.; If required, reset the WIN bits to default state.


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23.2.3 DEDICATED CAN RECEIVE BUFFER REGISTERS

This section shows the dedicated CAN Receive Bufferregisters with their associated control registers.

REGISTER 23-13: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER

Mode 0R/C-0 R/W-0 R/W-0 U-0 R-0 R/W-0 R-0 R-0

RXFUL RXM1 RXM0 — RXRTRRO RXB0DBEN JTOFF FILHIT0

Mode 1, 2R/C-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0

RXFUL RXM1 RTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0bit 7 bit 0

bit 7 RXFUL: Receive Full Status bit1 = Receive buffer contains a received message0 = Receive buffer is open to receive a new message

Note: This bit is set by the CAN module upon receiving a message and must be clearedby software after the buffer is read. As long as RXFUL is set, no new message willbe loaded and buffer will be considered full.

bit 6 Mode 0:RXM1: Receive Buffer Mode bit 1; combines with RXM0 to form RXM<1:0> bits (see bit 5)

11 = Receive all messages (including those with errors); filter criteria is ignored 10 = Receive only valid messages with extended identifier; EXIDEN in RXFnSIDL must be ‘1’01 = Receive only valid messages with standard identifier, EXIDEN in RXFnSIDL must be ‘0’00 = Receive all valid messages as per EXIDEN bit in RXFnSIDL register

Mode 1, 2:RXM1: Receive Buffer Mode bit1 = Receive all messages (including those with errors); acceptance filters are ignored 0 = Receive all valid messages as per acceptance filters

bit 5 Mode 0:RXM0: Receive Buffer Mode bit 0; combines with RXM1 to form RXM<1:0> bits (see bit 6)

Mode 1, 2:RTRRO: Remote Transmission Request bit for Received Message (read-only)

1 = A remote transmission request is received0 = A remote transmission request is not received

bit 4 Mode 0:Unimplemented: Read as ‘0’

Mode 1, 2:

FILHIT4: Filter Hit bit 4This bit combines with other bits to form filter acceptance bits <4:0>.

bit 3 Mode 0:RXRTRRO: Remote Transmission Request bit for Received Message (read-only)1 = A remote transmission request is received0 = A remote transmission request is not received

Mode 1, 2:FILHIT3: Filter Hit bit 3

This bit combines with other bits to form filter acceptance bits <4:0>.

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REGISTER 23-13: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER (CONTINUED)

bit 2 Mode 0:RXB0DBEN: Receive Buffer 0 Double-Buffer Enable bit 1 = Receive Buffer 0 overflow will write to Receive Buffer 1 0 = No Receive Buffer 0 overflow to Receive Buffer 1

Mode 1, 2:FILHIT2: Filter Hit bit 2This bit combines with other bits to form filter acceptance bits <4:0>.

bit 1 Mode 0:JTOFF: Jump Table Offset bit (read-only copy of RXB0DBEN)1 = Allows jump table offset between 6 and 7 0 = Allows jump table offset between 1 and 0

Note: This bit allows same filter jump table for both RXB0CON and RXB1CON.

Mode 1, 2:FILHIT1: Filter Hit bit 1

This bit combines with other bits to form filter acceptance bits <4:0>.

bit 0 Mode 0:

FILHIT0: Filter Hit bit 0This bit indicates which acceptance filter enabled the message reception into Receive Buffer 0.1 = Acceptance Filter 1 (RXF1) 0 = Acceptance Filter 0 (RXF0)

Mode 1, 2:

FILHIT0: Filter Hit bit 0This bit, in combination with FILHIT<4:1>, indicates which acceptance filter enabled themessage reception into this receive buffer.01111 = Acceptance Filter 15 (RXF15) 01110 = Acceptance Filter 14 (RXF14)...00000 = Acceptance Filter 0 (RXF0)

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REGISTER 23-14: RXB1CON: RECEIVE BUFFER 1 CONTROL REGISTER

Mode 0R/C-0 R/W-0 R/W-0 U-0 R-0 R/W-0 R-0 R-0

RXFUL RXM1 RXM0 — RXRTRRO FILHIT2 FILHIT1 FILHIT0

Mode 1, 2R/C-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0

RXFUL RXM1 RTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0bit 7 bit 0

bit 7 RXFUL: Receive Full Status bit1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message

Note: This bit is set by the CAN module upon receiving a message and must be cleared by software afterthe buffer is read. As long as RXFUL is set, no new message will be loaded and buffer will beconsidered full.

bit 6 Mode 0:RXM1: Receive Buffer Mode bit 1; combines with RXM0 to form RXM<1:0> bits (see bit 5) 11 = Receive all messages (including those with errors); filter criteria is ignored 10 = Receive only valid messages with extended identifier; EXIDEN in RXFnSIDL must be ‘1’01 = Receive only valid messages with standard identifier, EXIDEN in RXFnSIDL must be ‘0’00 = Receive all valid messages as per EXIDEN bit in RXFnSIDL registerMode 1, 2:RXM1: Receive Buffer Mode bit1 = Receive all messages (including those with errors); acceptance filters are ignored 0 = Receive all valid messages as per acceptance filters

bit 5 Mode 0:RXM0: Receive Buffer Mode bit 0; combines with RXM1 to form RXM<1:0> bits (see bit 6)Mode 1, 2:RTRRO: Remote Transmission Request bit for Received Message (read-only)1 = A remote transmission request is received0 = A remote transmission request is not received

bit 4 Mode 0:Unimplemented: Read as ‘0’ Mode 1, 2:FILHIT4: Filter Hit bit 4This bit combines with other bits to form filter acceptance bits <4:0>.

bit 3 Mode 0:RXRTRRO: Remote Transmission Request bit for Received Message (read-only)1 = A remote transmission request is received0 = A remote transmission request is not receivedMode 1, 2:FILHIT3: Filter Hit bit 3This bit combines with other bits to form filter acceptance bits <4:0>.

bit 2-0 Mode 0:FILHIT2:FILHIT0: Filter Hit bitsThese bits indicate which acceptance filter enabled the last message reception into Receive Buffer 1.111 = Reserved 110 = Reserved 101 = Acceptance Filter 5 (RXF5) 100 = Acceptance Filter 4 (RXF4) 011 = Acceptance Filter 3 (RXF3) 010 = Acceptance Filter 2 (RXF2) 001 = Acceptance Filter 1 (RXF1), only possible when RXB0DBEN bit is set 000 = Acceptance Filter 0 (RXF0), only possible when RXB0DBEN bit is setMode 1, 2:FILHIT2:FILHIT0 Filter Hit bits <2:0>These bits, in combination with FILHIT<4:3>, indicate which acceptance filter enabled the message reception into this receive buffer.01111 = Acceptance Filter 15 (RXF15) 01110 = Acceptance Filter 14 (RXF14)...00000 = Acceptance Filter 0 (RXF0)

Legend: U = Unimplemented bit, read as ‘0’ - n = Value at PORC = Clearable bit R = Readable bit W = Writable bit x = Bit is unknown‘1’ = Bit is set ‘0’ = Bit is cleared

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REGISTER 23-15: RXBnSIDH: RECEIVE BUFFER n STANDARD IDENTIFIER REGISTERS, HIGH BYTE [0 ≤ n ≤ 1]

REGISTER 23-16: RXBnSIDL: RECEIVE BUFFER n STANDARD IDENTIFIER REGISTERS, LOW BYTE [0 ≤ n ≤ 1]

REGISTER 23-17: RXBnEIDH: RECEIVE BUFFER n EXTENDED IDENTIFIER REGISTERS, HIGH BYTE [0 ≤ n ≤ 1]

R-x R-x R-x R-x R-x R-x R-x R-x


bit 7 bit 0

bit 7-0 SID10:SID3: Standard Identifier bits, if EXID = 0 (RXBnSIDL<3>);Extended Identifier bits EID28:EID21, if EXID = 1.

Legend:



R-x R-x R-x R-x R-x U-0 R-x R-x

SID2 SID1 SID0 SRR EXID — EID17 EID16

bit 7 bit 0

bit 7-5 SID2:SID0: Standard Identifier bits, if EXID = 0;

Extended Identifier bits EID20:EID18, if EXID = 1.

bit 4 SRR: Substitute Remote Request bit

This bit is always ‘0’ when EXID = 1 or equal to the value of RXRTRRO (RBXnCON<3>) when EXID = 0.

bit 3 EXID: Extended Identifier bit1 = Received message is an extended data frame, SID10:SID0 are EID28:EID18 0 = Received message is a standard data frame



Legend:





bit 7 bit 0


Legend:

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REGISTER 23-18: RXBnEIDL: RECEIVE BUFFER n EXTENDED IDENTIFIER REGISTERS, LOW BYTE [0 ≤ n ≤ 1]

REGISTER 23-19: RXBnDLC: RECEIVE BUFFER n DATA LENGTH CODE REGISTERS [0 ≤ n ≤ 1]



bit 7 bit 0


Legend:



U-0 R-x R-x R-x R-x R-x R-x R-x

— RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0

bit 7 bit 0


bit 6 RXRTR: Receiver Remote Transmission Request bit1 = Remote transfer request 0 = No remote transfer request

bit 5 RB1: Reserved bit 1

Reserved by CAN Spec and read as ‘0’.

bit 4 RB0: Reserved bit 0

Reserved by CAN Spec and read as ‘0’.

bit 3-0 DLC3:DLC0: Data Length Code bits

1111 = Invalid 1110 = Invalid 1101 = Invalid 1100 = Invalid 1011 = Invalid 1010 = Invalid 1001 = Invalid 1000 = Data length = 8 bytes 0111 = Data length = 7 bytes 0110 = Data length = 6 bytes 0101 = Data length = 5 bytes 0100 = Data length = 4 bytes 0011 = Data length = 3 bytes 0010 = Data length = 2 bytes 0001 = Data length = 1 bytes 0000 = Data length = 0 bytes

Legend:




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REGISTER 23-20: RXBnDm: RECEIVE BUFFER n DATA FIELD BYTE m REGISTERS[0 ≤ n ≤ 1, 0 ≤ m ≤ 7]

REGISTER 23-21: RXERRCNT: RECEIVE ERROR COUNT REGISTER

EXAMPLE 23-5: READING A CAN MESSAGE


RXBnDm7 RXBnDm6 RXBnDm5 RXBnDm4 RXBnDm3 RXBnDm2 RXBnDm1 RXBnDm0

bit 7 bit 0

bit 7-0 RXBnDm7:RXBnDm0: Receive Buffer n Data Field Byte m bits (where 0 ≤ n < 1 and 0 < m < 7)Each receive buffer has an array of registers. For example, Receive Buffer 0 has 8 registers: RXB0D0 to RXB0D7.

Legend:



R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0

bit 7 bit 0

bit 7-0 REC7:REC0: Receive Error Counter bitsThis register contains the receive error value as defined by the CAN specifications.

When RXERRCNT > 127, the module will go into an error-passive state. RXERRCNT does not have the ability to put the module in “bus-off” state.

Legend:



; Need to read a pending message from RXB0 buffer.; To receive any message, filter, mask and RXM1:RXM0 bits in RXB0CON registers must be ; programmed correctly.;; Make sure that there is a message pending in RXB0.BTFSS RXB0CON, RXFUL ; Does RXB0 contain a message?BRA NoMessage ; No. Handle this situation...; We have verified that a message is pending in RXB0 buffer.; If this buffer can receive both Standard or Extended Identifier messages, ; identify type of message received.BTFSS RXB0SIDL, EXID ; Is this Extended Identifier?BRA StandardMessage ; No. This is Standard Identifier message.

; Yes. This is Extended Identifier message.; Read all 29-bits of Extended Identifier message....; Now read all data bytesMOVFF RXB0DO, MY_DATA_BYTE1...; Once entire message is read, mark the RXB0 that it is read and no longer FULL.BCF RXB0CON, RXFUL ; This will allow CAN Module to load new messages

; into this buffer....

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23.2.3.1 Programmable TX/RX and Auto RTR Buffers

The ECAN module contains 6 message buffers that canbe programmed as transmit or receive buffers. Any ofthese buffers can also be programmed to automaticallyhandle RTR messages.

REGISTER 23-22: BnCON: TX/RX BUFFER n CONTROL REGISTERS IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 0](1)

Note: These registers are not used in Mode 0.

R/C-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0

RXFUL RXM1 RTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0

bit 7 bit 0

bit 7 RXFUL: Receive Full Status bit(1)

1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message

Note: This bit is set by the CAN module upon receiving a message and must be clearedby software after the buffer is read. As long as RXFUL is set, no new message willbe loaded and buffer will be considered full.

bit 6 RXM1: Receive Buffer Mode bit1 = Receive all messages including partial and invalid (acceptance filters are ignored)0 = Receive all valid messages as per acceptance filters

bit 5 RTRRO: Read-Only Remote Transmission Request bit for Received Message1 = Received message is a remote transmission request0 = Received message is not a remote transmission request

bit 4-0 FILHIT4:FILHIT0: Filter Hit bits

These bits indicate which acceptance filter enabled the last message reception into this buffer.01111 = Acceptance Filter 15 (RXF15)01110 = Acceptance Filter 14 (RXF14) ...00001 = Acceptance Filter 1 (RXF1) 00000 = Acceptance Filter 0 (RXF0)

Note 1: These registers are available in Mode 1 and 2 only.

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REGISTER 23-23: BnCON: TX/RX BUFFER n CONTROL REGISTERS IN TRANSMIT MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 1](1)

R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

TXBIF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0

bit 7 bit 0

bit 7 TXBIF: Transmit Buffer Interrupt Flag bit(1)

1 = A message is successfully transmitted0 = No message was transmitted

bit 6 TXABT: Transmission Aborted Status bit(1)

1 = Message was aborted 0 = Message was not aborted

bit 5 TXLARB: Transmission Lost Arbitration Status bit(2) 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent

bit 4 TXERR: Transmission Error Detected Status bit(2) 1 = A bus error occurred while the message was being sent 0 = A bus error did not occur while the message was being sent

bit 3 TXREQ: Transmit Request Status bit(3)

1 = Requests sending a message; clears the TXABT, TXLARB, and TXERR bits0 = Automatically cleared when the message is successfully sent

Note: Clearing this bit in software while the bit is set will request a message abort.

bit 2 RTREN: Automatic Remote Transmission Request Enable bit1 = When a remote transmission request is received, TXREQ will be automatically set0 = When a remote transmission request is received, TXREQ will be unaffected

bit 1-0 TXPRI1:TXPRI0: Transmit Priority bits(4)

11 = Priority Level 3 (highest priority) 10 = Priority Level 2 01 = Priority Level 1 00 = Priority Level 0 (lowest priority)


2: This bit is automatically cleared when TXREQ is set.

3: While TXREQ is set or transmission is in progress, transmit buffer registers remainread-only.

4: These bits set the order in which the transmit buffer will be transferred. They do notalter the CAN message identifier.

Legend:

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REGISTER 23-24: BnSIDH: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS, HIGH BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 0](1)

REGISTER 23-25: BnSIDH: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS, HIGH BYTE IN TRANSMIT MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 1](1)



bit 7 bit 0

bit 7-0 SID10:SID3: Standard Identifier bits, if EXIDE (BnSIDL<3>) = 0;Extended Identifier bits EID28:EID21, if EXIDE = 1.


Legend:





bit 7 bit 0

bit 7-0 SID10:SID3: Standard Identifier bits, if EXIDE (BnSIDL<3>) = 0;Extended Identifier bits EID28:EID21, if EXIDE = 1.


Legend:

PIC18F6585/8585/6680/8680

REGISTER 23-26: BnSIDL: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 0](1)

REGISTER 23-27: BnSIDL: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS, LOW BYTE IN TRANSMIT MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 1](1)

R-x R-x R-x R-x R-x U-0 R-x R-x

SID2 SID1 SID0 SRR EXID — EID17 EID16

bit 7 bit 0

bit 7-5 SID2:SID0: Standard Identifier bits, if EXID = 0;Extended Identifier bits EID20:EID18, if EXID = 1.

bit 4 SRR: Substitute Remote Transmission Request bit (only when EXID = 1)1 = Remote transmission request occurred0 = No remote transmission request occurred

bit 3 EXID: Extended Identifier Enable bit

1 = Received message is an extended identifier frame, SID10:SID0 are EID28:EID18 0 = Received message is a standard identifier frame




Legend:




SID2 SID1 SID0 — EXIDE — EID17 EID16

bit 7 bit 0

bit 7-5 SID2:SID0: Standard Identifier bits, if EXIDE = 0;

Extended Identifier bits EID20:EID18, if EXIDE = 1.


bit 3 EXIDE: Extended Identifier Enable bit1 = Received message is an extended identifier frame, SID10:SID0 are EID28:EID18 0 = Received message is a standard identifier frame




Legend:

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REGISTER 23-28: BnEIDH: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS, HIGH BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 0](1)

REGISTER 23-29: BnEIDH: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS, HIGH BYTE IN TRANSMIT MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 1](1)



bit 7 bit 0



Legend:





bit 7 bit 0



Legend:

PIC18F6585/8585/6680/8680

REGISTER 23-30: BnEIDL: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL<n>) = 0](1)

REGISTER 23-31: BnEIDL: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS, LOW BYTE IN TRANSMIT MODE [0 ≤ n ≤ 5, TXnEN (BSEL<n>) = 1](1)



bit 7 bit 0



Legend:





bit 7 bit 0



Legend:

PIC18F6585/8585/6680/8680

REGISTER 23-32: BnDm: TX/RX BUFFER n DATA FIELD BYTE m REGISTERS IN RECEIVE MODE[0 ≤ n ≤ 5, 0 ≤ m ≤ 7, TXnEN (BSEL<n>) = 0](1)

REGISTER 23-33: BnDm: TX/RX BUFFER n DATA FIELD BYTE m REGISTERS IN TRANSMIT MODE[0 ≤ n ≤ 5, 0 ≤ m ≤ 7, TXnEN (BSEL<n>) = 1](1)


BnDm7 BnDm6 BnDm5 BnDm4 BnDm3 BnDm2 BnDm1 BnDm0

bit 7 bit 0

bit 7-0 BnDm7:BnDm0: Receive Buffer n Data Field Byte m bits (where 0 ≤ n < 3 and 0 < m < 8)Each receive buffer has an array of registers. For example, Receive Buffer 0 has 7 registers: B0D0 to B0D7.


Legend:




BnDm7 BnDm6 BnDm5 BnDm4 BnDm3 BnDm2 BnDm1 BnDm0

bit 7 bit 0

bit 7-0 BnDm7:BnDm0: Transmit Buffer n Data Field Byte m bits (where 0 ≤ n < 3 and 0 < m < 8)Each transmit buffer has an array of registers. For example, Transmit Buffer 0 has 7 registers: TXB0D0 to TXB0D7.


Legend:

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REGISTER 23-34: BnDLC: TX/RX BUFFER n DATA LENGTH CODE REGISTERS IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL<n>) = 0](1)

U-0 R-x R-x R-x R-x R-x R-x R-x

— RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0

bit 7 bit 0


bit 6 RXRTR: Receiver Remote Transmission Request bit

1 = This is a remote transmission request0 = This is not a remote transmission request

bit 5 RB1: Reserved bit 1Reserved by CAN Spec and read as ‘0’.

bit 4 RB0: Reserved bit 0Reserved by CAN Spec and read as ‘0’.

bit 3-0 DLC3:DLC0: Data Length Code bits1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Data length = 8 bytes 0111 = Data length = 7 bytes 0110 = Data length = 6 bytes 0101 = Data length = 5 bytes 0100 = Data length = 4 bytes 0011 = Data length = 3 bytes 0010 = Data length = 2 bytes 0001 = Data length = 1 bytes 0000 = Data length = 0 bytes


Legend:

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REGISTER 23-35: BnDLC: TX/RX BUFFER n DATA LENGTH CODE REGISTERS IN TRANSMIT MODE[0 ≤ n ≤ 5, TXnEN (BSEL<n>) = 1](1)

REGISTER 23-36: BSEL0: BUFFER SELECT REGISTER 0(1)

U-0 R/W-x U-0 U-0 R/W-x R/W-x R/W-x R/W-x

— TXRTR — — DLC3 DLC2 DLC1 DLC0

bit 7 bit 0


bit 6 TXRTR: Transmitter Remote Transmission Request bit

1 = Transmitted message will have RTR bit set0 = Transmitted message will have RTR bit cleared


bit 3-0 DLC3:DLC0: Data Length Code bits1111-1001 = Reserved 1000 = Data length = 8 bytes 0111 = Data length = 7 bytes 0110 = Data length = 6 bytes 0101 = Data length = 5 bytes 0100 = Data length = 4 bytes 0011 = Data length = 3 bytes 0010 = Data length = 2 bytes 0001 = Data length = 1 bytes 0000 = Data length = 0 bytes


Legend:



R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0

B5TXEN B4TXEN B3TXEN B2TXEN B1TXEN B0TXEN — —

bit 7 bit 0

bit 7-2 B5TXEN:B0TXEN: Buffer 5 to Buffer 0 Transmit Enable bit1 = Buffer is configured in Transmit mode0 = Buffer is configured in Receive mode


Note 1: This register is available in Mode 1 and 2 only.

Legend:

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23.2.3.2 Message Acceptance Filters and Masks

This subsection describes the message acceptancefilters and masks for the CAN receive buffers.

REGISTER 23-37: RXFnSIDH: RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER REGISTERS, HIGH BYTE [0 ≤ n ≤ 15](1)

REGISTER 23-38: RXFnSIDL: RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER REGISTERS, LOW BYTE [0 ≤ n ≤ 15](1)

Note: These registers are writable inConfiguration mode only.



bit 7 bit 0

bit 7-0 SID10:SID3: Standard Identifier Filter bits, if EXIDEN = 0;Extended Identifier Filter bits EID28:EID21, if EXIDEN = 1.

Note 1: Registers RXF6SIDH:RXF15SIDH are available in Mode 1 and 2 only.

Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’



SID2 SID1 SID0 — EXIDEN — EID17 EID16

bit 7 bit 0

bit 7-5 SID2:SID0: Standard Identifier Filter bits, if EXIDEN = 0;

Extended Identifier Filter bits EID20:EID18, if EXIDEN = 1.


bit 3 EXIDEN: Extended Identifier Filter Enable bit1 = Filter will only accept extended ID messages 0 = Filter will only accept standard ID messages

Note: In Mode 0, this bit must be set/cleared as required, irrespective of correspondingmask register value.


bit 1-0 EID17:EID16: Extended Identifier Filter bits

Note 1: Registers RXF6SIDL:RXF15SIDL are available in Mode 1 and 2 only.



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REGISTER 23-39: RXFnEIDH: RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIERREGISTERS, HIGH BYTE [0 ≤ n ≤ 15](1)

REGISTER 23-40: RXFnEIDL: RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER REGISTERS, LOW BYTE [0 ≤ n ≤ 15](1)

REGISTER 23-41: RXMnSIDH: RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK REGISTERS, HIGH BYTE [0 ≤ n ≤ 1]



bit 7 bit 0


Note 1: Registers RXF6EIDH:RXF15EIDH are available in Mode 1 and 2 only.

Legend:





bit 7 bit 0


Note 1: Registers RXF6EIDL:RXF15EIDL are available in Mode 1 and 2 only.

Legend:





bit 7 bit 0

bit 7-0 SID10:SID3: Standard Identifier Mask bits, or Extended Identifier Mask bits EID28:EID21

Legend:




PIC18F6585/8585/6680/8680

REGISTER 23-42: RXMnSIDL: RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK REGISTERS, LOW BYTE [0 ≤ n ≤ 1]

REGISTER 23-43: RXMnEIDH: RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK REGISTERS, HIGH BYTE [0 ≤ n ≤ 1]

REGISTER 23-44: RXMnEIDL: RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK REGISTERS, LOW BYTE [0 ≤ n ≤ 1]

R/W-x R/W-x R/W-x U-0 R/W-0 U-0 R/W-x R/W-x

SID2 SID1 SID0 — EXIDEN(1) — EID17 EID16

bit 7 bit 0

bit 7-5 SID2:SID0: Standard Identifier Mask bits, or Extended Identifier Mask bits EID20:EID18


bit 3 Mode 0:Unimplemented: Read as ‘0’

Mode 1, 2:

EXIDEN: Extended Identifier Filter Enable Mask bit(1)

1 = Messages selected by EXIDEN bit in RXFnSIDL will be accepted0 = Both standard and extended identifier messages will be accepted

Note 1: This bit is available in Mode 1 and 2 only.


bit 1-0 EID17:EID16: Extended Identifier Mask bits

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bit 7 bit 0


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bit 7 bit 0


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PIC18F6585/8585/6680/8680

REGISTER 23-45: SDFLC: STANDARD DATA BYTES FILTER LENGTH COUNT REGISTER(1)

REGISTER 23-46: RXFCONn: RECEIVE FILTER CONTROL REGISTER n [0 ≤ n ≤ 1](1)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — FLC4 FLC3 FLC2 FLC1 FLC0

bit 7 bit 0


bit 4-0 FLC4:FLC0: Filter Length Count bits

Mode 0:Not used; forced to ‘00000’.

Mode 1, 2:00000-10010 = 0 18 bits are available for standard data byte filter. Actual number of bits

used depends on DLC3:DLC0 bits (RXBnDLC<3:0> or BnDLC<3:0> ifconfigured as RX buffer) of message being received.

If DLC3:DLC0 = 0000 No bits will be compared with incoming data bitsIf DLC3:DLC0 = 0001 Up to 8 data bits of RXFnEID<7:0>, as determined by FLC2:FLC0, will

be compared with the corresponding number of data bits of theincoming message

If DLC3:DLC0 = 0010 Up to 16 data bits of RXFnEID<15:0>, as determined by FLC3:FLC0,will be compared with the corresponding number of data bits of theincoming message

If DLC3:DLC0 = 0011 Up to 18 data bits of RXFnEID<17:0>, as determined by FLC4:FLC0,will be compared with the corresponding number of data bits of theincoming message


Legend:



RXFCON0R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RXF7EN RXF6EN RXF5EN RXF4EN RXF3EN RXF2EN RXF1EN RXF0EN

RXFCON1R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0

RXF15EN RXF14EN RXF13EN RXF12EN RXF11EN RXF10EN RXF9EN RXF8EN

bit 7 bit 0

bit 7-0 RXFnEN: Receive Filter n Enable bit

0 = Filter is disabled1 = Filter is enabled


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PIC18F6585/8585/6680/8680

REGISTER 23-47: RXFBCONn: RECEIVE FILTER BUFFER CONTROL REGISTER n(1)

RXFBCON0R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

F1BP_3 F1BP_2 F1BP_1 F1BP_0 F0BP_3 F0BP_2 F0BP_1 F0BP_0















bit 7 bit 0

bit 7-0 FnBP_3:FnBP_0: Filter n Buffer Pointer Nibble bits0000 = Filter n is associated with RXB00001 = Filter n is associated with RXB10010 = Filter n is associated with B00011 = Filter n is associated with B1 . . .0111 = Filter n is associated with B51111:1000 = Reserved


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PIC18F6585/8585/6680/8680

REGISTER 23-48: MSEL0: MASK SELECT REGISTER 0(1) R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0

FIL3_1 FIL3_0 FIL2_1 FIL2_0 FIL1_1 FIL1_0 FIL0_1 FIL0_0

bit 7 bit 0

bit 7-6 FIL3_1:FIL3_0: Filter 3 Select bits 1 and 011 = No mask10 = Filter 1501 = Acceptance Mask 100 = Acceptance Mask 0





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PIC18F6585/8585/6680/8680



bit 7 bit 0






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PIC18F6585/8585/6680/8680

23.2.4 CAN BAUD RATE REGISTERS

This subsection describes the CAN Baud Rateregisters.

REGISTER 23-52: BRGCON1: BAUD RATE CONTROL REGISTER 1

Note: These registers are writable inConfiguration mode only.


SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0

bit 7 bit 0

bit 7-6 SJW1:SJW0: Synchronized Jump Width bits11 = Synchronization jump width time = 4 x TQ 10 = Synchronization jump width time = 3 x TQ 01 = Synchronization jump width time = 2 x TQ 00 = Synchronization jump width time = 1 x TQ

bit 5-0 BRP5:BRP0: Baud Rate Prescaler bits111111 = TQ = (2 x 64)/FOSC 111110 = TQ = (2 x 63)/FOSC . . .000001 = TQ = (2 x 2)/FOSC 000000 = TQ = (2 x 1)/FOSC

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PIC18F6585/8585/6680/8680

REGISTER 23-53: BRGCON2: BAUD RATE CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0

bit 7 bit 0

bit 7 SEG2PHTS: Phase Segment 2 Time Select bit1 = Freely programmable 0 = Maximum of PHEG1 or Information Processing Time (IPT), whichever is greater

bit 6 SAM: Sample of the CAN bus Line bit

1 = Bus line is sampled three times prior to the sample point 0 = Bus line is sampled once at the sample point

bit 5-3 SEG1PH2:SEG1PH0: Phase Segment 1 bits111 = Phase Segment 1 time = 8 x TQ 110 = Phase Segment 1 time = 7 x TQ 101 = Phase Segment 1 time = 6 x TQ 100 = Phase Segment 1 time = 5 x TQ 011 = Phase Segment 1 time = 4 x TQ 010 = Phase Segment 1 time = 3 x TQ 001 = Phase Segment 1 time = 2 x TQ 000 = Phase Segment 1 time = 1 x TQ

bit 2-0 PRSEG2:PRSEG0: Propagation Time Select bits111 = Propagation time = 8 x TQ 110 = Propagation time = 7 x TQ 101 = Propagation time = 6 x TQ 100 = Propagation time = 5 x TQ 011 = Propagation time = 4 x TQ 010 = Propagation time = 3 x TQ 001 = Propagation time = 2 x TQ 000 = Propagation time = 1 x TQ

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PIC18F6585/8585/6680/8680

REGISTER 23-54: BRGCON3: BAUD RATE CONTROL REGISTER 3 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

WAKDIS WAKFIL — — — SEG2PH2(1) SEG2PH1(1) SEG2PH0(1)

bit 7 bit 0

bit 7 WAKDIS: Wake-up Disable bit1 = Disable CAN bus activity wake-up feature0 = Enable CAN bus activity wake-up feature

bit 6 WAKFIL: Selects CAN bus Line Filter for Wake-up bit

1 = Use CAN bus line filter for wake-up 0 = CAN bus line filter is not used for wake-up


bit 2-0 SEG2PH2:SEG2PH0: Phase Segment 2 Time Select bits(1)

111 = Phase Segment 2 time = 8 x TQ 110 = Phase Segment 2 time = 7 x TQ 101 = Phase Segment 2 time = 6 x TQ 100 = Phase Segment 2 time = 5 x TQ 011 = Phase Segment 2 time = 4 x TQ 010 = Phase Segment 2 time = 3 x TQ 001 = Phase Segment 2 time = 2 x TQ 000 = Phase Segment 2 time = 1 x TQ

Note 1: Ignored if SEG2PHTS bit (BRGCON2<7>) is ‘0’.

Legend:

PIC18F6585/8585/6680/8680

23.2.5 CAN MODULE I/O CONTROL REGISTER

This register controls the operation of the CAN module’sI/O pins in relation to the rest of the microcontroller.

REGISTER 23-55: CIOCON: CAN I/O CONTROL REGISTERR/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0

TX2SRC TX2EN ENDRHI CANCAP — — — —

bit 7 bit 0

bit 7 TX2SRC: CANTX2 Pin Data Source bit

1 = CANTX2 pin will output the CAN clock0 = CANTX2 pin will output CANTX1

bit 6 TX2EN: CANTX2 Pin Enable bit1 = CANTX2 pin will output CANTX1 or CAN clock as selected by TX2SRC bit0 = CANTX2 pin will have digital I/O function

bit 5 ENDRHI: Enable Drive High bit(1)

1 = CANTX pin will drive VDD when recessive 0 = CANTX pin will be tri-state when recessive

bit 4 CANCAP: CAN Message Receive Capture Enable bit

1 = Enable CAN capture, CAN message receive signal replaces input on RC2/CCP1 0 = Disable CAN capture, RC2/CCP1 input to CCP1 module


Note 1: Always set this bit when using differential bus to avoid signal crosstalk in CANTXfrom other nearby pins.

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PIC18F6585/8585/6680/8680

23.2.6 CAN INTERRUPT REGISTERSThe registers in this section are the same as describedin Section 9.0 “Interrupts”. They are duplicated herefor convenience.

REGISTER 23-56: PIR3: PERIPHERAL INTERRUPT FLAG REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IRXIF WAKIF ERRIF TXB2IF/ TXBnIF

TXB1IF(1) TXB0IF(1) RXB1IF/ RXBnIF

RXB0IF/FIFOWMIF

bit 7 bit 0

bit 7 IRXIF: CAN Invalid Received Message Interrupt Flag bit1 = An invalid message has occurred on the CAN bus 0 = No invalid message on CAN bus

bit 6 WAKIF: CAN bus Activity Wake-up Interrupt Flag bit1 = Activity on CAN bus has occurred 0 = No activity on CAN bus

bit 5 ERRIF: CAN bus Error Interrupt Flag bit1 = An error has occurred in the CAN module (multiple sources) 0 = No CAN module errors

bit 4 When CAN is in Mode 0:TXB2IF: CAN Transmit Buffer 2 Interrupt Flag bit1 = Transmit Buffer 2 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 2 has not completed transmission of a messageWhen CAN is in Mode 1 or 2:TXBnIF: Any Transmit Buffer Interrupt Flag bit1 = One or more transmit buffers has completed transmission of a message and may be reloaded 0 = No transmit buffer is ready for reload





bit 1 When CAN is in Mode 0:RXB1IF: CAN Receive Buffer 1 Interrupt Flag bit1 = Receive Buffer 1 has received a new message 0 = Receive Buffer 1 has not received a new message When CAN is in Mode 1 or 2:RXBnIF: Any Receive Buffer Interrupt Flag bit1 = One or more receive buffers has received a new message 0 = No receive buffer has received a new message

bit 0 When CAN is in Mode 0:RXB0IF: CAN Receive Buffer 0 Interrupt Flag bit1 = Receive Buffer 0 has received a new message 0 = Receive Buffer 0 has not received a new messageWhen CAN is in Mode 1:Unimplemented: Read as ‘0’When CAN is in Mode 2:FIFOWMIF: FIFO Watermark Interrupt Flag bit1 = FIFO high watermark is reached 0 = FIFO high watermark is not reached




PIC18F6585/8585/6680/8680

REGISTER 23-57: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IRXIE WAKIE ERRIE TXB2IE/ TXBnIE

TXB1IE(1) TXB0IE(1) RXB1IE/ RXBnIE

RXB0IE/FIFOWMIE

bit 7 bit 0

bit 7 IRXIE: CAN Invalid Received Message Interrupt Enable bit1 = Enable invalid message received interrupt 0 = Disable invalid message received interrupt

bit 6 WAKIE: CAN bus Activity Wake-up Interrupt Enable bit

1 = Enable bus activity wake-up interrupt 0 = Disable bus activity wake-up interrupt

bit 5 ERRIE: CAN bus Error Interrupt Enable bit1 = Enable CAN bus error interrupt 0 = Disable CAN bus error interrupt

bit 4 When CAN is in Mode 0:TXB2IE: CAN Transmit Buffer 2 Interrupt Enable bit1 = Enable Transmit Buffer 2 interrupt 0 = Disable Transmit Buffer 2 interrupt

When CAN is in Mode 1 or 2:TXBnIE: CAN Transmit Buffer Interrupts Enable bit1 = Enable transmit buffer interrupt; individual interrupt is enabled by TXBIE and BIE0 0 = Disable all transmit buffer interrupts





bit 1 When CAN is in Mode 0:RXB1IE: CAN Receive Buffer 1 Interrupt Enable bit1 = Enable Receive Buffer 1 interrupt 0 = Disable Receive Buffer 1 interrupt

When CAN is in Mode 1 or 2:RXBnIE: CAN Receive Buffer Interrupts Enable bit1 = Enable receive buffer interrupt; individual interrupt is enabled by BIE0 0 = Disable all receive buffer interrupts

bit 0 When CAN is in Mode 0:RXB0IE: CAN Receive Buffer 0 Interrupt Enable bit

1 = Enable Receive Buffer 0 interrupt 0 = Disable Receive Buffer 0 interrupt

When CAN is in Mode 1:Unimplemented: Read as ‘0’When CAN is in Mode 2:FIFOWMIE: FIFO Watermark Interrupt Enable bit1 = Enable FIFO watermark interrupt 0 = Disable FIFO watermark interrupt


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PIC18F6585/8585/6680/8680

REGISTER 23-58: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

IRXIP WAKIP ERRIP TXB2IP/ TXBnIP

TXB1IP(1) TXB0IP(1) RXB1IP/RXBnIP

RXB0IP/FIFOWMIP

bit 7 bit 0

bit 7 IRXIP: CAN Invalid Received Message Interrupt Priority bit1 = High priority 0 = Low priority

bit 6 WAKIP: CAN bus Activity Wake-up Interrupt Priority bit


bit 5 ERRIP: CAN bus Error Interrupt Priority bit1 = High priority 0 = Low priority

bit 4 When CAN is in Mode 0:TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit1 = High priority 0 = Low priority

When CAN is in Mode 1 or 2:TXBnIP: CAN Transmit Buffer Interrupt Priority bit1 = High priority 0 = Low priority





bit 1 When CAN is in Mode 0:RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit1 = High priority 0 = Low priority

When CAN is in Mode 1 or 2:RXBnIP: CAN Receive Buffer Interrupts Priority bit1 = High priority 0 = Low priority

bit 0 When CAN is in Mode 0:RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit


When CAN is in Mode 1:Unimplemented: Read as ‘0’When CAN is in Mode 2:FIFOWMIP: FIFO Watermark Interrupt Priority bit1 = High priority 0 = Low priority


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PIC18F6585/8585/6680/8680

REGISTER 23-59: TXBIE: TRANSMIT BUFFERS INTERRUPT ENABLE REGISTER(1)

REGISTER 23-60: BIE0: BUFFER INTERRUPT ENABLE REGISTER 0(1)

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0

— — — TXB2IE TXB1IE TXB0IE — —

bit 7 bit 0


bit 4-2 TX2BIE:TXB0IE: Transmit Buffer 2-0 Interrupt Enable bit(2)

1 = Transmit buffer interrupt is enabled0 = Transmit buffer interrupt is disabled



2: TXBIE in PIE3 register must be set to get an interrupt.

Legend:




B5IE B4IE B3IE B2IE B1IE B0IE RXB1IE RXB0IE

bit 7 bit 0

bit 7-2 B5IE:B0IE: Programmable Transmit/Receive Buffer 5-0 Interrupt Enable bit(2)

1 = Interrupt is enabled0 = Interrupt is disabled

bit 1-0 RXB1IE:RXB0IE: Dedicated Receive Buffer 1-0 Interrupt Enable bit(2)

1 = Interrupt is enabled0 = Interrupt is disabled


2: Either TXBIE or RXBIE in PIE3 register must be set to get an interrupt.

Legend:




PIC18F6585/8585/6680/8680

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TABLE 23-1: CAN CONTROLLER REGISTER MAP

Address(1) Name Address Name Address Name Address Name

F7Fh SPBRGH(3) F5Fh CANCON_RO0 F3Fh CANCON_RO2 F1Fh RXM1EID

F7Eh BAUDCON(3) F5Eh CANSTAT_RO0 F3Eh CANSTAT_RO2 F1Eh RXM1EID

F7Dh —(4) F5Dh RXB1D7 F3Dh TXB1D7 F1Dh RXM1SID

F7Ch —(4) F5Ch RXB1D6 F3Ch TXB1D6 F1Ch RXM1SID

F7Bh —(4) F5Bh RXB1D5 F3Bh TXB1D5 F1Bh RXM0EID

F7Ah —(4) F5Ah RXB1D4 F3Ah TXB1D4 F1Ah RXM0EID

F79h ECCP1DEL(3) F59h RXB1D3 F39h TXB1D3 F19h RXM0SID

F78h —(4) F58h RXB1D2 F38h TXB1D2 F18h RXM0SID

F77h ECANCON F57h RXB1D1 F37h TXB1D1 F17h RXF5EID

F76h TXERRCNT F56h RXB1D0 F36h TXB1D0 F16h RXF5EID

F75h RXERRCNT F55h RXB1DLC F35h TXB1DLC F15h RXF5SID

F74h COMSTAT F54h RXB1EIDL F34h TXB1EIDL F14h RXF5SID

F73h CIOCON F53h RXB1EIDH F33h TXB1EIDH F13h RXF4EID

F72h BRGCON3 F52h RXB1SIDL F32h TXB1SIDL F12h RXF4EID

F71h BRGCON2 F51h RXB1SIDH F31h TXB1SIDH F11h RXF4SID

F70h BRGCON1 F50h RXB1CON F30h TXB1CON F10h RXF4SID

F6Fh CANCON F4Fh CANCON_RO1(2) F2Fh CANCON_RO3(2) F0Fh RXF3EID

F6Eh CANSTAT F4Eh CANSTAT_RO1(2) F2Eh CANSTAT_RO3(2) F0Eh RXF3EID

F6Dh RXB0D7 F4Dh TXB0D7 F2Dh TXB2D7 F0Dh RXF3SID

F6Ch RXB0D6 F4Ch TXB0D6 F2Ch TXB2D6 F0Ch RXF3SID

F6Bh RXB0D5 F4Bh TXB0D5 F2Bh TXB2D5 F0Bh RXF2EID

F6Ah RXB0D4 F4Ah TXB0D4 F2Ah TXB2D4 F0Ah RXF2EID

F69h RXB0D3 F49h TXB0D3 F29h TXB2D3 F09h RXF2SID

F68h RXB0D2 F48h TXB0D2 F28h TXB2D2 F08h RXF2SID

F67h RXB0D1 F47h TXB0D1 F27h TXB2D1 F07h RXF1EID

F66h RXB0D0 F46h TXB0D0 F26h TXB2D0 F06h RXF1EID

F65h RXB0DLC F45h TXB0DLC F25h TXB2DLC F05h RXF1SID

F64h RXB0EIDL F44h TXB0EIDL F24h TXB2EIDL F04h RXF1SID

F63h RXB0EIDH F43h TXB0EIDH F23h TXB2EIDH F03h RXF0EID

F62h RXB0SIDL F42h TXB0SIDL F22h TXB2SIDL F02h RXF0EID

F61h RXB0SIDH F41h TXB0SIDH F21h TXB2SIDH F01h RXF0SID

F60h RXB0CON F40h TXB0CON F20h TXB2CON F00h RXF0SID

Note 1: Shaded registers are available in Access Bank low area while the rest are available in Bank 15.2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for

each instance of the controller register due to the Microchip header file requirement.3: These registers are not CAN registers.4: Unimplemented registers are read as ‘0’.


PIC18F6585/8585/6680/8680

EFFh —(4) EDFh —(4) EBFh —(4) E9Fh —(4)

EFEh —(4) EDEh —(4) EBEh —(4) E9Eh —(4)

EFDh —(4) EDDh —(4) EBDh —(4) E9Dh —(4)

EFCh —(4) EDCh —(4) EBCh —(4) E9Ch —(4)

EFBh —(4) EDBh —(4) EBBh —(4) E9Bh —(4)

EFAh —(4) EDAh —(4) EBAh —(4) E9Ah —(4)

EF9h —(4) ED9h —(4) EB9h —(4) E99h —(4)

EF8h —(4) ED8h —(4) EB8h —(4) E98h —(4)

EF7h —(4) ED7h —(4) EB7h —(4) E97h —(4)

EF6h —(4) ED6h —(4) EB6h —(4) E96h —(4)

EF5h —(4) ED5h —(4) EB5h —(4) E95h —(4)

EF4h —(4) ED4h —(4) EB4h —(4) E94h —(4)

EF3h —(4) ED3h —(4) EB3h —(4) E93h —(4)

EF2h —(4) ED2h —(4) EB2h —(4) E92h —(4)

EF1h —(4) ED1h —(4) EB1h —(4) E91h —(4)

EF0h —(4) ED0h —(4) EB0h —(4) E90h —(4)

EEFh —(4) ECFh —(4) EAFh —(4) E8Fh —(4)

EEEh —(4) ECEh —(4) EAEh —(4) E8Eh —(4)

EEDh —(4) ECDh —(4) EADh —(4) E8Dh —(4)

EECh —(4) ECCh —(4) EACh —(4) E8Ch —(4)

EEBh —(4) ECBh —(4) EABh —(4) E8Bh —(4)

EEAh —(4) ECAh —(4) EAAh —(4) E8Ah —(4)

EE9h —(4) EC9h —(4) EA9h —(4) E89h —(4)

EE8h —(4) EC8h —(4) EA8h —(4) E88h —(4)

EE7h —(4) EC7h —(4) EA7h —(4) E87h —(4)

EE6h —(4) EC6h —(4) EA6h —(4) E86h —(4)

EE5h —(4) EC5h —(4) EA5h —(4) E85h —(4)

EE4h —(4) EC4h —(4) EA4h —(4) E84h —(4)

EE3h —(4) EC3h —(4) EA3h —(4) E83h —(4)

EE2h —(4) EC2h —(4) EA2h —(4) E82h —(4)

EE1h —(4) EC1h —(4) EA1h —(4) E81h —(4)

EE0h —(4) EC0h —(4) EA0h —(4) E80h —(4)

TABLE 23-1: CAN CONTROLLER REGISTER MAP (CONTINUED)





PIC18F6585/8585/6680/8680

E7Fh CANCON_RO4(2) E5Fh CANCON_RO6(2) E3Fh CANCON_RO8(2) E1Fh —(4)

E7Eh CANSTAT_RO4(2) E5Eh CANSTAT_RO6(2) E3Eh CANSTAT_RO8(2) E1Eh —(4)





E79h B5D3 E59h B3D3 E39h B1D3 E19h —(4)

E78h B5D2 E58h B3D2 E38h B1D2 E18h —(4)

E77h B5D1 E57h B3D1 E37h B1D1 E17h —(4)

E76h B5D0 E56h B3D0 E36h B1D0 E16h —(4)













E69h B4D3 E49h B2D3 E29h B0D3 E09h —(4)

E68h B4D2 E48h B2D2 E28h B0D2 E08h —(4)

E67h B4D1 E47h B2D1 E27h B0D1 E07h —(4)

E66h B4D0 E46h B2D0 E26h B0D0 E06h —(4)












PIC18F6585/8585/6680/8680

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DFFh —(4) DDFh —(4) DBFh —(4) D9Fh —(4)

DFEh —(4) DDEh —(4) DBEh —(4) D9Eh —(4)

DFDh —(4) DDDh —(4) DBDh —(4) D9Dh —(4)

DFCh TXBIE DDCh —(4) DBCh —(4) D9Ch —(4)

DFBh —(4) DDBh —(4) DBBh —(4) D9Bh —(4)

DFAh BIE0 DDAh —(4) DBAh —(4) D9Ah —(4)

DF9h —(4) DD9h —(4) DB9h —(4) D99h —(4)

DF8h BSEL0 DD8h SDFLC DB8h —(4) D98h —(4)

DF7h —(4) DD7h —(4) DB7h —(4) D97h —(4)

DF6h —(4) DD6h —(4) DB6h —(4) D96h —(4)



DF3h MSEL3 DD3h —(4) DB3h —(4) D93h RXF15EID

DF2h MSEL2 DD2h —(4) DB2h —(4) D92h RXF15EID

DF1h MSEL1 DD1h —(4) DB1h —(4) D91h RXF15SID

DF0h MSEL0 DD0h —(4) DB0h —(4) D90h RXF15SID

DEFh —(4) DCFh —(4) DAFh —(4) D8Fh —(4)

DEEh —(4) DCEh —(4) DAEh —(4) D8Eh —(4)

DEDh —(4) DCDh —(4) DADh —(4) D8Dh —(4)

DECh —(4) DCCh —(4) DACh —(4) D8Ch —(4)

DEBh —(4) DCBh —(4) DABh —(4) D8Bh RXF14EID

DEAh —(4) DCAh —(4) DAAh —(4) D8Ah RXF14EID

DE9h —(4) DC9h —(4) DA9h —(4) D89h RXF14SID

DE8h —(4) DC8h —(4) DA8h —(4) D88h RXF14SID

DE7h RXFBCON7 DC7h —(4) DA7h —(4) D87h RXF13EID


DE5h RXFBCON5 DC5h —(4) DA5h —(4) D85h RXF13SID











PIC18F6585/8585/6680/8680


Address(1) Name

D7Fh —(4)

D7Eh —(4)

D7Dh —(4)

D7Ch —(4)

D7Bh RXF11EIDL

D7Ah RXF11EIDH

D79h RXF11SIDL

D78h RXF11SIDH

D77h RXF10EIDL

D76h RXF10EIDH

D75h RXF10SIDL

D74h RXF10SIDH

D73h RXF9EIDL

D72h RXF9EIDH

D71h RXF9SIDL

D70h RXF9SIDH

D6Fh —(4)

D6Eh —(4)

D6Dh —(4)

D6Ch —(4)

D6Bh RXF8EIDL

D6Ah RXF8EIDH

D69h RXF8SIDL

D68h RXF8SIDH

D67h RXF7EIDL

D66h RXF7EIDH

D65h RXF7SIDL

D64h RXF7SIDH

D63h RXF6EIDL

D62h RXF6EIDH

D61h RXF6SIDL

D60h RXF6SIDH

Note 1: Shaded registers are available in Access Bank low area while the rest are available in Bank 15.

2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the controller register due to the Microchip header file requirement.

3: These registers are not CAN registers.4: Unimplemented registers are read as ‘0’.


PIC18F6585/8585/6680/8680

23.3 CAN Modes of Operation

The PIC18F6585/8585/6680/8680 has six main modesof operation:

• Configuration mode• Disable mode

• Normal Operation mode• Listen Only mode• Loopback mode

• Error Recognition mode

All modes, except Error Recognition, are requested bysetting the REQOP bits (CANCON<7:5>); Error Recog-nition is requested through the RXM bits of the ReceiveBuffer register(s). Entry into a mode is Acknowledgedby monitoring the OPMODE bits.

When changing modes, the mode will not actuallychange until all pending message transmissions arecomplete. Because of this, the user must verify that thedevice has actually changed into the requested modebefore further operations are executed.

23.3.1 CONFIGURATION MODE

The CAN module must be initialized before theactivation. This is only possible if the module is in theConfiguration mode. The Configuration mode isrequested by setting the REQOP2 bit. Only when thestatus bit, OPMODE2, has a high level can the initial-ization be performed. Once in Configuration mode,registers such as baud rate control, acceptance mask/filter and ECAN mode selection can be modified. A newECAN mode selection does not take into effect untilConfiguration mode is exited. The module is activatedby setting the REQOP control bits to zero.

The module will protect the user from accidentallyviolating the CAN protocol through programmingerrors. All registers which control the configuration ofthe module can not be modified while the module isonline. The CAN module will not be allowed to enter theConfiguration mode while a transmission or receptionis taking place. The CAN module will also not beallowed, if the CANRX pin is low (i.e., the CAN bus isbusy). The CAN module waits for 11 recessive bits onthe CAN bus (bus Idle condition) before switching toConfiguration mode. The Configuration mode servesas a lock to protect the following registers:

• Configuration registers • Functional Mode Selection registers

• Bit Timing registers • Identifier Acceptance Filter registers • Identifier Acceptance Mask registers

• Filter and Mask Control registers• Mask Selection registers

In the Configuration mode, the module will not transmitor receive. The error counters are cleared and the inter-rupt flags remain unchanged. The programmer willhave access to configuration registers that are accessrestricted in other modes.

23.3.2 DISABLE MODE

In Disable mode, the module will not transmit orreceive. The module has the ability to set the WAKIF bitdue to bus activity; however, any pending interrupts willremain and the error counters will retain their value.

If REQOP<2:0> is set to ‘001’, the module will enter theModule Disable mode. This mode is similar to disablingother peripheral modules by turning off the moduleenables. This causes the module internal clock to stopunless the module is active (i.e., receiving or transmit-ting a message). If the module is active, the module willwait for 11 recessive bits on the CAN bus, detect thatcondition as an Idle bus, then accept the moduledisable command. OPMODE<2:0> = 001 indicateswhether the module successfully went into ModuleDisable mode.

The WAKIE interrupt is the only module interrupt that isstill active in the Module Disable mode. If wake-up fromCAN bus activity is required, the CAN module must beput into Disable mode before putting the core to Sleep.If the WAKDIS is cleared and WAKIE is set, the proces-sor will receive an interrupt whenever the moduledetects recessive to dominant transition. On wake-up,the module will automatically be set to the previousmode of operation. For example, if the module wasswitched from Normal to Disable mode on bus activitywake-up, the module will automatically enter intoNormal mode and the first message that caused themodule to wake-up is lost. The module will not gener-ate any error frame. Firmware logic must detect thiscondition and make sure that retransmission isrequested. If the processor receives a wake-up inter-rupt while it is sleeping, more than one message mayget lost. The actual number of messages lost woulddepend on the processor oscillator start-up time andincoming message bit rate.

The I/O pins will revert to normal I/O function when themodule is in the Module Disable mode.

Note: CAN module must be put in Disable orConfiguration mode prior to putting theprocessor to sleep. Failure to do that mayput the CAN module in indeterminatestate.

PIC18F6585/8585/6680/8680

23.3.3 NORMAL MODE

This is the standard operating mode of thePIC18F6585/8585/6680/8680 devices. In this mode,the device actively monitors all bus messages and gen-erates Acknowledge bits, error frames, etc. This is alsothe only mode in which the PIC18F6585/8585/6680/8680 devices will transmit messages over the CANbus.

23.3.4 LISTEN ONLY MODE

Listen Only mode provides a means for thePIC18F6585/8585/6680/8680 devices to receive allmessages, including messages with errors. This modecan be used for bus monitor applications or fordetecting the baud rate in ‘hot plugging’ situations. Forauto-baud detection, it is necessary that there are atleast two other nodes which are communicating witheach other. The baud rate can be detected empiricallyby testing different values until valid messages arereceived. The Listen Only mode is a silent mode,meaning no messages will be transmitted while in thisstate, including error flags or Acknowledge signals. Thefilters and masks can be used to allow only particularmessages to be loaded into the receive registers, or thefilter masks can be set to all zeros to allow a messagewith any identifier to pass. The error counters are resetand deactivated in this state. The Listen Only mode isactivated by setting the mode request bits in theCANCON register.

23.3.5 LOOPBACK MODE

This mode will allow internal transmission of messagesfrom the transmit buffers to the receive buffers withoutactually transmitting messages on the CAN bus. Thismode can be used in system development and testing.In this mode, the ACK bit is ignored and the device willallow incoming messages from itself, just as if theywere coming from another node. The Loopback modeis a silent mode, meaning no messages will be trans-mitted while in this state, including error flags orAcknowledge signals. The CANTX pin will revert to portI/O while the device is in this mode. The filters andmasks can be used to allow only particular messagesto be loaded into the receive registers. The masks canbe set to all zeros to provide a mode that accepts allmessages. The Loopback mode is activated by settingthe mode request bits in the CANCON register.

23.3.6 ERROR RECOGNITION MODE

The module can be set to ignore all errors and receiveany message. In functional Mode 0, the Error Recogni-tion mode is activated by setting the RXM<1:0> bits inthe RXBnCON registers to ‘11’. In this mode, the datawhich is in the message assembly buffer until the errortime, is copied in the receive buffer and can be read viathe CPU interface.

23.4 CAN Module Functional Modes

In addition to CAN modes of operation, the ECANmodule offers a total of three functional modes. Each ofthese modes are identified as Mode 0, Mode 1 andMode 2.

23.4.1 MODE 0 – LEGACY MODE

Mode 0 is designed to be fully compatible with CANmodules used in PIC18CXX8 and PIC18FXX8 devices.This is the default mode of operation on all Resetconditions. As a result, module code written for thePIC18XX8 CAN module may be used on the ECANmodule without any code changes.

The following is the list of resources available in Mode 0:

• Three transmit buffers: TXB0, TXB1 and TXB2• Two receive buffers: RXB0 and RXB1• Two acceptance masks, one for each receive

buffer: RXM0, RXM1• Six acceptance filters, 2 for RXB0 and 4 for RXB1:

RXF0, RXF1, RXF2, RXF3, RXF4, RXF5

23.4.2 MODE 1 – ENHANCED LEGACY MODE

Mode 1 is similar to Mode 0, with the exception thatmore resources are available in Mode 1. There are16 acceptance filters and two Acceptance Mask regis-ters. Acceptance Filter 15 can be used as either anacceptance filter or an Acceptance Mask register. Inaddition to three transmit and two receive buffers, thereare six more message buffers. One or more of theseadditional buffers can be programmed as transmit orreceive buffers. These additional buffers can also beprogrammed to automatically handle RTR messages.

Fourteen of 16 Acceptance Filter registers can bedynamically associated to any receive buffer andAcceptance Mask register. This capability can be usedto associate more than one filter to any one buffer.

PIC18F6585/8585/6680/8680

When a receive buffer is programmed to use standardidentifier messages, part of the full Acceptance Filterregister can be used as data byte filter. The length ofdata byte filter is programmable from 0 to 18 bits. Thisfunctionality simplifies implementation of high-levelprotocols, such as DeviceNet.


• Three transmit buffers: TXB0, TXB1 and TXB2

• Two receive buffers: RXB0 and RXB1• Six buffers programmable as TX or RX: B0-B5• Automatic RTR handling on B0-B5

• Sixteen dynamically assigned acceptance filters: RXF0-RXF15

• Two dedicated Acceptance Mask registers; RXF15 programmable as third mask: RXM0-RXM1, RXF15

• Programmable data filter on standard identifier messages: SDFLC

23.4.3 MODE 2 – ENHANCED FIFO MODE

In Mode 2, two or more receive buffers are used to formthe receive FIFO (First In First Out) buffer. There is noone-to-one relation between the receive buffer andAcceptance Filter registers. Any filter that is enabledand linked to any FIFO receive buffer can generateacceptance and cause FIFO to be updated.

FIFO length is user programmable, from 2-8 buffersdeep. FIFO length is determined by the very firstprogrammable buffer that is configured as a transmitbuffer. For example, if Buffer 2 (B2) is programmed asa transmit buffer, FIFO consists of RXB0, RXB1, B0and B1 – creating a FIFO length of 4. If all programma-ble buffers are configured as receive buffers, FIFO willhave the maximum length of 8.


• Three transmit buffers: TXB0, TXB1 and TXB2• Two receive buffers: RXB0 and RXB1

• Six buffers programmable as TX or RX; receive buffers form FIFO: B0-B5

• Automatic RTR handling on B0-B5• Sixteen acceptance filters: RXF0-RXF15• Two dedicated Acceptance Mask registers;

RXF15 programmable as third mask: RXM0-RXM1, RXF15

• Programmable data filter on standard identifier messages: SDFLC, useful for DeviceNet protocol

23.5 CAN Message Buffers

23.5.1 DEDICATED TRANSMIT BUFFERS

The PIC18F6585/8585/6680/8680 devices implementthree dedicated transmit buffers – TXB0, TXB1 andTXB2. Each of these buffers occupies 14 bytes ofSRAM and are mapped into the SFR memory map.These are the only transmit buffers available inMode 0. Mode 1 and 2 may access these and otheradditional buffers.

Each transmit buffer contains one Control register(TXBnCON), four Identifier registers (TXBnSIDL,TXBnSIDH, TXBnEIDL, TXBnEIDH), one Data LengthCount register (TXBnDLC) and eight Data Byteregisters (TXBnDm).

23.5.2 DEDICATED RECEIVE BUFFERS

The PIC18F6585/8585/6680/8680 devices implementtwo dedicated receive buffers – RXB0 and RXB1. Eachof these buffers occupies 14 bytes of SRAM and aremapped into SFR memory map. These are the onlyreceive buffers available in Mode 0. Mode 1 and 2 mayaccess these and other additional buffers.

Each receive buffer contains one Control register(RXBnCON), four Identifier registers (RXBnSIDL,RXBnSIDH, RXBnEIDL, RXBnEIDH), one Data LengthCount register (RXBnDLC) and eight Data Byteregisters (RXBnDm).

There is also a separate Message Assembly Buffer(MAB) which acts as an additional receive buffer. MABis always committed to receiving the next messagefrom the bus and is not directly accessible to user firm-ware. The MAB assembles all incoming messages oneby one. A message is transferred to appropriatereceive buffers only if the corresponding acceptancefilter criteria is met.


PIC18F6585/8585/6680/8680

23.5.3 PROGRAMMABLE TRANSMIT/RECEIVE BUFFERS

The ECAN module implements six new buffers: B0-B5.These buffers are individually programmable as eithertransmit or receive buffers. These buffers are availableonly in Mode 1 and 2. As with dedicated transmit andreceive buffers, each of these programmable buffersoccupies 14 bytes of SRAM and are mapped into SFRmemory map.

Each buffer contains one Control register (BnCON),four Identifier registers (BnSIDL, BnSIDH, BnEIDL,BnEIDH), one Data Length Count register (BnDLC)and eight Data Byte registers (BnDm). Each of theseregisters contains two sets of control bits. Dependingon whether the buffer is configured as transmit orreceive, one would use the corresponding control bitset. By default, all buffers are configured as receivebuffers. Each buffer can be individually configured astransmit or receive buffers by setting the correspondingTXENn bit in the BSEL0 register.

When configured as transmit buffers, user firmwaremay access transmit buffers in any order similar toaccessing dedicated transmit buffers. In receive config-uration, with Mode 1 enabled, user firmware may alsoaccess receive buffers in any order required. But inMode 2, all receive buffers are combined to form a sin-gle FIFO. Actual FIFO length is programmable by userfirmware. Access to FIFO must be done through theFIFO pointer bits (FP<4:0>) in the CANCON register. Itmust be noted that there is no hardware protectionagainst out of order FIFO reads.

23.5.4 PROGRAMMABLE AUTO-RTR BUFFERS

In Mode 1 and 2, any of six programmable transmit/receive buffers may be programmed to automaticallyrespond to predefined RTR messages without userfirmware intervention. Automatic RTR handling isenabled by setting the TXnEN bit in the BSEL0 registerand the RTREN bit in the BnCON register. After thissetup, when an RTR request is received, the TXREQbit is automatically set and current buffer content isautomatically queued for transmission as a RTRresponse. As with all transmit buffers, once the TXREQbit is set, buffer registers become read-only and anywrites to them will be ignored.

The following outlines the steps required toautomatically handle RTR messages:

1. Set buffer to Transmit mode by setting TXnENbit to ‘1’ in BSEL0 register.

2. At least one acceptance filter must be associ-ated with this buffer and preloaded withexpected RTR identifier.

3. Bit RTREN in BnCON register must be set to ‘1’.

4. Buffer must be preloaded with the data to besent as a RTR response.

Normally, user firmware will keep Buffer Data registersup to date. If firmware attempts to update buffer whilean automatic RTR response is in process oftransmission, all writes to buffers are ignored.

23.6 CAN Message Transmission

23.6.1 INITIATING TRANSMISSION

For the MCU to have write access to the messagebuffer, the TXREQ bit must be clear, indicating that themessage buffer is clear of any pending message to betransmitted. At a minimum, the SIDH, SIDL, and DLCregisters must be loaded. If data bytes are present inthe message, the data registers must also be loaded. Ifthe message is to use extended identifiers, theEIDH:EIDL registers must also be loaded and theEXIDE bit set.

To initiate message transmission, the TXREQ bit mustbe set for each buffer to be transmitted. When TXREQis set, the TXABT, TXLARB and TXERR bits will becleared. To successfully complete the transmission,there must be at least one node with matching baudrate on the network.

Setting the TXREQ bit does not initiate a messagetransmission, it merely flags a message buffer as readyfor transmission. Transmission will start when thedevice detects that the bus is available. The device willthen begin transmission of the highest priority messagethat is ready.

When the transmission has completed successfully, theTXREQ bit will be cleared, the TXBnIF bit will be set, andan interrupt will be generated if the TXBnIE bit is set.

If the message transmission fails, the TXREQ willremain set, indicating that the message is still pendingfor transmission and one of the following condition flagswill be set. If the message started to transmit butencountered an error condition, the TXERR and theIRXIF bits will be set and an interrupt will be generated.If the message lost arbitration, the TXLARB bit will beset.

PIC18F6585/8585/6680/8680

23.6.2 ABORTING TRANSMISSION

The MCU can request to abort a message by clearingthe TXREQ bit associated with the corresponding mes-sage buffer (TXBnCON<3> or BnCON<3>). Setting theABAT bit (CANCON<4>) will request an abort of allpending messages. If the message has not yet startedtransmission or if the message started but is inter-rupted by loss of arbitration or an error, the abort will beprocessed. The abort is indicated when the modulesets the TXABT bit for the corresponding buffer(TXBnCON<6> or BnCON<6>). If the message hasstarted to transmit, it will attempt to transmit the currentmessage fully. If the current message is transmittedfully and is not lost to arbitration or an error, the TXABTbit will not be set because the message was transmit-ted successfully. Likewise, if a message is beingtransmitted during an abort request and the message islost to arbitration or an error, the message will not beretransmitted and the TXABT bit will be set, indicatingthat the message was successfully aborted.

Once an abort is requested by setting ABAT or TXABTbits, it cannot be cleared to cancel the abort request.Only CAN module hardware or a POR condition canclear it.

23.6.3 TRANSMIT PRIORITY

Transmit priority is a prioritization within thePIC18F6585/8585/6680/8680 devices of the pendingtransmittable messages. This is independent from andnot related to any prioritization implicit in the messagearbitration scheme built into the CAN protocol. Prior tosending the SOF, the priority of all buffers that arequeued for transmission is compared. The transmitbuffer with the highest priority will be sent first. If morethan one buffer has the same priority setting, the mes-sage is transmitted in the order of TXB2, TXB1, TXB0,B5, B4, B3, B2, B1, B0. There are four levels of transmitpriority. If TXP bits for a particular message buffer areset to ‘11’, that buffer has the highest possible priority.If TXP bits for a particular message buffer are ‘00’, thatbuffer has the lowest possible priority.

FIGURE 23-2: TRANSMIT BUFFERS

TX

RE

Q

TXB0

TX

AB

T

TX

LAR

B

TX

ER

R

TX

B0I

F

ME

SS

AG

E

MessageQueueControl

Transmit Byte Sequencer

TX

RE

Q

TXB1

TX

AB

T

TX

LAR

B

TX

ER

R

TX

B1I

F

ME

SS

AG

E

TX

RE

Q

TXB2

TX

AB

T

TX

LAR

B

TX

ER

R

TX

B2I

F

ME

SS

AG

E

ME

SS

AG

E

TX

B2I

F

TX

RE

Q

TX

AB

T

TX

LAR

B

TX

ER

R

TXB3-TXB8

PIC18F6585/8585/6680/8680

23.7 Message Reception

23.7.1 RECEIVING A MESSAGE

Of all receive buffers, the MAB is always committed toreceiving the next message from the bus. The MCUcan access one buffer while the other buffer is availablefor message reception, or holding a previously receivedmessage.

When a message is moved into either of the receivebuffers, the associated RXFUL bit is set. This bit mustbe cleared by the MCU when it has completed process-ing the message in the buffer in order to allow a newmessage to be received into the buffer. This bitprovides a positive lockout to ensure that the firmwarehas finished with the message before the moduleattempts to load a new message into the receive buffer.If the receive interrupt is enabled, an interrupt will begenerated to indicate that a valid message has beenreceived.

Once a message is loaded into any matching buffer,user firmware may determine exactly what filter causedthis reception by checking the filter hit bits in theRXBnCON or BnCON registers. In Mode 0, FILHIT<3:0>of RXBnCON serve as filter hit bits. In Mode 1 and 2,FILHIT<4:0> of BnCON serve as filter hit bits. The sameregisters also indicate whether the current message isRTR frame or not. A received message is considered astandard identifier message if the EXID bit in RXBnSIDLor the BnSIDL register is cleared. Conversely, a setEXID bit indicates an extended identifier message. If thereceived message is a standard identifier message, userfirmware needs to read the SIDL and SIDH registers. Inthe case of an extended identifier message, firmwareshould read the SIDL, SIDH, EIDL and EIDH registers. Ifthe RXBnDLC or BnDLC register contain non-zero datacount, user firmware should also read the correspondingnumber of data bytes by accessing the RXBnDm orBnDm registers. When a received message is RTR andif the current buffer is not configured for automatic RTRhandling, user firmware must take appropriate actionand respond manually.

Each receive buffer contains RXM bits to set specialReceive modes. In Mode 0, RXM<1:0> bits inRXBnCON define a total of four Receive modes. InMode 1 and 2, RXM1 bit in combination with the EXIDmask and filter bit define the same four Receivemodes. Normally, these bits are set to ‘00’ to enablereception of all valid messages as determined by theappropriate acceptance filters. In this case, the deter-mination of whether or not to receive standard orextended messages is determined by the EXIDE bit inthe Acceptance Filter register. In Mode 0, if the RXMbits are set to ‘01’ or ‘10’, the receiver will accept onlymessages with standard or extended identifiers,respectively. If an acceptance filter has the EXIDE bitset such that it does not correspond with the RXMmode, that acceptance filter is rendered useless. InMode 1 and 2, setting EXID in the SIDL Mask registerwill ensure that only standard or extended identifiersare received. These two modes of RXM bits can beused in systems where it is known that only standard orextended messages will be on the bus. If the RXM bitsare set to ‘11’ (RXM1 = 1 in Mode 1 and 2), the bufferwill receive all messages regardless of the values ofthe acceptance filters. Also, if a message has an errorbefore the end of frame, that portion of the messageassembled in the MAB before the error frame, will beloaded into the buffer. This mode may serve as a valu-able debugging tool for a given CAN network. It shouldnot be used in an actual system environment as theactual system will always have some bus errors and allnodes on the bus are expected to ignore them.

In Mode 1 and 2, when a programmable buffer isconfigured as a transmit buffer and one or more accep-tance filters are associated with it, all incoming mes-sages matching this acceptance filter criteria will bediscarded. To avoid this scenario, user firmware mustmake sure that there are no acceptance filters associ-ated with a buffer configured as a transmit buffer.

23.7.2 RECEIVE PRIORITY

When in Mode 0, RXB0 is the higher priority buffer andhas two message acceptance filters associated with it.RXB1 is the lower priority buffer and has four acceptancefilters associated with it. The lower number of acceptancefilters makes the match on RXB0 more restrictive andimplies a higher priority for that buffer. Additionally, theRXB0CON register can be configured such that if RXB0contains a valid message and another valid message isreceived, an overflow error will not occur and the newmessage will be moved into RXB1 regardless of theacceptance criteria of RXB1. There are also twoprogrammable acceptance filter masks available, one foreach receive buffer (see Section 4.5).

Note: The entire contents of the MAB are movedinto the receive buffer once a message isaccepted. This means that regardless ofthe type of identifier (standard orextended) and the number of data bytesreceived, the entire receive buffer is over-written with the MAB contents. Therefore,the contents of all registers in the buffermust be assumed to have been modifiedwhen any message is received.

PIC18F6585/8585/6680/8680

In Mode 1 and 2, there are a total of 16 acceptance fil-ters available and each can be dynamically assigned toany of the receive buffers. A buffer with a lower numberhas higher priority. Given this, if an incoming messagematches with two or more receive buffer acceptancecriteria, the buffer with the lower number will be loadedwith that message.

23.7.3 ENHANCED FIFO MODE

When configured for Mode 2, two of the dedicatedreceive buffers, in combination with one or more pro-grammable transmit/receive buffers, are used to createa maximum of 8 buffers deep FIFO (First In First Out)buffer. In this mode, there is no direct correlationbetween filters and receive buffer registers. Any filterthat has been enabled can generate an acceptance.When a message has been accepted, it is stored in thenext available receive buffer register and an internalwrite pointer is incremented. The FIFO can be a maxi-mum of 8 buffers deep. The entire FIFO must consist ofcontiguous receive buffers. The FIFO head begins atRXB0 buffer and its tail spans toward B5. The maxi-mum length of the FIFO is limited by the presence orabsence of the first transmit buffer starting from B0. If abuffer is configured as a transmit buffer, the FIFOlength is reduced accordingly. For instance, if B3 isconfigured as transmit buffer, the actual FIFO will con-sist of RXB0, RXB1, B0, B1 and B2, a total of 5 buffers.If B0 is configured as a transmit buffer, the FIFO lengthwill be 2. If none of the programmable buffers are con-figured as a transmit buffer, the FIFO will be 8 buffersdeep. A system that requires more transmit buffersshould try to locate transmit buffers at the very end ofB0-B5 buffers to maximize available FIFO length.

When a message is received in FIFO mode, the Inter-rupt Flag Code bits (EICODE<4:0>) in the CANSTATregister will have a value of ‘10000’, indicating theFIFO has received a message. FIFO pointer bitsFP<3:0> in the CANCON register point to the bufferthat contains data not yet read. The FIFO pointer bits,in this sense, serve as the FIFO read pointer. The usershould use FP bits and read corresponding buffer data.When receive data is no longer needed, the RXFUL bitin the current buffer must be cleared, causing FP<3:0>to be updated by the module.

To determine whether FIFO is empty or not, the usermay use FP<3:0> bits to access RXFUL bit in the cur-rent buffer. If RXFUL is cleared, the FIFO is consideredto be empty. If it is set, the FIFO may contain one ormore messages. In Mode 2, the module also providesa bit called FIFO High Water Mark (FIFOWM) in theECANCON register. This bit can be used to cause aninterrupt whenever the FIFO contains only one or fourempty buffers. The FIFO high water mark interrupt canserve as an early warning to a full FIFO condition.

23.7.4 TIME-STAMPING

The CAN module can be programmed to generate atime-stamp for every message that is received. Whenenabled, the module generates a capture signal forCCP1, which in turn captures the value of either Timer1or Timer3. This value can be used as the messagetime-stamp.

To use the time-stamp capability, the CANCAP bit(CIOCAN<4>) must be set. This replaces the captureinput for CCP1 with the signal generated from the CANmodule. In addition, CCP1CON<3:0> must be set to‘0011’ to enable the CCP special event trigger for CANevents.

23.8 Message Acceptance Filters and Masks

The message acceptance filters and masks are used todetermine if a message in the message assemblybuffer should be loaded into any of the receive buffers.Once a valid message has been received into the MAB,the identifier fields of the message are compared to thefilter values. If there is a match, that message will beloaded into the appropriate receive buffer. The filtermasks are used to determine which bits in the identifierare examined with the filters. A truth table is shownbelow in Table 23-2 that indicates how each bit in theidentifier is compared to the masks and filters to deter-mine if a message should be loaded into a receivebuffer. The mask essentially determines which bits toapply the acceptance filters to. If any mask bit is set toa zero, then that bit will automatically be acceptedregardless of the filter bit.

TABLE 23-2: FILTER/MASK TRUTH TABLE

In Mode 0, acceptance filters RXF0 and RXF1 and filtermask RXM0 are associated with RXB0. Filters RXF2,RXF3, RXF4 and RXF5 and mask RXM1 areassociated with RXB1.

Mask bit n

Filter bit n

Message Identifier bit n001

Accept or Reject bit n

0 x x Accept

1 0 0 Accept

1 0 1 Reject

1 1 0 Reject

1 1 1 Accept

Legend: x = don’t care

PIC18F6585/8585/6680/8680

In Mode 1 and 2, there are an additional 10 acceptancefilters, RXF6-RXF15, creating a total of 16 availablefilters. RXF15 can be used either as an acceptancefilter or acceptance mask register. Each of theseacceptance filters can be individually enabled ordisabled by setting or clearing RXFENn bit in theRXFCONn register. Any of these 16 acceptance filterscan be dynamically associated with any of the receivebuffers. Actual association is made by setting appropri-ate bits in the RXFBCONn register. Each RXFBCONnregister contains a nibble for each filter. This nibble canbe used to associate a specific filter to any of availablereceive buffers. User firmware may associate morethan one filter to any one specific receive buffer.

In addition to dynamic filter to buffer association, inMode 1 and 2, each filter can also be dynamically asso-ciated to available acceptance mask registers. FILn_mbits in the MSELn register can be used to link a specificacceptance filter to an acceptance mask register. Aswith filter to buffer association, one can also associatemore than one mask to a specific acceptance filter.

When a filter matches and a message is loaded into thereceive buffer, the filter number that enabled themessage reception is loaded into the FILHIT bit(s). InMode 0 for RXB1, the RXB1CON register contains theFILHIT<2:0> bits. They are coded as follows:

• 101 = Acceptance Filter 5 (RXF5)

• 100 = Acceptance Filter 4 (RXF4)• 011 = Acceptance Filter 3 (RXF3)• 010 = Acceptance Filter 2 (RXF2)

• 001 = Acceptance Filter 1 (RXF1)• 000 = Acceptance Filter 0 (RXF0)

The coding of the RXB0DBEN bit enables these threebits to be used similarly to the FILHIT bits and to distin-guish a hit on filter RXF0 and RXF1, in either RXB0 orafter a rollover into RXB1.

• 111 = Acceptance Filter 1 (RXF1)• 110 = Acceptance Filter 0 (RXF0)

• 001 = Acceptance Filter 1 (RXF1)• 000 = Acceptance Filter 0

If the RXB0DBEN bit is clear, there are six codes cor-responding to the six filters. If the RXB0DBEN bit is set,there are six codes corresponding to the six filters plustwo additional codes corresponding to RXF0 and RXF1filters that rollover into RXB1.

In Mode 1 and 2, each buffer control register contains5 bits of filter hit bits FILHIT<4:0>. A binary value of ‘0’indicates a hit from RXF0 and 15 indicates RXF15.

If more than one acceptance filter matches, the FILHITbits will encode the binary value of the lowestnumbered filter that matched. In other words, if filterRXF2 and filter RXF4 match, FILHIT will be loaded withthe value for RXF2. This essentially prioritizes theacceptance filters with a lower number filter havinghigher priority. Messages are compared to filters inascending order of filter number.

The mask and filter registers can only be modifiedwhen the PIC18F6585/8585/6680/8680 devices are inConfiguration mode.

FIGURE 23-3: MESSAGE ACCEPTANCE MASK AND FILTER OPERATION

Note: ‘000’ and ‘001’ can only occur if theRXB0DBEN bit is set in the RXB0CONregister, allowing RXB0 messages torollover into RXB1.

Acceptance Filter Register Acceptance Mask Register

RxRqst

Message Assembly Buffer

RXFn0

RXFn1

RXFnn

RXMn0

RXMn1

RXMnn

Identifier

PIC18F6585/8585/6680/8680

23.9 Baud Rate Setting

All nodes on a given CAN bus must have the samenominal bit rate. The CAN protocol uses Non-Return-to-Zero (NRZ) coding which does not encode a clockwithin the data stream. Therefore, the receive clockmust be recovered by the receiving nodes andsynchronized to the transmitter’s clock.

As oscillators and transmission time may vary fromnode to node, the receiver must have some type ofPhase Lock Loop (PLL) synchronized to data transmis-sion edges to synchronize and maintain the receiverclock. Since the data is NRZ coded, it is necessary toinclude bit stuffing to ensure that an edge occurs atleast every six bit times to maintain the Digital PhaseLock Loop (DPLL) synchronization.

The bit timing of the PIC18F6585/8585/6680/8680 isimplemented using a DPLL that is configured to syn-chronize to the incoming data and provides the nominaltiming for the transmitted data. The DPLL breaks eachbit time into multiple segments made up of minimalperiods of time called the Time Quanta (TQ).

Bus timing functions executed within the bit time frame,such as synchronization to the local oscillator, networktransmission delay compensation, and sample pointpositioning, are defined by the programmable bit timinglogic of the DPLL.

All devices on the CAN bus must use the same bit rate.However, all devices are not required to have the samemaster oscillator clock frequency. For the different clockfrequencies of the individual devices, the bit rate has tobe adjusted by appropriately setting the baud rateprescaler and number of time quanta in each segment.

The Nominal Bit Rate is the number of bits transmittedper second, assuming an ideal transmitter with an idealoscillator, in the absence of resynchronization. Thenominal bit rate is defined to be a maximum of 1 Mb/s.

The Nominal Bit Time is defined as:

EQUATION 23-1:

The Nominal Bit Time can be thought of as beingdivided into separate, non-overlapping time segments.These segments (Figure 23-4) include:

• Synchronization Segment (Sync_Seg)• Propagation Time Segment (Prop_Seg)

• Phase Buffer Segment 1 (Phase_Seg1)• Phase Buffer Segment 2 (Phase_Seg2)

The time segments (and thus the Nominal Bit Time) arein turn made up of integer units of time called TimeQuanta or TQ (see Figure 23-4). By definition, the Nom-inal Bit Time is programmable from a minimum of 8 TQ

to a maximum of 25 TQ. Also by definition, the minimumNominal Bit Time is 1 µs, corresponding to a maximum1 Mb/s rate. The actual duration is given by therelationship:

EQUATION 23-2:

The Time Quantum is a fixed unit derived from theoscillator period. It is also defined by the programmablebaud rate prescaler with integer values from 1 to 64 inaddition to a fixed divide-by-two for clock generation.Mathematically, this is:

EQUATION 23-3:

where FOSC is the clock frequency, TOSC is the corre-sponding oscillator period, and BRP is an integer (0through 63) represented by the binary values ofBRGCON1<5:0>.

FIGURE 23-4: BIT TIME PARTITIONING

TBIT = 1/Nominal Bit Rate

Nominal Bit Time = TQ * (Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2)

TQ (µs) = (2 * (BRP+1))/FOSC (MHz)or

TQ (µs) = (2 * (BRP+1)) * TOSC (µs)

Input

Sync Propagation

Segment

Phase

Segment 1

Phase

Segment 2

Sample Point

TQ

Nominal Bit Time

BitTimeIntervals

Signal

Segment

PIC18F6585/8585/6680/8680

23.9.1 TIME QUANTA

As already mentioned, the Time Quanta is a fixed unitderived from the oscillator period and baud rateprescaler. Its relationship to TBIT and the Nominal BitRate is shown in Example 23-6.

EXAMPLE 23-6: CALCULATING TQ, NOMINAL BIT RATE AND NOMINAL BIT TIME

The frequencies of the oscillators in the different nodesmust be coordinated in order to provide a system widespecified nominal bit time. This means that all oscilla-tors must have a TOSC that is an integral divisor of TQ.It should also be noted that although the number of TQ

is programmable from 4 to 25, the usable minimum is8 TQ. A bit time of less than 8 TQ in length is notguaranteed to operate correctly.

23.9.2 SYNCHRONIZATION SEGMENT

This part of the bit time is used to synchronize thevarious CAN nodes on the bus. The edge of the inputsignal is expected to occur during the sync segment.The duration is 1 TQ.

23.9.3 PROPAGATION SEGMENT

This part of the bit time is used to compensate for phys-ical delay times within the network. These delay timesconsist of the signal propagation time on the bus lineand the internal delay time of the nodes. The length ofthe Propagation Segment can be programmed from1 TQ to 8 TQ by setting the PRSEG2:PRSEG0 bits.

23.9.4 PHASE BUFFER SEGMENTS

The phase buffer segments are used to optimallylocate the sampling point of the received bit within thenominal bit time. The sampling point occurs betweenPhase Segment 1 and Phase Segment 2. Thesesegments can be lengthened or shortened by theresynchronization process. The end of Phase Segment1 determines the sampling point within a bit time.Phase Segment 1 is programmable from 1 TQ to 8 TQ

in duration. Phase Segment 2 provides delay beforethe next transmitted data transition and is alsoprogrammable from 1 TQ to 8 TQ in duration. However,due to IPT requirements, the actual minimum length ofPhase Segment 2 is 2 TQ, or it may be defined to beequal to the greater of Phase Segment 1 or theInformation Processing Time (IPT).

23.9.5 SAMPLE POINT

The sample point is the point of time at which the buslevel is read and the value of the received bit is deter-mined. The sampling point occurs at the end of PhaseSegment 1. If the bit timing is slow and contains manyTQ, it is possible to specify multiple sampling of the busline at the sample point. The value of the received bit isdetermined to be the value of the majority decision ofthree values. The three samples are taken at the sam-ple point and twice before, with a time of TQ/2 betweeneach sample.

23.9.6 INFORMATION PROCESSING TIME

The Information Processing Time (IPT) is the timesegment starting at the sample point that is reservedfor calculation of the subsequent bit level. The CANspecification defines this time to be less than or equalto 2 TQ. The PIC18F6585/8585/6680/8680 devicesdefine this time to be 2 TQ. Thus, Phase Segment 2must be at least 2 TQ long.

TQ (µs) = (2 * (BRP+1))/FOSC (MHz)

TBIT (µs) = TQ (µs) * number of TQ per bit interval

Nominal Bit Rate (bits/s) = 1/TBIT

CASE 1:

For FOSC = 16 MHz, BRP<5:0> = 00h and Nominal Bit Time = 8 TQ:

TQ = (2*1)/16 = 0.125 µs (125 ns)

TBIT = 8 * 0.125 = 1 µs (10-6s)

Nominal Bit Rate = 1/10-6 = 106 bits/s (1 Mb/s)

CASE 2:

For FOSC = 20 MHz, BRP<5:0> = 01h and Nominal Bit Time = 8 TQ:

TQ = (2*2)/20 = 0.2 µs (200 ns)

TBIT = 8 * 0.2 = 1.6 µs (1.6 * 10-6s)

Nominal Bit Rate = 1/1.6 * 10-6s = 625,000 bits/s(625 Kb/s)

CASE 3:

For FOSC = 25 MHz, BRP<5:0> = 3Fh and Nominal Bit Time = 25 TQ:

TQ = (2*64)/25 = 5.12 µs

TBIT = 25 * 5.12 = 128 µs (1.28 * 10-4s)

Nominal Bit Rate = 1/1.28 * 10-4 = 7813 bits/s(7.8 Kb/s)

PIC18F6585/8585/6680/8680

23.10 Synchronization

To compensate for phase shifts between the oscillatorfrequencies of each of the nodes on the bus, each CANcontroller must be able to synchronize to the relevantsignal edge of the incoming signal. When an edge inthe transmitted data is detected, the logic will comparethe location of the edge to the expected time(Sync_Seg). The circuit will then adjust the values ofPhase Segment 1 and Phase Segment 2 as necessary.There are two mechanisms used for synchronization.

23.10.1 HARD SYNCHRONIZATION

Hard synchronization is only done when there is arecessive to dominant edge during a bus Idle condition,indicating the start of a message. After hard synchroni-zation, the bit time counters are restarted withSync_Seg. Hard synchronization forces the edgewhich has occurred to lie within the synchronizationsegment of the restarted bit time. Due to the rules ofsynchronization, if a hard synchronization occurs therewill not be a resynchronization within that bit time.

23.10.2 RESYNCHRONIZATION

As a result of resynchronization, Phase Segment 1may be lengthened or Phase Segment 2 may be short-ened. The amount of lengthening or shortening of thephase buffer segments has an upper bound given bythe Synchronization Jump Width (SJW). The value ofthe SJW will be added to Phase Segment 1 (seeFigure 23-5) or subtracted from Phase Segment 2 (seeFigure 23-6). The SJW is programmable between 1 TQ

and 4 TQ.

Clocking information will only be derived from reces-sive to dominant transitions. The property that only afixed maximum number of successive bits have thesame value, ensures resynchronization to the bitstream during a frame.

The phase error of an edge is given by the position ofthe edge relative to Sync_Seg, measured in TQ. Thephase error is defined in magnitude of TQ as follows:

• e = 0 if the edge lies within Sync_Seg.

• e > 0 if the edge lies before the sample point.• e < 0 if the edge lies after the sample point of the

previous bit.

If the magnitude of the phase error is less than, or equalto the programmed value of the synchronization jumpwidth, the effect of a resynchronization is the same asthat of a hard synchronization.

If the magnitude of the phase error is larger than thesynchronization jump width, and if the phase error ispositive, then Phase Segment 1 is lengthened by anamount equal to the synchronization jump width.

If the magnitude of the phase error is larger than theresynchronization jump width, and if the phase error isnegative, then Phase Segment 2 is shortened by anamount equal to the synchronization jump width.

23.10.3 SYNCHRONIZATION RULES

• Only one synchronization within one bit time is allowed.

• An edge will be used for synchronization only if the value detected at the previous sample point (previously read bus value) differs from the bus value immediately after the edge.

• All other recessive to dominant edges fulfilling rules 1 and 2 will be used for resynchronization, with the exception that a node transmitting a dominant bit will not perform a resynchronization as a result of a recessive to dominant edge with a positive phase error.

PIC18F6585/8585/6680/8680

FIGURE 23-5: LENGTHENING A BIT PERIOD (ADDING SJW TO PHASE SEGMENT 1)

FIGURE 23-6: SHORTENING A BIT PERIOD (SUBTRACTING SJW FROM PHASE SEGMENT 2)

Input

SyncProp

Segment

Phase

Segment 1

Phase

Segment 2≤ SJW

Sample PointTQ

Signal

Nominal Bit Length

Actual Bit Length

BitTimeSegments

SyncProp

Segment

Phase

Segment 1

Phase

Segment 2 ≤ SJW

TQ Sample Point

Nominal Bit Length

Actual Bit Length


PIC18F6585/8585/6680/8680

23.11 Programming Time Segments

Some requirements for programming of the timesegments:

• Prop_Seg + Phase_Seg 1 ≥ Phase_Seg 2• Phase_Seg 2 ≥ Sync Jump Width.

For example, assume that a 125 kHz CAN baud rate isdesired, using 20 MHz for FOSC. With a TOSC of 50 ns,a baud rate prescaler value of 04h gives a TQ of 500 ns.To obtain a Nominal Bit Rate of 125 kHz, the NominalBit Time must be 8 µs or 16 TQ.

Using 1 TQ for the Sync_Seg, 2 TQ for the Prop_Segand 7 TQ for Phase Segment 1, would place the samplepoint at 10 TQ after the transition. This leaves 6 TQ forPhase Segment 2.

By the rules above, the Sync Jump Width could be themaximum of 4 TQ. However, normally a large SJW isonly necessary when the clock generation of thedifferent nodes is inaccurate or unstable, such as usingceramic resonators. Typically, an SJW of 1 is enough.

23.12 Oscillator Tolerance

As a rule of thumb, the bit timing requirements allowceramic resonators to be used in applications withtransmission rates of up to 125 Kbit/sec. For the full busspeed range of the CAN protocol, a quartz oscillator isrequired. A maximum node-to-node oscillator variationof 1.7% is allowed.

23.13 Bit Timing Configuration Registers

The Configuration registers (BRGCON1, BRGCON2,BRGCON3) control the bit timing for the CAN businterface. These registers can only be modified whenthe PIC18F6585/8585/6680/8680 devices are inConfiguration mode.

23.13.1 BRGCON1

The BRP bits control the baud rate prescaler. TheSJW<1:0> bits select the synchronization jump width interms of multiples of TQ.

23.13.2 BRGCON2

The PRSEG bits set the length of the propagation seg-ment in terms of TQ. The SEG1PH bits set the length ofPhase Segment 1 in TQ. The SAM bit controls howmany times the RXCAN pin is sampled. Setting this bitto a ‘1’ causes the bus to be sampled three times; twiceat TQ/2 before the sample point and once at the normalsample point (which is at the end of Phase Segment 1).The value of the bus is determined to be the value readduring at least two of the samples. If the SAM bit is setto a ‘0’, then the RXCAN pin is sampled only once atthe sample point. The SEG2PHTS bit controls how thelength of Phase Segment 2 is determined. If this bit isset to a ‘1’, then the length of Phase Segment 2 isdetermined by the SEG2PH bits of BRGCON3. If theSEG2PHTS bit is set to a ‘0’, then the length of PhaseSegment 2 is the greater of Phase Segment 1 and theinformation processing time (which is fixed at 2 TQ forthe PIC18F6585/8585/6680/8680).

23.13.3 BRGCON3

The PHSEG2<2:0> bits set the length (in TQ) of PhaseSegment 2 if the SEG2PHTS bit is set to a ‘1’. If theSEG2PHTS bit is set to a ‘0’, then the PHSEG2<2:0>bits have no effect.

23.14 Error Detection

The CAN protocol provides sophisticated errordetection mechanisms. The following errors can bedetected.

23.14.1 CRC ERROR

With the Cyclic Redundancy Check (CRC), the trans-mitter calculates special check bits for the bitsequence, from the start of a frame until the end of thedata field. This CRC sequence is transmitted in theCRC field. The receiving node also calculates the CRCsequence using the same formula and performs acomparison to the received sequence. If a mismatch isdetected, a CRC error has occurred and an error frameis generated. The message is repeated.

PIC18F6585/8585/6680/8680

23.14.2 ACKNOWLEDGE ERROR

In the Acknowledge field of a message, the transmitterchecks if the Acknowledge slot (which was sent out asa recessive bit) contains a dominant bit. If not, no othernode has received the frame correctly. An Acknowl-edge error has occurred; an error frame is generatedand the message will have to be repeated.

23.14.3 FORM ERROR

If a node detects a dominant bit in one of the foursegments, including end of frame, interframe space,Acknowledge delimiter, or CRC delimiter, then a formerror has occurred and an error frame is generated.The message is repeated.

23.14.4 BIT ERROR

A bit error occurs if a transmitter sends a dominant bitand detects a recessive bit, or if it sends a recessive bitand detects a dominant bit, when monitoring the actualbus level and comparing it to the just transmitted bit. Inthe case where the transmitter sends a recessive bitand a dominant bit is detected during the arbitrationfield and the Acknowledge slot, no bit error isgenerated because normal arbitration is occurring.

23.14.5 STUFF BIT ERROR

lf between the start of frame and the CRC delimiter, sixconsecutive bits with the same polarity are detected,the bit stuffing rule has been violated. A stuff bit erroroccurs and an error frame is generated. The messageis repeated.

23.14.6 ERROR STATES

Detected errors are made public to all other nodes viaerror frames. The transmission of the erroneous mes-sage is aborted and the frame is repeated as soon aspossible. Furthermore, each CAN node is in one of thethree error states “error-active”, “error-passive” or “bus-off” according to the value of the internal error counters.The error-active state is the usual state where the bus

node can transmit messages and activate error frames(made of dominant bits) without any restrictions. In theerror-passive state, messages and passive errorframes (made of recessive bits) may be transmitted.The bus-off state makes it temporarily impossible forthe station to participate in the bus communication.During this state, messages can neither be receivednor transmitted.

23.14.7 ERROR MODES AND ERROR COUNTERS

The PIC18F6585/8585/6680/8680 devices contain twoerror counters: the Receive Error Counter(RXERRCNT), and the Transmit Error Counter(TXERRCNT). The values of both counters can be readby the MCU. These counters are incremented ordecremented in accordance with the CAN busspecification.

The PIC18F6585/8585/6680/8680 devices are error-active if both error counters are below the error-passivelimit of 128. They are error-passive if at least one of theerror counters equals or exceeds 128. They go to bus-off if the transmit error counter equals or exceeds thebus-off limit of 256. The devices remain in this stateuntil the bus-off recovery sequence is received. Thebus-off recovery sequence consists of 128 occurrencesof 11 consecutive recessive bits (see Figure 23-7).Note that the CAN module, after going bus-off, willrecover back to error-active without any intervention bythe MCU if the bus remains Idle for 128 x 11 bit times.If this is not desired, the error Interrupt Service Routineshould address this. The current Error mode of theCAN module can be read by the MCU via theCOMSTAT register.

Additionally, there is an error state warning flag bit,EWARN, which is set if at least one of the errorcounters equals or exceeds the error warning limit of96. EWARN is reset if both error counters are less thanthe error warning limit.


PIC18F6585/8585/6680/8680

FIGURE 23-7: ERROR MODES STATE DIAGRAM

23.15 CAN Interrupts

The module has several sources of interrupts. Each ofthese interrupts can be individually enabled or dis-abled. The PIR3 register contains interrupt flags. ThePIE3 register contains the enables for the 8 main inter-rupts. A special set of read-only bits in the CANSTATregister, the ICODE bits, can be used in combinationwith a jump table for efficient handling of interrupts.

All interrupts have one source with the exception of theerror interrupt and buffer interrupts in Mode 1 and 2. Anyof the error interrupt sources can set the error interruptflag. The source of the error interrupt can be determinedby reading the Communication Status register,COMSTAT. In Mode 1 and 2, there are two interruptenable/disable and flag bits – one for all transmit buffersand the other for all receive buffers.

The interrupts can be broken up into two categories:receive and transmit interrupts.

The receive related interrupts are:

• Receive Interrupts • Wake-up Interrupt

• Receiver Overrun Interrupt• Receiver Warning Interrupt• Receiver Error-Passive Interrupt

The transmit related interrupts are:

• Transmit Interrupts • Transmitter Warning Interrupt

• Transmitter Error-Passive Interrupt • Bus-Off Interrupt

23.15.1 INTERRUPT CODE BITS

To simplify the interrupt handling process in user firm-ware, the ECAN module encodes a special set of bits. InMode 0, these bits are ICODE<2:0> in the CANSTATregister. In Mode 1 and 2, these bits are EICODE<3:0>in the CANSTAT register. Interrupts are internally priori-tized such that the higher priority interrupts are assignedlower values. Once the highest priority interrupt condi-tion has been cleared, the code for the next highestpriority interrupt that is pending (if any) will be reflectedby the ICODE bits. Note that only those interrupt sourcesthat have their associated interrupt enable bit set will bereflected in the ICODE bits.

In Mode 2, when a receive message interrupt occurs,EICODE bits will always consist of ‘10000’. Userfirmware may use FIFO pointer bits to actually accessthe next available buffer.

Bus-Off

Error-Active

Error-Passive

RXERRCNT < 127 orTXERRCNT < 127

RXERRCNT > 127 orTXERRCNT > 127

TXERRCNT > 255

128 occurrences of11 consecutive“recessive” bits

Reset

PIC18F6585/8585/6680/8680

23.15.2 TRANSMIT INTERRUPT

When the transmit interrupt is enabled, an interrupt willbe generated when the associated transmit bufferbecomes empty and is ready to be loaded with a newmessage. In Mode 0, there are separate interruptenable/disable and flag bits for each of the threededicated transmit buffers. The TXBnIF bit will be set toindicate the source of the interrupt. The interrupt iscleared by the MCU resetting the TXBnIF bit to a ‘0’. InMode 1 and 2, all transmit buffers share one interruptenable/disable and flag bits. In Mode 1 and 2, TXBIE inPIE3 and TXBIF in PIR3 indicate when a transmit bufferhas completed transmission of its message. TXBnIF,TXBnIE and TXBnIP in PIR3, PIE3 and IPR3, respec-tively, are not used in Mode 1 and 2. Individual transmitbuffer interrupts can be enabled or disabled by setting orclearing TXBIE and BnIE register bits. When a sharedinterrupt occurs, user firmware must poll the TXREQ bitof all transmit buffers to detect the source of interrupt.

23.15.3 RECEIVE INTERRUPT

When the receive interrupt is enabled, an interrupt willbe generated when a message has been successfullyreceived and loaded into the associated receive buffer.This interrupt is activated immediately after receivingthe End Of Frame (EOF) field.

In Mode 0, the RXBnIF bit is set to indicate the sourceof the interrupt. The interrupt is cleared by the MCUresetting the RXBnIF bit to a ‘0’.

In Mode 1 and 2, all receive buffers share one interrupt.Individual receive buffer interrupts can be controlled bythe RXBnIE and BIEn registers. In Mode 1, when ashared receive interrupt occurs, user firmware mustpoll the RXFUL bit of each receive buffer to detect thesource of interrupt. In Mode 2, a receive interruptindicates that the new message is loaded into FIFO.FIFO can be read by using FIFO pointer bits, FP.

In Mode 2, the FIFOWMIF bit indicates if the FIFO highwatermark is reached. The FIFO high watermark isdefined by the FIFOWM bit in the ECANCON register.

23.15.4 MESSAGE ERROR INTERRUPT

When an error occurs during transmission or receptionof a message, the message error flag, IRXIF, will be setand if the IRXIE bit is set, an interrupt will be generated.This is intended to be used to facilitate baud ratedetermination when used in conjunction with ListenOnly mode.

23.15.5 BUS ACTIVITY WAKE-UP INTERRUPT

When the PIC18F6585/8585/6680/8680 devices are inSleep mode and the bus activity wake-up interrupt isenabled, an interrupt will be generated and the WAKIFbit will be set when activity is detected on the CAN bus.This interrupt causes the PIC18F6585/8585/6680/8680 devices to exit Sleep mode. The interrupt is resetby the MCU, clearing the WAKIF bit.

23.15.6 ERROR INTERRUPT

When the error interrupt is enabled, an interrupt isgenerated if an overflow condition occurs or if the errorstate of the transmitter or receiver has changed. Theerror flags in COMSTAT will indicate one of thefollowing conditions.

23.15.6.1 Receiver Overflow

An overflow condition occurs when the MAB hasassembled a valid received message (the messagemeets the criteria of the acceptance filters) and thereceive buffer associated with the filter is not availablefor loading of a new message. The associatedCOMSTAT.RXnOVFL bit will be set to indicate theoverflow condition. This bit must be cleared by theMCU.

23.15.6.2 Receiver Warning

The receive error counter has reached the MCUwarning limit of 96.

23.15.6.3 Transmitter Warning

The transmit error counter has reached the MCUwarning limit of 96.

23.15.6.4 Receiver Bus Passive

The receive error counter has exceeded the error-passive limit of 127 and the device has gone toerror-passive state.

23.15.6.5 Transmitter Bus Passive

The transmit error counter has exceeded the error-passive limit of 127 and the device has gone toerror-passive state.

23.15.6.6 Bus-Off

The transmit error counter has exceeded 255 and thedevice has gone to bus-off state.

23.15.6.7 Interrupt Acknowledge

Interrupts are directly associated with one or more sta-tus flags in the PIR register. Interrupts are pending aslong as one of the flags is set. Once an interrupt flag isset by the device, the flag can not be reset by themicrocontroller until the interrupt condition is removed.


PIC18F6585/8585/6680/8680

NOTES:


PIC18F6585/8585/6680/8680

24.0 SPECIAL FEATURES OF THE CPU

There are several features intended to maximize sys-tem reliability, minimize cost through elimination ofexternal components, provide power saving operatingmodes and offer code protection. These are:

• OSC Selection

• Reset- Power-on Reset (POR)- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)- Brown-out Reset (BOR)

• Interrupts

• Watchdog Timer (WDT)• Sleep• Code Protection

• ID Locations• In-Circuit Serial Programming

All PIC18F6585/8585/6680/8680 devices have aWatchdog Timer which is permanently enabled via theconfiguration bits or software controlled. It runs off itsown RC oscillator for added reliability. There are twotimers that offer necessary delays on power-up. One isthe Oscillator Start-up Timer (OST), intended to keepthe chip in Reset until the crystal oscillator is stable.The other is the Power-up Timer (PWRT) which pro-vides a fixed delay on power-up only, designed to keepthe part in Reset while the power supply stabilizes. Withthese two timers on-chip, most applications need noexternal Reset circuitry.

Sleep mode is designed to offer a very low currentPower-down mode. The user can wake-up from Sleepthrough external Reset, Watchdog Timer Wake-up, orthrough an interrupt. Several oscillator options are alsomade available to allow the part to fit the application.The RC oscillator option saves system cost, while theLP crystal option saves power. A set of configurationbits is used to select various options.

24.1 Configuration Bits

The configuration bits can be programmed (read as ‘0’)or left unprogrammed (read as ‘1’) to select variousdevice configurations. These bits are mapped, startingat program memory location 300000h.

The user will note that address 300000h is beyond theuser program memory space. In fact, it belongs to theconfiguration memory space (300000h through3FFFFFh) which can only be accessed using tablereads and table writes.

Programming the Configuration registers is done in amanner similar to programming the Flash memory. TheEECON1 register WR bit starts a self-timed write to theConfiguration register. In normal Operation mode, aTBLWT instruction with the TBLPTR pointed to the Con-figuration register sets up the address and the data forthe Configuration register write. Setting the WR bitstarts a long write to the Configuration register. TheConfiguration registers are written a byte at a time. Towrite or erase a configuration cell, a TBLWT instructioncan write a ‘1’ or a ‘0’ into the cell.


PIC18F6585/8585/6680/8680

TABLE 24-1: CONFIGURATION BITS AND DEVICE IDS

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Default/

UnprogrammedValue

300001h CONFIG1H — — OSCSEN — FOSC3 FOSC2 FOSC1 FOSC0 --1- 1111

300002h CONFIG2L — — — — BORV1 BORV0 BODEN PWRTEN ---- 1111

300003h CONFIG2H — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111

300004h(1) CONFIG3L WAIT — — — — — PM1 PM0 1--- --11

300005h CONFIG3H MCLRE — — — — — ECCPMX(4) CCP2MX 1--- --11

300006h CONFIG4L DEBUG — — — — LVP — STVREN 1--- -1-1

300008h CONFIG5L — — — — CP3(2) CP2 CP1 CP0 ---- 1111

300009h CONFIG5H CPD CPB — — — — — — 11-- ----

30000Ah CONFIG6L — — — — WRT3(2) WRT2 WRT1 WRT0 ---- 1111

30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ----

30000Ch CONFIG7L — — — — EBTR3(2) EBTR2 EBTR1 EBTR0 ---- 1111

30000Dh CONFIG7H — EBTRB — — — — — — -1-- ----

3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 (Note 3)

3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 1010

Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.

Note 1: Unimplemented in PIC18F6X8X devices; maintain this bit set.2: Unimplemented in PIC18FX585 devices; maintain this bit set.3: See Register 24-13 for DEVID1 values.4: Reserved in PIC18F6X8X devices; maintain this bit set.


PIC18F6585/8585/6680/8680

REGISTER 24-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) U-0 U-0 R/P-1 U-0 R/P-1 R/P-1 R/P-1 R/P-1

— — OSCSEN — FOSC3 FOSC2 FOSC1 FOSC0

bit 7 bit 0


bit 5 OSCSEN: Oscillator System Clock Switch Enable bit1 = Oscillator system clock switch option is disabled (main oscillator is source)0 = Timer1 oscillator system clock switch option is enabled (oscillator switching is enabled)


bit 3-0 FOSC3:FOSC0: Oscillator Selection bits1111 = RC oscillator with OSC2 configured as RA6 1110 = HS oscillator with SW enabled 4x PLL1101 = EC oscillator with OSC2 configured as RA6 and SW enabled 4x PLL1100 = EC oscillator with OSC2 configured as RA6 and HW enabled 4x PLL1011 = Reserved; do not use1010 = Reserved; do not use1001 = Reserved; do not use1000 = Reserved; do not use0111 = RC oscillator with OSC2 configured as RA60110 = HS oscillator with HW enabled 4x PLL0101 = EC oscillator with OSC2 configured as RA60100 = EC oscillator with OSC2 configured as divide by 4 clock output0011 = RC oscillator with OSC2 configured as divide by 4 clock output0010 = HS oscillator0001 = XT oscillator0000 = LP oscillator

Legend:


- n = Value when device is unprogrammed u = Unchanged from programmed state


PIC18F6585/8585/6680/8680

REGISTER 24-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1

— — — — BORV1 BORV0 BOREN PWRTEN

bit 7 bit 0


bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits11 = VBOR set to 2.0V 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.5V

bit 1 BOREN: Brown-out Reset Enable bit1 = Brown-out Reset enabled 0 = Brown-out Reset disabled

bit 0 PWRTEN: Power-up Timer Enable bit

1 = PWRT disabled 0 = PWRT enabled

Legend:




PIC18F6585/8585/6680/8680

REGISTER 24-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)

REGISTER 24-4: CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h)(1)

U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN

bit 7 bit 0


bit 4-1 WDTPS3:WDTPS0: Watchdog Timer Postscaler Select bits

1111 = 1:32768 1110 = 1:16384 1101 = 1:8192 1100 = 1:4096 1011 = 1:2048 1010 = 1:1024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:640101 = 1:32 0100 = 1:160011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1

bit 0 WDTEN: Watchdog Timer Enable bit

1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit)

Legend:



R/P-1 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1

WAIT — — — — — PM1 PM0

bit 7 bit 0

bit 7 WAIT: External Bus Data Wait Enable bit1 = Wait selections unavailable for table reads and table writes 0 = Wait selections for table reads and table writes are determined by WAIT1:WAIT0 bits

(MEMCOM<5:4>)


bit 1-0 PM1:PM0: Processor Mode Select bits11 = Microcontroller mode 10 = Microprocessor mode 01 = Microprocessor with Boot Block mode 00 = Extended Microcontroller mode

Note 1: This register is unimplemented for PIC18F6X8X devices; maintain these bits set.

Legend:

PIC18F6585/8585/6680/8680


REGISTER 24-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)

R/P-1 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1

MCLRE — — — — — ECCPMX CCP2MX

bit 7 bit 0

bit 7 MCLRE: MCLR Enable bit(1)

1 = MCLR pin enabled, RG5 input pin disabled0 = RG5 input enabled, MCLR disabled


bit 1 ECCPMX: CCP1 PWM outputs P1B, P1C mux bit (PIC18F8X8X devices only)(2)

1 = P1B, P1C are multiplexed with RE6, RE50 = P1B, P1C are multiplexed with RH7, RH6

bit 0 CCP2MX: CCP2 Mux bitIn Microcontroller mode:1 = CCP2 input/output is multiplexed with RC1 0 = CCP2 input/output is multiplexed with RE7

In Microprocessor, Microprocessor with Boot Block and Extended Microcontroller modes(PIC18F8X8X devices only):1 = CCP2 input/output is multiplexed with RC1 0 = CCP2 input/output is multiplexed with RB3

Note 1: If MCLR is disabled, either disable low-voltage ICSP or hold RB5/PGM low toensure proper entry into ICSP mode.

2: Reserved for PIC18F6X8X devices; maintain this bit set.

Legend:



R/P-1 U-0 U-0 U-0 U-0 R/P-1 U-0 R/P-1

DEBUG — — — — LVP — STVREN

bit 7 bit 0

bit 7 DEBUG: Background Debugger Enable bit1 = Background debugger disabled. RB6 and RB7 configured as general purpose I/O pins. 0 = Background debugger enabled. RB6 and RB7 are dedicated to in-circuit debug.


bit 2 LVP: Low-Voltage ICSP Enable bit1 = Low-voltage ICSP enabled 0 = Low-voltage ICSP disabled


bit 0 STVREN: Stack Full/Underflow Reset Enable bit

1 = Stack full/underflow will cause Reset 0 = Stack full/underflow will not cause Reset

Legend:




PIC18F6585/8585/6680/8680

REGISTER 24-7: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h)


U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1

— — — — CP3(1) CP2 CP1 CP0

bit 7 bit 0

bit 7-4 Unimplemented: Read as ‘0’ bit 3 CP3: Code Protection bit(1)

1 = Block 3 (00C000-00FFFFh) not code-protected 0 = Block 3 (00C000-00FFFFh) code-protected

Note 1: Unimplemented in PIC18FX585 devices; maintain this bit set.

bit 2 CP2: Code Protection bit1 = Block 2 (008000-00BFFFh) not code-protected 0 = Block 2 (008000-00BFFFh) code-protected

bit 1 CP1: Code Protection bit1 = Block 1 (004000-007FFFh) not code-protected 0 = Block 1 (004000-007FFFh) code-protected

bit 0 CP0: Code Protection bit

1 = Block 0 (000800-003FFFh) not code-protected 0 = Block 0 (000800-003FFFh) code-protected

Legend:R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’


R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0

CPD CPB — — — — — —bit 7 bit 0

bit 7 CPD: Data EEPROM Code Protection bit1 = Data EEPROM not code-protected0 = Data EEPROM code-protected

bit 6 CPB: Boot Block Code Protection bit1 = Boot block (000000-0007FFh) not code-protected0 = Boot block (000000-0007FFh) code-protected


Legend:R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’



PIC18F6585/8585/6680/8680

REGISTER 24-9: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah)

REGISTER 24-10: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh)

U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1

— — — — WRT3(1) WRT2 WRT1 WRT0

bit 7 bit 0


bit 3 WRT3: Write Protection bit(1)

1 = Block 3 (00C000-00FFFFh) not write-protected 0 = Block 3 (00C000-00FFFFh) write-protected


bit 2 WRT2: Write Protection bit1 = Block 2 (008000-00BFFFh) not write-protected 0 = Block 2 (008000-00BFFFh) write-protected

bit 1 WRT1: Write Protection bit1 = Block 1 (004000-007FFFh) not write-protected 0 = Block 1 (004000-007FFFh) write-protected

bit 0 WR0: Write Protection bit

1 = Block 0 (000800-003FFFh) not write-protected 0 = Block 0 (000800-003FFFh) write-protected

Legend:



R/C-1 R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0

WRTD WRTB WRTC — — — — —

bit 7 bit 0

bit 7 WRTD: Data EEPROM Write Protection bit1 = Data EEPROM not write-protected0 = Data EEPROM write-protected

bit 6 WRTB: Boot Block Write Protection bit

1 = Boot block (000000-0007FFh) not write-protected0 = Boot block (000000-0007FFh) write-protected

bit 5 WRTC: Configuration Register Write Protection bit1 = Configuration registers (300000-3000FFh) not write-protected0 = Configuration registers (300000-3000FFh) write-protected


Legend:




PIC18F6585/8585/6680/8680

REGISTER 24-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)

REGISTER 24-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh)

U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1

— — — — EBTR3(1) EBTR2 EBTR1 EBTR0

bit 7 bit 0


bit 3 EBTR3: Table Read Protection bit(1)

1 = Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks0 = Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks


bit 2 EBTR2: Table Read Protection bit1 = Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks 0 = Block 2 (008000-00BFFFh) protected from table reads executed in other blocks

bit 1 EBTR1: Table Read Protection bit1 = Block 1 (004000-007FFFh) not protected from table reads executed in other blocks 0 = Block 1 (004000-007FFFh) protected from table reads executed in other blocks

bit 0 EBTR0: Table Read Protection bit

1 = Block 0 (000800-003FFFh) not protected from table reads executed in other blocks 0 = Block 0 (000800-003FFFh) protected from table reads executed in other blocks

Legend:



U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0

— EBTRB — — — — — —

bit 7 bit 0


bit 6 EBTRB: Boot Block Table Read Protection bit

1 = Boot block (000000-0007FFh) not protected from table reads executed in other blocks0 = Boot block (000000-0007FFh) protected from table reads executed in other blocks


Legend:




PIC18F6585/8585/6680/8680

REGISTER 24-13: DEVICE ID REGISTER 1 FOR PIC18FXX8X DEVICES (ADDRESS 3FFFFEh)

REGISTER 24-14: DEVICE ID REGISTER 2 FOR PIC18FXX8X DEVICES (ADDRESS 3FFFFFh)

R R R R R R R R

DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0

bit 7 bit 0

bit 7-5 DEV2:DEV0: Device ID bits000 = PIC18F8680001 = PIC18F6680010 = PIC18F8585011 = PIC18F6585

bit 4-0 REV4:REV0: Revision ID bitsThese bits are used to indicate the device revision.

Legend:



R-0 R-0 R-0 R-0 R-1 R-0 R-1 R-0

DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3

bit 7 bit 0

bit 7-0 DEV10:DEV3: Device ID bits

These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the part number.

0000 1010 = PIC18F6585/8585/6680/8680

Legend:




PIC18F6585/8585/6680/8680

24.2 Watchdog Timer (WDT)

The Watchdog Timer is a free-running, on-chip RCoscillator which does not require any external compo-nents. This RC oscillator is separate from the RCoscillator of the OSC1/CLKI pin. That means that theWDT will run even if the clock on the OSC1/CLKI andOSC2/CLKO/RA6 pins of the device has been stopped,for example, by execution of a SLEEP instruction.

During normal operation, a WDT time-out generates adevice Reset (Watchdog Timer Reset). If the device isin Sleep mode, a WDT time-out causes the device towake-up and continue with normal operation (Watch-dog Timer wake-up). The TO bit in the RCON registerwill be cleared upon a WDT time-out.

The Watchdog Timer is enabled/disabled by a deviceconfiguration bit. If the WDT is enabled, softwareexecution may not disable this function. When theWDTEN configuration bit is cleared, the SWDTEN bitenables/disables the operation of the WDT.

The WDT time-out period values may be found inSection 27.0 “Electrical Characteristics” underparameter #31. Values for the WDT postscaler may beassigned using the configuration bits.

24.2.1 CONTROL REGISTER

Register 24-15 shows the WDTCON register. This is areadable and writable register which contains a controlbit that allows software to override the WDT enableconfiguration bit, only when the configuration bit hasdisabled the WDT.

REGISTER 24-15: WDTCON REGISTER

Note 1: The CLRWDT and SLEEP instructionsclear the WDT and the postscaler ifassigned to the WDT and prevent it fromtiming out and generating a device Resetcondition.

2: When a CLRWDT instruction is executedand the postscaler is assigned to theWDT, the postscaler count will be clearedbut the postscaler assignment is notchanged.

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — — SWDTEN

bit 7 bit 0


bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit

1 = Watchdog Timer is on0 = Watchdog Timer is turned off if the WDTEN configuration bit in the Configuration register = 0

Legend:




PIC18F6585/8585/6680/8680

24.2.2 WDT POSTSCALER

The WDT has a postscaler that can extend the WDTReset period. The postscaler is selected at the time ofthe device programming by the value written to theCONFIG2H Configuration register.

FIGURE 24-1: WATCHDOG TIMER BLOCK DIAGRAM

TABLE 24-2: SUMMARY OF WATCHDOG TIMER REGISTERS

PostscalerWDT Timer

WDTEN

16-to-1 MUX WDTPS3:WDTPS0

WDTTime-out

16

SWDTEN bit Configuration bit

Note: WDPS3:WDPS0 are bits in register CONFIG2H.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CONFIG2H — — — WDTPS3 WDTPS2 WDTPS2 WDTPS0 WDTEN

RCON IPEN — — RI TO PD POR BOR

WDTCON — — — — — — — SWDTEN

Legend: Shaded cells are not used by the Watchdog Timer.


PIC18F6585/8585/6680/8680

24.3 Power-down Mode (Sleep)

Power-down mode is entered by executing a SLEEPinstruction.

If enabled, the Watchdog Timer will be cleared butkeeps running, the PD bit (RCON<3>) is cleared, theTO (RCON<4>) bit is set and the oscillator driver isturned off. The I/O ports maintain the status they hadbefore the SLEEP instruction was executed (drivinghigh, low, or high-impedance).

For lowest current consumption in this mode, place allI/O pins at either VDD or VSS, ensure no external cir-cuitry is drawing current from the I/O pin, power-downthe A/D and disable external clocks. Pull all I/O pinsthat are high-impedance inputs, high or low externallyto avoid switching currents caused by floating inputs.The T0CKI input should also be at VDD or VSS for low-est current consumption. The contribution from on-chippull-ups on PORTB should be considered.

The MCLR pin must be at a logic high level (VIHMC).

24.3.1 WAKE-UP FROM SLEEP

The device can wake-up from Sleep through one of thefollowing events:

1. External Reset input on MCLR pin.

2. Watchdog Timer Wake-up (if WDT wasenabled).

3. Interrupt from INT pin, RB port change or aperipheral interrupt.

The following peripheral interrupts can wake the devicefrom Sleep:

1. PSP read or write.2. TMR1 interrupt. Timer1 must be operating as an

asynchronous counter.3. TMR3 interrupt. Timer3 must be operating as an

asynchronous counter.4. CCP Capture mode interrupt.

5. Special event trigger (Timer1 in Asynchronousmode using an external clock).

6. MSSP (Start/Stop) bit detect interrupt.7. MSSP transmit or receive in Slave mode

(SPI/I2C).8. USART RX or TX (Synchronous Slave mode).9. A/D conversion (when A/D clock source is RC).

10. EEPROM write operation complete.11. LVD interrupt.12. CAN wake-up interrupt.

Other peripherals cannot generate interrupts sinceduring Sleep, no on-chip clocks are present.

External MCLR Reset will cause a device Reset. Allother events are considered a continuation of programexecution and will cause a “wake-up”. The TO and PDbits in the RCON register can be used to determine thecause of the device Reset. The PD bit which is set onpower-up is cleared when Sleep is invoked. The TO bitis cleared if a WDT time-out occurred (and causedwake-up).

When the SLEEP instruction is being executed, the nextinstruction (PC + 2) is pre-fetched. For the device towake-up through an interrupt event, the correspondinginterrupt enable bit must be set (enabled). Wake-up isregardless of the state of the GIE bit. If the GIE bit isclear (disabled), the device continues execution at theinstruction after the SLEEP instruction. If the GIE bit isset (enabled), the device executes the instruction afterthe SLEEP instruction and then branches to the inter-rupt address. In cases where the execution of theinstruction following SLEEP is not desirable, the usershould have a NOP after the SLEEP instruction.

24.3.2 WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) andany interrupt source has both its interrupt enable bitand interrupt flag bit set, one of the following will occur:

• If an interrupt condition (interrupt flag bit and interrupt enable bits are set) occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared.

• If the interrupt condition occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from Sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared.

Even if the flag bits were checked before executing aSLEEP instruction, it may be possible for flag bits tobecome set before the SLEEP instruction completes. Todetermine whether a SLEEP instruction executed, testthe PD bit. If the PD bit is set, the SLEEP instructionwas executed as a NOP.

To ensure that the WDT is cleared, a CLRWDTinstruction should be executed before a SLEEPinstruction.

PIC18F6585/8585/6680/8680

FIGURE 24-2: WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKO(4)

INT pin

INTF Flag(INTCON<1>)

GIEH bit(INTCON<7>)

INSTRUCTION FLOW

PC

InstructionFetchedInstructionExecuted

PC PC+2 PC+4

Inst(PC) = Sleep

Inst(PC - 1)

Inst(PC + 2)

Sleep

Processor inSleep

Interrupt Latency(3)

Inst(PC + 4)

Inst(PC + 2)

Inst(0008h) Inst(000Ah)

Inst(0008h)Dummy Cycle

PC + 4 0008h 000Ah

Dummy Cycle

TOST(2)

PC+4

Note 1: XT, HS or LP Oscillator mode assumed.2: GIE = 1 assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.3: TOST = 1024 TOSC (drawing not to scale). This delay will not occur for RC and EC Oscillator modes.4: CLKO is not available in these oscillator modes but shown here for timing reference.

PIC18F6585/8585/6680/8680

24.4 Program Verification and Code Protection

The overall structure of the code protection on thePIC18 Flash devices differs significantly from otherPICmicro® devices.

The user program memory is divided on binary bound-aries into four blocks of 16 Kbytes each. The first blockis further divided into a boot block of 2048 bytes and asecond block (Block 0) of 14 Kbytes.

Each of the blocks has three code protection bitsassociated with them. They are:

• Code-Protect bit (CPn)• Write-Protect bit (WRTn)• External Block Table Read bit (EBTRn)

Figure 24-3 shows the program memory organizationfor 48 and 64-Kbyte devices and the specific codeprotection bit associated with each block. The actuallocations of the bits are summarized in Table 24-3.

FIGURE 24-3: CODE-PROTECTED PROGRAM MEMORY FOR PIC18FXX8X DEVICES

TABLE 24-3: SUMMARY OF CODE PROTECTION REGISTERS

MEMORY SIZE/DEVICE Block Code Protection

Controlled By:48 Kbytes(PIC18FX585

64 Kbytes(PIC18FX680)

Address Range

Boot Block Boot Block000000h0007FFh

CPB, WRTB, EBTRB

Block 0 Block 0000800h003FFFh

CP0, WRT0, EBTR0

Block 1 Block 1004000h

007FFFhCP1, WRT1, EBTR1

Block 2 Block 2008000h

00BFFFhCP2, WRT2, EBTR2

Unimplemented Read ‘0’ Block 300C000h

00FFFFhCP3, WRT3, EBTR3

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

300008h CONFIG5L — — — — CP3(1) CP2 CP1 CP0

300009h CONFIG5H CPD CPB — — — — — —

30000Ah CONFIG6L — — — — WRT3(1) WRT2 WRT1 WRT0

30000Bh CONFIG6H WRTD WRTB WRTC — — — — —

30000Ch CONFIG7L — — — — EBTR3(1) EBTR2 EBTR1 EBTR0

30000Dh CONFIG7H — EBTRB — — — — — —

Legend: Shaded cells are unimplemented.

Note 1: Unimplemented in PIC18FX585 devices.


PIC18F6585/8585/6680/8680

24.4.1 PROGRAM MEMORYCODE PROTECTION

The user memory may be read to or written from anylocation using the table read and table write instruc-tions. The device ID may be read with table reads. TheConfiguration registers may be read and written withthe table read and table write instructions.

In User mode, the CPn bits have no direct effect. CPnbits inhibit external reads and writes. A block of usermemory may be protected from table writes if theWRTn configuration bit is ‘0’. The EBTRn bits controltable reads. For a block of user memory with theEBTRn bit set to ‘0’, a table read instruction that exe-cutes from within that block is allowed to read. A tableread instruction that executes from a location outside of

that block is not allowed to read and will result in read-ing ‘0’s. Figures 24-4 through 24-6 illustrate table writeand table read protection.

FIGURE 24-4: TABLE WRITE (WRTn) DISALLOWED

Note: Code protection bits may only be written toa ‘0’ from a ‘1’ state. It is not possible towrite a ‘1’ to a bit in the ‘0’ state. Codeprotection bits are only set to ‘1’ by a fullchip erase or block erase function. The fullchip erase and block erase functions canonly be initiated via ICSP or an externalprogrammer.

000000h0007FFh000800h

003FFFh004000h

007FFFh008000h

00BFFFh00C000h

00FFFFh

WRTB, EBTRB = 11

WRT0, EBTR0 = 01

WRT1, EBTR1 = 11

WRT2, EBTR2 = 11

WRT3, EBTR3 = 11

TBLWT *

TBLPTR = 000FFFh

PC = 003FFEh

TBLWT *PC = 008FFEh

Register Values Program Memory Configuration Bit Settings

Results: All table writes disabled to Block n whenever WRTn = 0.


PIC18F6585/8585/6680/8680

FIGURE 24-5: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED

FIGURE 24-6: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED

WRTB, EBTRB = 11

WRT0, EBTR0 = 10

WRT1, EBTR1 = 11

WRT2, EBTR2 = 11

WRT3, EBTR3 = 11

TBLRD *

TBLPTR = 000FFFh

PC = 004FFEh

Results: All table reads from external blocks to Block n are disabled whenever EBTRn = 0.TABLAT register returns a value of ‘0’.


0007FFh000800h

003FFFh004000h

007FFFh008000h

00BFFFh00C000h

00FFFFh

000000h

WRTB, EBTRB = 11

WRT0, EBTR0 = 10

WRT1, EBTR1 = 11

WRT2, EBTR2 = 11

WRT3, EBTR3 = 11

TBLRD *

TBLPTR = 000FFFh

PC = 003FFEh


Results: Table reads permitted within Block n even when EBTRBn = 0.TABLAT register returns the value of the data at the location TBLPTR.

0007FFh000800h

003FFFh004000h

007FFFh008000h

00BFFFh00C000h

00FFFFh

000000h


PIC18F6585/8585/6680/8680

24.4.2 DATA EEPROM CODE PROTECTION

The entire data EEPROM is protected from externalreads and writes by two bits: CPD and WRTD. CPDinhibits external reads and writes of data EEPROM.WRTD inhibits external writes to data EEPROM. TheCPU can continue to read and write data EEPROMregardless of the protection bit settings.

24.4.3 CONFIGURATION REGISTER PROTECTION

The Configuration registers can be write-protected. TheWRTC bit controls protection of the Configuration regis-ters. In User mode, the WRTC bit is readable only. WRTCcan only be written via ICSP or an external programmer.

24.5 ID Locations

Eight memory locations (200000h-200007h) aredesignated as ID locations where the user can storechecksum or other code identification numbers. Theselocations are accessible during normal executionthrough the TBLRD and TBLWT instructions or duringprogram/verify. The ID locations can be read when thedevice is code-protected.

24.6 In-Circuit Serial Programming

PIC18FXX80/XX85 microcontrollers can be seriallyprogrammed while in the end application circuit. This issimply done with two lines for clock and data, and threeother lines for power, ground and the programmingvoltage. This allows customers to manufacture boardswith unprogrammed devices and then program themicrocontroller just before shipping the product. Thisalso allows the most recent firmware or a customfirmware to be programmed.

24.7 In-Circuit Debugger

When the DEBUG bit in Configuration register,CONFIG4L, is programmed to a ‘0’, the in-circuitdebugger functionality is enabled. This function allowssimple debugging functions when used with MPLAB®

IDE. When the microcontroller has this featureenabled, some of the resources are not available forgeneral use. Table 24-4 shows which features areconsumed by the background debugger.

TABLE 24-4: DEBUGGER RESOURCES

To use the in-circuit debugger function of the micro-controller, the design must implement In-Circuit SerialProgramming connections to MCLR/VPP, VDD, GND,RB7 and RB6. This will interface to the in-circuitdebugger module available from Microchip or one ofthe third party development tool companies.

I/O pins RB6, RB7

Stack 2 levels

Program Memory 512 bytes

Data Memory 10 bytes


PIC18F6585/8585/6680/8680

24.8 Low-Voltage ICSP Programming

The LVP bit in Configuration register, CONFIG4L,enables Low-Voltage ICSP Programming. This modeallows the microcontroller to be programmed via ICSPusing a VDD source in the operating voltage range. Thisonly means that VPP does not have to be brought to VIHH

but can instead be left at the normal operating voltage.In this mode, the RB5/KBI1/PGM pin is dedicated to theprogramming function and ceases to be a general pur-pose I/O pin. During programming, VDD is applied to theRG5/MCLR/VPP pin. To enter Programming mode, VDD

must be applied to the RB5/KBI1/PGM pin, provided theLVP bit is set. The LVP bit defaults to a ‘1’ from thefactory.

If Low-Voltage Programming mode is not used, the LVPbit can be programmed to a ‘0’ and RB5/KBI1/PGMbecomes a digital I/O pin. However, the LVP bit mayonly be programmed when programming is enteredwith VIHH on RG5/MCLR/VPP.

It should be noted that once the LVP bit is programmedto ‘0’, only the High-Voltage Programming mode isavailable and only High-Voltage Programming modecan be used to program the device.

When using low-voltage ICSP, the part must be sup-plied 4.5V to 5.5V if a bulk erase will be executed. Thisincludes reprogramming of the code-protect bits froman on-state to an off-state. For all other cases of low-voltage ICSP, the part may be programmed at thenormal operating voltage. This means unique user IDsor user code can be reprogrammed or added.Note 1: The High-Voltage Programming mode is

always available regardless of the state ofthe LVP bit, by applying VIHH to the MCLRpin.

2: While in Low-Voltage ICSP mode, theRB5 pin can no longer be used as ageneral purpose I/O pin and should beheld low during normal operation.

3: When using Low-Voltage ICSP Program-ming (LVP) and the pull-ups on PORTBare enabled, bit 5 in the TRISB registermust be cleared to disable the pull-up onRB5 and ensure the proper operation ofthe device.

4: If the device Master Clear is disabled,verify that either of the following is done toensure proper entry into ICSP mode:

a) disable Low-Voltage Programming(CONFIG4L<2> = 0); or

b) make certain that RB5/KBI1/PGM isheld low during entry into ICSP.

PIC18F6585/8585/6680/8680

NOTES:


PIC18F6585/8585/6680/8680

25.0 INSTRUCTION SET SUMMARY

The PIC18 instruction set adds many enhancements tothe previous PICmicro instruction sets, while maintain-ing an easy migration from these PICmicro instructionsets.

Most instructions are a single program memory word(16 bits) but there are three instructions that require twoprogram memory locations.

Each single-word instruction is a 16-bit word dividedinto an opcode, which specifies the instruction type andone or more operands, which further specify theoperation of the instruction.

The instruction set is highly orthogonal and is groupedinto four basic categories:

• Byte-oriented operations• Bit-oriented operations• Literal operations

• Control operations

The PIC18 instruction set summary in Table 25-2 listsbyte-oriented, bit-oriented, literal and controloperations. Table 25-1 shows the opcode fielddescriptions.

Most byte-oriented instructions have three operands:

1. The file register (specified by ‘f’) 2. The destination of the result (specified by ‘d’) 3. The accessed memory (specified by ‘a’)

The file register designator ‘f’ specifies which fileregister is to be used by the instruction.

The destination designator ‘d’ specifies where theresult of the operation is to be placed. If ‘d’ is zero, theresult is placed in the WREG register. If ‘d’ is one, theresult is placed in the file register specified in theinstruction.

All bit-oriented instructions have three operands:

1. The file register (specified by ‘f’) 2. The bit in the file register (specified by ‘b’) 3. The accessed memory (specified by ‘a’)

The bit field designator ‘b’ selects the number of the bitaffected by the operation, while the file register desig-nator ‘f’ represents the number of the file in which thebit is located.

The literal instructions may use some of the followingoperands:

• A literal value to be loaded into a file register (specified by ‘k’)

• The desired FSR register to load the literal value into (specified by ‘f’)

• No operand required (specified by ‘—’)

The control instructions may use some of the followingoperands:

• A program memory address (specified by ‘n’)

• The mode of the call or return instructions (specified by ‘s’)

• The mode of the table read and table write instructions (specified by ‘m’)

• No operand required (specified by ‘—’)

All instructions are a single word except for threedouble-word instructions. These three instructionswere made double-word instructions so that all therequired information is available in these 32 bits. In thesecond word, the 4 MSbs are ‘1’s. If this second wordis executed as an instruction (by itself), it will executeas a NOP.

All single-word instructions are executed in a singleinstruction cycle unless a conditional test is true or theprogram counter is changed as a result of the instruc-tion. In these cases, the execution takes two instructioncycles with the additional instruction cycle(s) executedas a NOP.

The double-word instructions execute in two instructioncycles.

One instruction cycle consists of four oscillator periods.Thus, for an oscillator frequency of 4 MHz, the normalinstruction execution time is 1 µs. If a conditional test istrue or the program counter is changed as a result of aninstruction, the instruction execution time is 2 µs.Two-word branch instructions (if true) would take 3 µs.

Figure 25-1 shows the general formats that theinstructions can have.

All examples use the format ‘nnh’ to represent a hexa-decimal number, where ‘h’ signifies a hexadecimaldigit.

The Instruction Set Summary, shown in Table 25-2,lists the instructions recognized by the MicrochipAssembler (MPASMTM).

Section 25.1 “Instruction Set” provides a descriptionof each instruction.


PIC18F6585/8585/6680/8680

TABLE 25-1: OPCODE FIELD DESCRIPTIONS

Field Description

a RAM access bita = 0: RAM location in Access RAM (BSR register is ignored)a = 1: RAM bank is specified by BSR register

bbb Bit address within an 8-bit file register (0 to 7).

BSR Bank Select Register. Used to select the current RAM bank.

d Destination select bitd = 0: store result in WREGd = 1: store result in file register f

dest Destination either the WREG register or the specified register file location.

f 8-bit register file address (0x00 to 0xFF).

fs 12-bit register file address (0x000 to 0xFFF). This is the source address.

fd 12-bit register file address (0x000 to 0xFFF). This is the destination address.

k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).

label Label name.

mm The mode of the TBLPTR register for the table read and table write instructions.Only used with table read and table write instructions:

* No change to register (such as TBLPTR with table reads and writes).

*+ Post-Increment register (such as TBLPTR with table reads and writes).

*- Post-Decrement register (such as TBLPTR with table reads and writes).

+* Pre-Increment register (such as TBLPTR with table reads and writes).

n The relative address (2’s complement number) for relative branch instructions, or the direct address for call/branch and return instructions.

PRODH Product of Multiply High Byte.

PRODL Product of Multiply Low Byte.

s Fast Call/Return mode select bits = 0: do not update into/from shadow registerss = 1: certain registers loaded into/from shadow registers (Fast mode)

u Unused or unchanged.

WREG Working register (accumulator).

x Don’t care (0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools.

TBLPTR 21-bit Table Pointer (points to a program memory location).

TABLAT 8-bit Table Latch.

TOS Top-of-Stack.

PC Program Counter.

PCL Program Counter Low Byte.

PCH Program Counter High Byte.

PCLATH Program Counter High Byte Latch.

PCLATU Program Counter Upper Byte Latch.

GIE Global Interrupt Enable bit.

WDT Watchdog Timer.

TO Time-out bit.

PD Power-down bit.

C, DC, Z, OV, N ALU status bits: Carry, Digit Carry, Zero, Overflow, Negative.

[ ] Optional.

( ) Contents.

→ Assigned to.

< > Register bit field.

∈ In the set of.

italics User defined term (font is courier).

PIC18F6585/8585/6680/8680

FIGURE 25-1: GENERAL FORMAT FOR INSTRUCTIONS

Byte-oriented file register operations

15 10 9 8 7 0

d = 0 for result destination to be WREG register

OPCODE d a f (FILE #)

d = 1 for result destination to be file register (f)a = 0 to force Access Bank

Bit-oriented file register operations

15 12 11 9 8 7 0

OPCODE b (BIT #) a f (FILE #)

b = 3-bit position of bit in file register (f)

Literal operations

15 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

Byte to Byte move operations (2-word)

15 12 11 0

OPCODE f (Source FILE #)

CALL, GOTO and Branch operations

15 8 7 0

OPCODE n<7:0> (literal)

n = 20-bit immediate value

a = 1 for BSR to select bankf = 8-bit file register address

a = 0 to force Access Banka = 1 for BSR to select bankf = 8-bit file register address

15 12 11 0

1111 n<19:8> (literal)

15 12 11 0

1111 f (Destination FILE #)

f = 12-bit file register address

Control operations

Example Instruction

ADDWF MYREG, W, B

MOVFF MYREG1, MYREG2

BSF MYREG, bit, B

MOVLW 0x7F

GOTO Label

15 8 7 0


15 12 11 0

n<19:8> (literal)

CALL MYFUNC

15 11 10 0


S = Fast bit

BRA MYFUNC

15 8 7 0

OPCODE n<7:0> (literal) BC MYFUNC

S

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TABLE 25-2: PIC18FXXX INSTRUCTION SET

Mnemonic,Operands

Description Cycles16-Bit Instruction Word Status

AffectedNotes

MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONSADDWFADDWFCANDWFCLRFCOMFCPFSEQCPFSGTCPFSLTDECFDECFSZDCFSNZINCFINCFSZINFSNZIORWFMOVFMOVFF

MOVWFMULWFNEGFRLCFRLNCFRRCFRRNCFSETFSUBFWB

SUBWFSUBWFB

SWAPFTSTFSZXORWF

f, d, af, d, af, d, af, af, d, af, af, af, af, d, af, d, af, d, af, d, af, d, af, d, af, d, af, d, afs, fd

f, af, af, af, d, af, d, af, d, af, d, af, af, d, a

f, d, af, d, a

f, d, af, af, d, a

Add WREG and fAdd WREG and Carry bit to fAND WREG with fClear fComplement fCompare f with WREG, Skip =Compare f with WREG, Skip >Compare f with WREG, Skip <Decrement fDecrement f, Skip if 0Decrement f, Skip if Not 0Increment fIncrement f, Skip if 0Increment f, Skip if Not 0Inclusive OR WREG with fMove fMove fs (source) to 1st word

fd (destination) 2nd wordMove WREG to fMultiply WREG with fNegate fRotate Left f through CarryRotate Left f (No Carry)Rotate Right f through CarryRotate Right f (No Carry)Set fSubtract f from WREG with borrow Subtract WREG from fSubtract WREG from f with borrowSwap nibbles in fTest f, Skip if 0Exclusive OR WREG with f

111111 (2 or 3)1 (2 or 3)1 (2 or 3)11 (2 or 3)1 (2 or 3)11 (2 or 3)1 (2 or 3)112

111111111

11

11 (2 or 3)1

001000100001011000010110011001100000001001000010001101000001010111001111011000000110001101000011010001100101

01010101

001101100001

01da00da01da101a11da001a010a000a01da11da11da10da11da10da00da00daffffffff111a001a110a01da01da00da00da100a01da

11da10da

10da011a10da

ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff

ffffffff

ffffffffffff

ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff

ffffffff

ffffffffffff

C, DC, Z, OV, NC, DC, Z, OV, NZ, NZZ, NNoneNoneNoneC, DC, Z, OV, NNoneNoneC, DC, Z, OV, NNoneNoneZ, NZ, NNone

NoneNoneC, DC, Z, OV, NC, Z, NZ, NC, Z, NZ, NNoneC, DC, Z, OV, N

C, DC, Z, OV, NC, DC, Z, OV, N

NoneNoneZ, N

1, 21, 21,221, 2441, 21, 2, 3, 41, 2, 3, 41, 21, 2, 3, 441, 21, 21

1, 2

1, 2

1, 2

1, 2

41, 2

BIT-ORIENTED FILE REGISTER OPERATIONSBCFBSFBTFSCBTFSSBTG

f, b, af, b, af, b, af, b, af, d, a

Bit Clear fBit Set fBit Test f, Skip if ClearBit Test f, Skip if SetBit Toggle f

111 (2 or 3)1 (2 or 3)1

10011000101110100111

bbbabbbabbbabbbabbba

ffffffffffffffffffff

ffffffffffffffffffff

NoneNoneNoneNoneNone

1, 21, 23, 43, 41, 2

Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.

5: If the table write starts the write cycle to internal memory, the write will continue until terminated.

PIC18F6585/8585/6680/8680

CONTROL OPERATIONSBCBNBNCBNNBNOVBNZBOVBRABZCALL

CLRWDTDAWGOTO

NOPNOPPOPPUSHRCALLRESETRETFIE

RETLWRETURNSLEEP

nnnnnnnnnn, s

——n

————n

s

ks—

Branch if CarryBranch if NegativeBranch if Not CarryBranch if Not NegativeBranch if Not OverflowBranch if Not ZeroBranch if OverflowBranch Unconditionally Branch if ZeroCall subroutine 1st word

2nd wordClear Watchdog TimerDecimal Adjust WREGGo to address 1st word

2nd wordNo OperationNo OperationPop top of return stack (TOS)Push top of return stack (TOS)Relative CallSoftware device ResetReturn from interrupt enable

Return with literal in WREG Return from SubroutineGo into Standby mode

1 (2)1 (2)1 (2)1 (2)1 (2)1 (2)1 (2)21 (2)2

112

1111212

221

1110111011101110111011101110110111101110111100000000111011110000111100000000110100000000

000000000000

00100110001101110101000101000nnn0000110skkkk000000001111kkkk0000xxxx000000001nnn00000000

110000000000

nnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnkkkkkkkk00000000kkkkkkkk0000xxxx00000000nnnn11110001

kkkk00010000

nnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnkkkkkkkk01000111kkkkkkkk0000xxxx01100101nnnn1111000s

kkkk001s0011

NoneNoneNoneNoneNoneNoneNoneNoneNoneNone

TO, PDCNone

NoneNoneNoneNoneNoneAllGIE/GIEH, PEIE/GIELNoneNoneTO, PD

4

TABLE 25-2: PIC18FXXX INSTRUCTION SET (CONTINUED)

Mnemonic,Operands


AffectedNotes

MSb LSb







PIC18F6585/8585/6680/8680

LITERAL OPERATIONSADDLWANDLWIORLWLFSR

MOVLBMOVLWMULLWRETLWSUBLWXORLW

kkkf, k

kkkkkk

Add literal and WREGAND literal with WREGInclusive OR literal with WREGMove literal (12-bit) 2nd word to FSRx 1st wordMove literal to BSR<3:0>Move literal to WREGMultiply literal with WREGReturn with literal in WREG Subtract WREG from literalExclusive OR literal with WREG

1112

111211

00000000000011101111000000000000000000000000

11111011100111100000000111101101110010001010

kkkkkkkkkkkk00ffkkkk0000kkkkkkkkkkkkkkkkkkkk

kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk

C, DC, Z, OV, NZ, NZ, NNone

NoneNoneNoneNoneC, DC, Z, OV, NZ, N

DATA MEMORY ↔ PROGRAM MEMORY OPERATIONSTBLRD*TBLRD*+TBLRD*-TBLRD+*TBLWT*TBLWT*+TBLWT*-TBLWT+*

Table ReadTable Read with post-incrementTable Read with post-decrementTable Read with pre-incrementTable WriteTable Write with post-incrementTable Write with post-decrementTable Write with pre-increment

2

2 (5)

00000000000000000000000000000000

00000000000000000000000000000000

00000000000000000000000000000000

10001001101010111100110111101111

NoneNoneNoneNoneNoneNoneNoneNone

TABLE 25-2: PIC18FXXX INSTRUCTION SET (CONTINUED)

Mnemonic,Operands


AffectedNotes

MSb LSb

PIC18F6585/8585/6680/8680

25.1 Instruction Set

ADDLW ADD literal to W

Syntax: [ label ] ADDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) + k → W

Status Affected: N, OV, C, DC, Z

Encoding: 0000 1111 kkkk kkkk

Description: The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.

Words: 1

Cycles: 1

Q Cycle Activity:Q1 Q2 Q3 Q4

Decode Readliteral ‘k’

Process Data

Write to W

Example: ADDLW 0x15

Before InstructionW = 0x10

After InstructionW = 0x25

ADDWF ADD W to f

Syntax: [ label ] ADDWF f [,d [,a] f [,d [,a]

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (W) + (f) → dest


Encoding: 0010 01da ffff ffff

Description: Add W to register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘d’ (default). If ‘a’ is ‘0’, the Access Bank will be selected. If ‘a’ is ‘1’, the BSR is used.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4Decode Read

register ‘f’Process

DataWrite to

destination

Example: ADDWF REG, 0, 0

Before InstructionW = 0x17REG = 0xC2

After InstructionW = 0xD9REG = 0xC2


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ADDWFC ADD W and Carry bit to f

Syntax: [ label ] ADDWFC f [,d [,a]]

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (W) + (f) + (C) → dest

Status Affected: N,OV, C, DC, Z


Description: Add W, the Carry Flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory loca-tion ‘f’. If ‘a’ is ‘0’, the Access Bank will be selected. If ‘a’ is ‘1’, the BSR will not be overridden.

Words: 1

Cycles: 1

Q Cycle Activity:



DataWrite to

destination

Example: ADDWFC REG, 0, 1

Before InstructionCarry bit = 1REG = 0x02W = 0x4D

After InstructionCarry bit = 0REG = 0x02W = 0x50

ANDLW AND literal with W

Syntax: [ label ] ANDLW k


Operation: (W) .AND. k → W

Status Affected: N, Z


Description: The contents of W are ANDed with the 8-bit literal ‘k’. The result is placed in W.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4Decode Read literal

‘k’Process

DataWrite to W

Example: ANDLW 0x5F

Before InstructionW = 0xA3

After InstructionW = 0x03


PIC18F6585/8585/6680/8680

ANDWF AND W with f

Syntax: [ label ] ANDWF f [,d [,a]]

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (W) .AND. (f) → dest



Description: The contents of W are AND’ed with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected. If ‘a’ is ‘1’, the BSR will not be overridden (default).

Words: 1

Cycles: 1

Q Cycle Activity:



DataWrite to

destination

Example: ANDWF REG, 0, 0

Before InstructionW = 0x17REG = 0xC2

After Instruction

W = 0x02REG = 0xC2

BC Branch if Carry

Syntax: [ label ] BC n

Operands: -128 ≤ n ≤ 127

Operation: if carry bit is ‘1’ (PC) + 2 + 2n → PC

Status Affected: None

Encoding: 1110 0010 nnnn nnnn

Description: If the Carry bit is ‘1’, then the program will branch.The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction.

Words: 1

Cycles: 1(2)

Q Cycle Activity:If Jump:


‘n’Process

DataWrite to PC

No operation

No operation

No operation

No operation

If No Jump:


‘n’Process

DataNo

operation

Example: HERE BC 5

Before InstructionPC = address (HERE)

After InstructionIf Carry = 1; PC = address (HERE+12)If Carry = 0; PC = address (HERE+2)


PIC18F6585/8585/6680/8680

BCF Bit Clear f

Syntax: [ label ] BCF f,b[,a]

Operands: 0 ≤ f ≤ 2550 ≤ b ≤ 7a ∈ [0,1]

Operation: 0 → f


Encoding: 1001 bbba ffff ffff

Description: Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default).

Words: 1

Cycles: 1


Decode Readregister ‘f’

Process Data

Writeregister ‘f’

Example: BCF FLAG_REG, 7, 0

Before InstructionFLAG_REG = 0xC7

After InstructionFLAG_REG = 0x47

BN Branch if Negative

Syntax: [ label ] BN n

Operands: -128 ≤ n ≤ 127

Operation: if negative bit is ‘1’(PC) + 2 + 2n → PC



Description: If the Negative bit is ‘1’, then the program will branch.The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction.

Words: 1

Cycles: 1(2)



‘n’Process

DataWrite to PC

No operation

No operation

No operation

No operation

If No Jump:


‘n’Process

DataNo

operation

Example: HERE BN Jump


After InstructionIf Negative = 1; PC = address (Jump)If Negative = 0; PC = address (HERE+2)

PIC18F6585/8585/6680/8680

BNC Branch if Not Carry

Syntax: [ label ] BNC n

Operands: -128 ≤ n ≤ 127

Operation: if carry bit is ‘0’(PC) + 2 + 2n → PC



Description: If the Carry bit is ‘0’, then the program will branch.The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction.

Words: 1

Cycles: 1(2)



‘n’Process

DataWrite to PC

No operation

No operation

No operation

No operation

If No Jump:


‘n’Process

DataNo

operation

Example: HERE BNC Jump


After InstructionIf Carry = 0; PC = address (Jump)If Carry = 1; PC = address (HERE+2)

BNN Branch if Not Negative

Syntax: [ label ] BNN n

Operands: -128 ≤ n ≤ 127

Operation: if negative bit is ‘0’(PC) + 2 + 2n → PC



Description: If the Negative bit is ‘0’, then the program will branch.The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction.

Words: 1

Cycles: 1(2)



‘n’Process

DataWrite to PC

No operation

No operation

No operation

No operation

If No Jump:


‘n’Process

DataNo

operation

Example: HERE BNN Jump


After InstructionIf Negative = 0; PC = address (Jump)If Negative = 1; PC = address (HERE+2)


PIC18F6585/8585/6680/8680

BNOV Branch if Not Overflow

Syntax: [ label ] BNOV n

Operands: -128 ≤ n ≤ 127

Operation: if overflow bit is ‘0’(PC) + 2 + 2n → PC



Description: If the Overflow bit is ‘0’, then the program will branch.The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction.

Words: 1

Cycles: 1(2)



‘n’Process

DataWrite to PC

No operation

No operation

No operation

No operation

If No Jump:


‘n’Process

DataNo

operation

Example: HERE BNOV Jump


After InstructionIf Overflow = 0; PC = address (Jump)If Overflow = 1; PC = address (HERE+2)

BNZ Branch if Not Zero

Syntax: [ label ] BNZ n

Operands: -128 ≤ n ≤ 127

Operation: if zero bit is ‘0’(PC) + 2 + 2n → PC



Description: If the Zero bit is ‘0’, then the program will branch.The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction.

Words: 1

Cycles: 1(2)



‘n’Process

DataWrite to PC

No operation

No operation

No operation

No operation

If No Jump:


‘n’Process

DataNo

operation

Example: HERE BNZ Jump


After InstructionIf Zero = 0; PC = address (Jump)If Zero = 1; PC = address (HERE+2)


PIC18F6585/8585/6680/8680

BRA Unconditional Branch

Syntax: [ label ] BRA n

Operands: -1024 ≤ n ≤ 1023

Operation: (PC) + 2 + 2n → PC


Encoding: 1101 0nnn nnnn nnnn

Description: Add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is a two-cycle instruction.

Words: 1

Cycles: 2

Q Cycle Activity:


‘n’Process

DataWrite to PC

No operation

No operation

No operation

No operation

Example: HERE BRA Jump


After InstructionPC = address (Jump)

BSF Bit Set f

Syntax: [ label ] BSF f,b[,a]

Operands: 0 ≤ f ≤ 2550 ≤ b ≤ 7a ∈ [0,1]

Operation: 1 → f



Description: Bit ‘b’ in register ‘f’ is set. If ‘a’ is ‘0’, Access Bank will be selected, over-riding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value.

Words: 1

Cycles: 1



Process Data


Example: BSF FLAG_REG, 7, 1

Before InstructionFLAG_REG = 0x0A

After InstructionFLAG_REG = 0x8A

PIC18F6585/8585/6680/8680

BTFSC Bit Test File, Skip if Clear

Syntax: [ label ] BTFSC f,b[,a]

Operands: 0 ≤ f ≤ 2550 ≤ b ≤ 7a ∈ [0,1]

Operation: skip if (f) = 0



Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skipped.If bit ‘b’ is ‘0’, then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default).

Words: 1

Cycles: 1(2)Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:



DataNo

operation

If skip:

Q1 Q2 Q3 Q4No

operationNo

operationNo

operationNo

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4No

operationNo

operationNo

operationNo

operation

No operation

No operation

No operation

No operation

Example: HEREFALSETRUE

BTFSC::

FLAG, 1, 0


After InstructionIf FLAG<1> = 0; PC = address (TRUE)If FLAG<1> = 1; PC = address (FALSE)

BTFSS Bit Test File, Skip if Set

Syntax: [ label ] BTFSS f,b[,a]

Operands: 0 ≤ f ≤ 2550 ≤ b < 7a ∈ [0,1]

Operation: skip if (f) = 1



Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped.If bit ‘b’ is ‘1’, then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default).

Words: 1





Process Data

No operation

If skip:Q1 Q2 Q3 Q4No

operationNo

operationNo

operationNo

operation

If skip and followed by 2-word instruction:Q1 Q2 Q3 Q4No

operationNo

operationNo

operationNo

operation

No operation

No operation

No operation

No operation

Example: HEREFALSETRUE

BTFSS::

FLAG, 1, 0


After InstructionIf FLAG<1> = 0; PC = address (FALSE)If FLAG<1> = 1; PC = address (TRUE)

PIC18F6585/8585/6680/8680

BTG Bit Toggle f

Syntax: [ label ] BTG f,b[,a]

Operands: 0 ≤ f ≤ 2550 ≤ b < 7a ∈ [0,1]

Operation: (f) → f



Description: Bit ‘b’ in data memory location ‘f’ is inverted. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default).

Words: 1

Cycles: 1



Process Data


Example: BTG PORTC, 4, 0

Before Instruction:PORTC = 0111 0101 [0x75]

After Instruction:PORTC = 0110 0101 [0x65]

BOV Branch if Overflow

Syntax: [ label ] BOV n

Operands: -128 ≤ n ≤ 127

Operation: if overflow bit is ‘1’(PC) + 2 + 2n → PC



Description: If the Overflow bit is ‘1’, then the program will branch.The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction.

Words: 1

Cycles: 1(2)



‘n’Process

DataWrite to PC

No operation

No operation

No operation

No operation

If No Jump:


‘n’Process

DataNo

operation

Example: HERE BOV Jump


After InstructionIf Overflow = 1; PC = address (Jump)If Overflow = 0; PC = address (HERE+2)

PIC18F6585/8585/6680/8680

BZ Branch if Zero

Syntax: [ label ] BZ n

Operands: -128 ≤ n ≤ 127

Operation: if Zero bit is ‘1’(PC) + 2 + 2n → PC



Description: If the Zero bit is ‘1’, then the program will branch.The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction.

Words: 1

Cycles: 1(2)



‘n’Process

DataWrite to PC

No operation

No operation

No operation

No operation

If No Jump:


‘n’Process

DataNo

operation

Example: HERE BZ Jump


After InstructionIf Zero = 1; PC = address (Jump)If Zero = 0; PC = address (HERE+2)

CALL Subroutine Call

Syntax: [ label ] CALL k [,s]

Operands: 0 ≤ k ≤ 1048575s ∈ [0,1]

Operation: (PC) + 4 → TOS,k → PC<20:1>,if s = 1(W) → WS,(STATUS) → STATUSS,(BSR) → BSRS


Encoding:1st word (k<7:0>)2nd word(k<19:8>)

11101111

110sk19kkk

k7kkkkkkk

kkkk0kkkk8

Description: Subroutine call of entire 2-Mbyte memory range. First, return address (PC+ 4) is pushed onto the return stack. If ‘s’ = 1, the W, Status and BSR registers are also pushed into their respective shadow registers, WS, STATUSS and BSRS. If ‘s’ = 0, no update occurs (default). Then, the 20-bit value ‘k’ is loaded into PC<20:1>. CALL is a two-cycle instruction.

Words: 2

Cycles: 2


Decode Read literal ‘k’<7:0>,

Push PC to stack

Read literal ‘k’<19:8>,

Write to PC

No operation

No operation

No operation

No operation

Example: HERE CALL THERE,1


After InstructionPC = address (THERE)TOS = address (HERE + 4)WS = WBSRS = BSRSTATUSS = STATUS

PIC18F6585/8585/6680/8680

CLRF Clear f

Syntax: [ label ] CLRF f [,a]

Operands: 0 ≤ f ≤ 255a ∈ [0,1]

Operation: 000h → f1 → Z

Status Affected: Z

Encoding: 0110 101a ffff ffff

Description: Clears the contents of the specified register. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default).

Words: 1

Cycles: 1



Process Data


Example: CLRF FLAG_REG,1

Before InstructionFLAG_REG = 0x5A

After InstructionFLAG_REG = 0x00

CLRWDT Clear Watchdog Timer

Syntax: [ label ] CLRWDT

Operands: None

Operation: 000h → WDT,000h → WDT postscaler,1 → TO,1 → PD

Status Affected: TO, PD

Encoding: 0000 0000 0000 0100

Description: CLRWDT instruction resets the Watchdog Timer. It also resets the postscaler of the WDT. Status bits TO and PD are set.

Words: 1

Cycles: 1


Decode No operation

Process Data

No operation

Example: CLRWDT

Before InstructionWDT Counter = ?

After InstructionWDT Counter = 0x00WDT Postscaler = 0TO = 1PD = 1


PIC18F6585/8585/6680/8680

COMF Complement f

Syntax: [ label ] COMF f [,d [,a]]

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: → dest



Description: The contents of register ‘f’ are com-plemented. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default).

Words: 1

Cycles: 1



Process Data

Write todestination

Example: COMF REG, 0, 0

Before InstructionREG = 0x13

After InstructionREG = 0x13W = 0xEC

( f )

CPFSEQ Compare f with W, skip if f = W

Syntax: [ label ] CPFSEQ f [,a]

Operands: 0 ≤ f ≤ 255a ∈ [0,1]

Operation: (f) – (W), skip if (f) = (W) (unsigned comparison)



Description: Compares the contents of data memory location ‘f’ to the contents of W by performing an unsigned subtraction.If ‘f’ = W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default).

Words: 1





Process Data

No operation


operationNo

operationNo

operationNo

operation


operationNo

operationNo

operationNo

operation

No operation

No operation

No operation

No operation

Example: HERE CPFSEQ REG, 0NEQUAL :EQUAL :

Before InstructionPC Address = HERE

W = ?REG = ?

After InstructionIf REG = W; PC = Address (EQUAL)If REG ≠ W; PC = Address (NEQUAL)


PIC18F6585/8585/6680/8680

CPFSGT Compare f with W, skip if f > W

Syntax: [ label ] CPFSGT f [,a]

Operands: 0 ≤ f ≤ 255a ∈ [0,1]

Operation: (f) − (W),skip if (f) > (W) (unsigned comparison)



Description: Compares the contents of data memory location ‘f’ to the contents of the W by performing an unsigned subtraction.If the contents of ‘f’ are greater than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default).

Words: 1





Process Data

No operation


operationNo

operationNo

operationNo

operation


operationNo

operationNo

operationNo

operation

No operation

No operation

No operation

No operation

Example: HERE CPFSGT REG, 0NGREATER :GREATER :

Before InstructionPC = Address (HERE)W = ?

After InstructionIf REG > W; PC = Address (GREATER)If REG ≤ W; PC = Address (NGREATER)

CPFSLT Compare f with W, skip if f < W

Syntax: [ label ] CPFSLT f [,a]

Operands: 0 ≤ f ≤ 255a ∈ [0,1]

Operation: (f) – (W),skip if (f) < (W) (unsigned comparison)



Description: Compares the contents of data memory location ‘f’ to the contents of W by performing an unsigned subtraction.If the contents of ‘f’ are less than the contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank will be selected. If ’a’ is ‘1’, the BSR will not be overrid-den (default).

Words: 1





Process Data

No operation


operationNo

operationNo

operationNo

operation


operationNo

operationNo

operationNo

operation

No operation

No operation

No operation

No operation

Example: HERE CPFSLT REG, 1NLESS :LESS :

Before InstructionPC = Address (HERE)W = ?

After InstructionIf REG < W; PC = Address (LESS)If REG ≥ W; PC = Address (NLESS)

PIC18F6585/8585/6680/8680

DAW Decimal Adjust W Register

Syntax: [ label ] DAW

Operands: None

Operation: If [W<3:0> >9] or [DC = 1] then(W<3:0>) + 6 → W<3:0>;else (W<3:0>) → W<3:0>;

If [W<7:4> >9] or [C = 1] then(W<7:4>) + 6 → W<7:4>;else (W<7:4>) → W<7:4>;

Status Affected: C

Encoding: 0000 0000 0000 0111

Description: DAW adjusts the eight-bit value in W, resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result.

Words: 1

Cycles: 1


Decode Readregister W

Process Data

WriteW

Example1: DAW

Before InstructionW = 0xA5C = 0DC = 0

After Instruction

W = 0x05C = 1DC = 0

Example 2:

Before Instruction

W = 0xCEC = 0DC = 0

After InstructionW = 0x34C = 1DC = 0

DECF Decrement f

Syntax: [ label ] DECF f [,d [,a]]

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (f) – 1 → dest

Status Affected: C, DC, N, OV, Z


Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default).

Words: 1

Cycles: 1



Process Data

Write to destination

Example: DECF CNT, 1, 0

Before InstructionCNT = 0x01Z = 0

After InstructionCNT = 0x00Z = 1

PIC18F6585/8585/6680/8680

DECFSZ Decrement f, skip if 0

Syntax: [ label ] DECFSZ f [,d [,a]]

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (f) – 1 → dest,skip if result = 0



Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default).If the result is ‘0’, the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default).

Words: 1





Process Data



operationNo

operationNo

operationNo

operation


operationNo

operationNo

operationNo

operation

No operation

No operation

No operation

No operation

Example: HERE DECFSZ CNT, 1, 1 GOTO LOOPCONTINUE

Before InstructionPC = Address (HERE)

After InstructionCNT = CNT - 1If CNT = 0; PC = Address (CONTINUE)If CNT ≠ 0; PC = Address (HERE+2)

DCFSNZ Decrement f, skip if not 0

Syntax: [ label ] DCFSNZ f [,d [,a]]

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (f) – 1 → dest,skip if result ≠ 0



Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default).If the result is not ‘0’, the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default).

Words: 1





Process Data



operationNo

operationNo

operationNo

operation


operationNo

operationNo

operationNo

operation

No operation

No operation

No operation

No operation

Example: HERE DCFSNZ TEMP, 1, 0ZERO : NZERO :

Before InstructionTEMP = ?

After InstructionTEMP = TEMP - 1,If TEMP = 0; PC = Address (ZERO)If TEMP ≠ 0; PC = Address (NZERO)


PIC18F6585/8585/6680/8680

GOTO Unconditional Branch

Syntax: [ label ] GOTO k

Operands: 0 ≤ k ≤ 1048575

Operation: k → PC<20:1>


Encoding:1st word (k<7:0>)2nd word(k<19:8>)

11101111

1111k19kkk

k7kkkkkkk

kkkk0kkkk8

Description: GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range. The 20-bit value ‘k’ is loaded into PC<20:1>. GOTO is always a two-cycle instruction.

Words: 2

Cycles: 2


Decode Read literal ‘k’<7:0>,

No operation

Read literal ‘k’<19:8>,

Write to PC

No operation

No operation

No operation

No operation

Example: GOTO THERE

After InstructionPC = Address (THERE)

INCF Increment f

Syntax: [ label ] INCF f [,d [,a]]

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (f) + 1 → dest

Status Affected: C, DC, N, OV, Z


Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default).

Words: 1

Cycles: 1



Process Data


Example: INCF CNT, 1, 0

Before InstructionCNT = 0xFFZ = 0C = ?DC = ?

After InstructionCNT = 0x00Z = 1C = 1DC = 1

PIC18F6585/8585/6680/8680

INCFSZ Increment f, skip if 0

Syntax: [ label ] INCFSZ f [,d [,a]]

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (f) + 1 → dest,skip if result = 0



Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default).If the result is ‘0’, the next instruc-tion which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default).

Words: 1





Process Data



operationNo

operationNo

operationNo

operation


operationNo

operationNo

operationNo

operation

No operation

No operation

No operation

No operation

Example: HERE INCFSZ CNT, 1, 0NZERO : ZERO :


After InstructionCNT = CNT + 1If CNT = 0; PC = Address (ZERO)If CNT ≠ 0; PC = Address (NZERO)

INFSNZ Increment f, skip if not 0

Syntax: [ label ] INFSNZ f [,d [,a]]

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (f) + 1 → dest, skip if result ≠ 0



Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default).If the result is not ‘0’, the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default).

Words: 1





Process Data



operationNo

operationNo

operationNo

operation


operationNo

operationNo

operationNo

operation

No operation

No operation

No operation

No operation

Example: HERE INFSNZ REG, 1, 0ZERONZERO


After InstructionREG = REG + 1If REG ≠ 0; PC = Address (NZERO)If REG = 0; PC = Address (ZERO)


PIC18F6585/8585/6680/8680

IORLW Inclusive OR literal with W

Syntax: [ label ] IORLW k


Operation: (W) .OR. k → W



Description: The contents of W are OR’ed with the eight-bit literal ‘k’. The result is placed in W.

Words: 1

Cycles: 1

Q Cycle Activity:


literal ‘k’Process

DataWrite to W

Example: IORLW 0x35

Before InstructionW = 0x9A

After InstructionW = 0xBF

IORWF Inclusive OR W with f

Syntax: [ label ] IORWF f [,d [,a]]

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (W) .OR. (f) → dest



Description: Inclusive OR W with register ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default).

Words: 1

Cycles: 1



Process Data


Example: IORWF RESULT, 0, 1

Before InstructionRESULT = 0x13W = 0x91

After InstructionRESULT = 0x13W = 0x93


PIC18F6585/8585/6680/8680

LFSR Load FSR

Syntax: [ label ] LFSR f,k

Operands: 0 ≤ f ≤ 20 ≤ k ≤ 4095

Operation: k → FSRf


Encoding: 11101111

11100000

00ffk7kkk

k11kkkkkkk

Description: The 12-bit literal ‘k’ is loaded into the file select register pointed to by ‘f’.

Words: 2

Cycles: 2


Decode Read literal ‘k’ MSB

Process Data

Writeliteral ‘k’ MSB to FSRfH

Decode Read literal ‘k’ LSB

Process Data

Write literal ‘k’ to FSRfL

Example: LFSR 2, 0x3AB

After InstructionFSR2H = 0x03FSR2L = 0xAB

MOVF Move f

Syntax: [ label ] MOVF f [,d [,a]]

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: f → dest



Description: The contents of register ‘f’ are moved to a destination dependent upon the status of ‘d’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). Location ‘f’ can be any-where in the 256-byte bank. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default).

Words: 1

Cycles: 1



Process Data

Write W

Example: MOVF REG, 0, 0

Before InstructionREG = 0x22W = 0xFF

After InstructionREG = 0x22W = 0x22


PIC18F6585/8585/6680/8680

MOVFF Move f to f

Syntax: [ label ] MOVFF fs,fdOperands: 0 ≤ fs ≤ 4095

0 ≤ fd ≤ 4095

Operation: (fs) → fdStatus Affected: None

Encoding:1st word (source)2nd word (destin.)

11001111

ffffffff

ffffffff

ffffsffffd

Description: The contents of source register ‘fs’ are moved to destination register ‘fd’. Location of source ‘fs’ can be anywhere in the 4096-byte data space (000h to FFFh) and location of destination ‘fd’ can also be anywhere from 000h to FFFh.Either source or destination can be W (a useful special situation).MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port).The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register

Words: 2

Cycles: 2 (3)



(src)

Process Data

No operation

Decode No operation

No dummy read

No operation

Write register ‘f’

(dest)

Example: MOVFF REG1, REG2

Before InstructionREG1 = 0x33REG2 = 0x11

After InstructionREG1 = 0x33,REG2 = 0x33

MOVLB Move literal to low nibble in BSR

Syntax: [ label ] MOVLB k


Operation: k → BSR



Description: The 8-bit literal ‘k’ is loaded into the Bank Select Register (BSR).

Words: 1

Cycles: 1


Decode Read literal ‘k’

Process Data

Writeliteral ‘k’ to

BSR

Example: MOVLB 5

Before InstructionBSR register = 0x02

After InstructionBSR register = 0x05


PIC18F6585/8585/6680/8680

MOVLW Move literal to W

Syntax: [ label ] MOVLW k


Operation: k → W



Description: The eight-bit literal ‘k’ is loaded into W.

Words: 1

Cycles: 1



Process Data

Write to W

Example: MOVLW 0x5A

After InstructionW = 0x5A

MOVWF Move W to f

Syntax: [ label ] MOVWF f [,a]

Operands: 0 ≤ f ≤ 255a ∈ [0,1]

Operation: (W) → f



Description: Move data from W to register ‘f’. Location ‘f’ can be anywhere in the 256-byte bank. If ‘a’ is ‘0’, the Access Bank will be selected, over-riding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default).

Words: 1

Cycles: 1



Process Data


Example: MOVWF REG, 0

Before InstructionW = 0x4FREG = 0xFF

After InstructionW = 0x4FREG = 0x4F


PIC18F6585/8585/6680/8680

MULLW Multiply Literal with W

Syntax: [ label ] MULLW k


Operation: (W) x k → PRODH:PRODL



Description: An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in PRODH:PRODL register pair. PRODH contains the high byte.W is unchanged.None of the status flags are affected.Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected.

Words: 1

Cycles: 1


Decode Read literal ‘k’

Process Data

Write registers PRODH:PRODL

Example: MULLW 0xC4

Before InstructionW = 0xE2PRODH = ?PRODL = ?

After Instruction

W = 0xE2PRODH = 0xADPRODL = 0x08

MULWF Multiply W with f

Syntax: [ label ] MULWF f [,a]

Operands: 0 ≤ f ≤ 255a ∈ [0,1]

Operation: (W) x (f) → PRODH:PRODL



Description:’ An unsigned multiplication is carried out between the contents of W and the register file location ‘f’. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte.Both W and ‘f’ are unchanged.None of the status flags are affected.Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default).

Words: 1

Cycles: 1



Process Data

Writeregisters PRODH:PRODL

Example: MULWF REG, 1

Before InstructionW = 0xC4REG = 0xB5PRODH = ?PRODL = ?

After InstructionW = 0xC4REG = 0xB5PRODH = 0x8APRODL = 0x94


PIC18F6585/8585/6680/8680

NEGF Negate f

Syntax: [ label ] NEGF f [,a]

Operands: 0 ≤ f ≤ 255a ∈ [0,1]

Operation: ( f ) + 1 → f



Description: Location ‘f’ is negated using two’s complement. The result is placed in the data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value.

Words: 1

Cycles: 1



Process Data

Write register ‘f’

Example: NEGF REG, 1

Before InstructionREG = 0011 1010 [0x3A]

After InstructionREG = 1100 0110 [0xC6]

NOP No Operation

Syntax: [ label ] NOP

Operands: None

Operation: No operation


Encoding: 00001111

0000xxxx

0000xxxx

0000xxxx

Description: No operation.

Words: 1

Cycles: 1


Decode No operation

No operation

No operation

Example:

None.


PIC18F6585/8585/6680/8680

POP Pop Top of Return Stack

Syntax: [ label ] POP

Operands: None

Operation: (TOS) → bit bucket


Encoding: 0000 0000 0000 0110

Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack.

Words: 1

Cycles: 1


Decode Nooperation

POP TOS value

Nooperation

Example: POPGOTO NEW

Before InstructionTOS = 0031A2hStack (1 level down)= 014332h

After InstructionTOS = 014332hPC = NEW

PUSH Push Top of Return Stack

Syntax: [ label ] PUSH

Operands: None

Operation: (PC+2) → TOS


Encoding: 0000 0000 0000 0101

Description: The PC+2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack.This instruction allows implement-ing a software stack by modifying TOS, and then pushing it onto the return stack.

Words: 1

Cycles: 1


Decode PUSH PC+2 onto return

stack

No operation

No operation

Example: PUSH

Before InstructionTOS = 00345AhPC = 000124h

After InstructionPC = 000126hTOS = 000126hStack (1 level down)= 00345Ah


PIC18F6585/8585/6680/8680

RCALL Relative Call

Syntax: [ label ] RCALL n

Operands: -1024 ≤ n ≤ 1023

Operation: (PC) + 2 → TOS,(PC) + 2 + 2n → PC


Encoding: 1101 1nnn nnnn nnnn

Description: Subroutine call with a jump up to 1K from the current location. First, return address (PC+2) is pushed onto the stack. Then, add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is a two-cycle instruction.

Words: 1

Cycles: 2


Decode Read literal ‘n’

Push PC to stack

Process Data

Write to PC

No operation

No operation

No operation

No operation

Example: HERE RCALL Jump


After InstructionPC = Address (Jump)TOS = Address (HERE+2)

RESET Reset

Syntax: [ label ] RESET

Operands: None

Operation: Reset all registers and flags that are affected by a MCLR Reset.

Status Affected: All

Encoding: 0000 0000 1111 1111

Description: This instruction provides a way to execute a MCLR Reset in software.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4Decode Start

ResetNo

operationNo

operation

Example: RESET

After InstructionRegisters = Reset ValueFlags* = Reset Value


PIC18F6585/8585/6680/8680

RETFIE Return from Interrupt

Syntax: [ label ] RETFIE [s]

Operands: s ∈ [0,1]

Operation: (TOS) → PC,1 → GIE/GIEH or PEIE/GIEL,if s = 1(WS) → W,(STATUSS) → STATUS,(BSRS) → BSR,PCLATU, PCLATH are unchanged.

Status Affected: GIE/GIEH, PEIE/GIEL.

Encoding: 0000 0000 0001 000s

Description: Return from interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low priority global interrupt enable bit. If ‘s’ = 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers, W, Status and BSR. If ‘s’ = 0, no update of these registers occurs (default).

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4Decode No

operationNo

operationPop PC from

stack

Set GIEH or GIEL

No operation

No operation

No operation

No operation

Example: RETFIE 1

After InterruptPC = TOSW = WSBSR = BSRSSTATUS = STATUSSGIE/GIEH, PEIE/GIEL = 1

RETLW Return Literal to W

Syntax: [ label ] RETLW k


Operation: k → W,(TOS) → PC,PCLATU, PCLATH are unchanged



Description: W is loaded with the eight-bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged.

Words: 1

Cycles: 2



Process Data

Pop PC from stack, Write

to W

No operation

No operation

No operation

No operation

Example:

CALL TABLE ; W contains table ; offset value ; W now has ; table value :TABLE

ADDWF PCL ; W = offsetRETLW k0 ; Begin tableRETLW k1 ;

: :

RETLW kn ; End of table

Before Instruction

W = 0x07

After Instruction

W = value of kn


PIC18F6585/8585/6680/8680

RETURN Return from Subroutine

Syntax: [ label ] RETURN [s]

Operands: s ∈ [0,1]

Operation: (TOS) → PC,if s = 1(WS) → W,(STATUSS) → STATUS,(BSRS) → BSR,PCLATU, PCLATH are unchanged


Encoding: 0000 0000 0001 001s

Description: Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter. If ‘s’ = 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers, W, Status and BSR. If ‘s’ = 0, no update of these registers occurs (default).

Words: 1

Cycles: 2

Q Cycle Activity:


operationProcess

DataPop PC

from stack

No operation

No operation

No operation

No operation

Example: RETURN

After InterruptPC = TOS

RLCF Rotate Left f through Carry

Syntax: [ label ] RLCF f [,d [,a]]

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (f<n>) → dest<n+1>,(f<7>) → C,(C) → dest<0>

Status Affected: C, N, Z


Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default).

Words: 1

Cycles: 1

Q Cycle Activity:



DataWrite to

destination

Example: RLCF REG, 0, 0

Before InstructionREG = 1110 0110C = 0

After InstructionREG = 1110 0110

W = 1100 1100C = 1

C register f

PIC18F6585/8585/6680/8680

RLNCF Rotate Left f (no carry)

Syntax: [ label ] RLNCF f [,d [,a]]

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (f<n>) → dest<n+1>,(f<7>) → dest<0>



Description: The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0,’ the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the BSR value (default).

Words: 1

Cycles: 1



Process Data


Example: RLNCF REG, 1, 0

Before InstructionREG = 1010 1011


register f

RRCF Rotate Right f through Carry

Syntax: [ label ] RRCF f [,d [,a]]

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (f<n>) → dest<n-1>,(f<0>) → C,(C) → dest<7>

Status Affected: C, N, Z


Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the BSR value (default).

Words: 1

Cycles: 1

Q Cycle Activity:



DataWrite to

destination

Example: RRCF REG, 0, 0

Before InstructionREG = 1110 0110C = 0


W = 0111 0011C = 0

C register f

PIC18F6585/8585/6680/8680

RRNCF Rotate Right f (no carry)

Syntax: [ label ] RRNCF f [,d [,a]]

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (f<n>) → dest<n-1>,(f<0>) → dest<7>



Description:’ The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the BSR value (default).

Words: 1

Cycles: 1



Process Data


Example 1: RRNCF REG, 1, 0

Before InstructionREG = 1101 0111


Example 2: RRNCF REG, 0, 0

Before InstructionW = ?REG = 1101 0111

After InstructionW = 1110 1011REG = 1101 0111

register f

SETF Set f

Syntax: [ label ] SETF f [,a]

Operands: 0 ≤ f ≤ 255a ∈ [0,1]

Operation: FFh → f



Description: The contents of the specified register are set to FFh. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the BSR value (default).

Words: 1

Cycles: 1



Process Data


Example: SETF REG,1

Before InstructionREG = 0x5A

After InstructionREG = 0xFF

PIC18F6585/8585/6680/8680

SLEEP Enter Sleep mode

Syntax: [ label ] SLEEP

Operands: None

Operation: 00h → WDT,0 → WDT postscaler,1 → TO,0 → PD

Status Affected: TO, PD

Encoding: 0000 0000 0000 0011

Description: The Power-down status bit (PD) is cleared. The Time-out status bit (TO) is set. Watchdog Timer and its postscaler are cleared.The processor is put into Sleep mode with the oscillator stopped.

Words: 1

Cycles: 1

Q Cycle Activity:


operationProcess

DataGo to

SLEEP

Example: SLEEP

Before InstructionTO = ?PD = ?

After InstructionTO = 1 †PD = 0

† If WDT causes wake-up, this bit is cleared.

SUBFWP Subtract f from W with borrow

Syntax: [ label ] SUBFWB f [,d [,a]]

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (W) – (f) – (C) → dest



Description: Subtract register ‘f’ and carry flag (borrow) from W (2’s complement method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the BSR value (default).

Words: 1

Cycles: 1

Q Cycle Activity:



DataWrite to

destination

Example 1: SUBFWB REG, 1, 0

Before InstructionREG = 3W = 2C = 1

After InstructionREG = FFW = 2C = 0Z = 0N = 1 ; result is negative



After InstructionREG = 2W = 3C = 1Z = 0N = 0 ; result is positive



After InstructionREG = 0W = 2C = 1Z = 1 ; result is zeroN = 0


PIC18F6585/8585/6680/8680

SUBLW Subtract W from literal

Syntax: [ label ] SUBLW k


Operation: k – (W) → W



Description: W is subtracted from the eight-bit literal ‘k’. The result is placed in W.

Words: 1

Cycles: 1



Process Data

Write to W

Example 1: SUBLW 0x02

Before InstructionW = 1C = ?

After InstructionW = 1C = 1 ; result is positiveZ = 0N = 0



After InstructionW = 0C = 1 ; result is zeroZ = 1N = 0



After InstructionW = FF ; (2’s complement)C = 0 ; result is negativeZ = 0N = 1

SUBWF Subtract W from f

Syntax: [ label ] SUBWF f [,d [,a]]

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (f) – (W) → dest



Description: Subtract W from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the BSR value (default).

Words: 1

Cycles: 1

Q Cycle Activity:



DataWrite to

destination

Example 1: SUBWF REG, 1, 0

Before InstructionREG = 3W = 2C = ?

After InstructionREG = 1W = 2C = 1 ; result is positiveZ = 0N = 0



After InstructionREG = 2W = 0C = 1 ; result is zeroZ = 1N = 0



After InstructionREG = FFh ;(2’s complement)W = 2C = 0 ; result is negativeZ = 0N = 1


PIC18F6585/8585/6680/8680

SUBWFB Subtract W from f with Borrow

Syntax: [ label ] SUBWFB f [,d [,a]]

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (f) – (W) – (C) → dest



Description: Subtract W and the Carry flag (bor-row) from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the BSR value (default).

Words: 1

Cycles: 1



Process Data


Example 1: SUBWFB REG, 1, 0

Before InstructionREG = 0x19 (0001 1001)W = 0x0D (0000 1101)C = 1

After InstructionREG = 0x0C (0000 1011)W = 0x0D (0000 1101)C = 1Z = 0N = 0 ; result is positive


Before InstructionREG = 0x1B (0001 1011)W = 0x1A (0001 1010)C = 0

After InstructionREG = 0x1B (0001 1011)W = 0x00C = 1Z = 1 ; result is zeroN = 0


Before InstructionREG = 0x03 (0000 0011)W = 0x0E (0000 1101)C = 1

After InstructionREG = 0xF5 (1111 0100)

; [2’s comp]W = 0x0E (0000 1101)C = 0Z = 0N = 1 ; result is negative

SWAPF Swap f

Syntax: [ label ] SWAPF f [,d [,a]]

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (f<3:0>) → dest<7:4>,(f<7:4>) → dest<3:0>



Description: The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the BSR value (default).

Words: 1

Cycles: 1

Q Cycle Activity:



DataWrite to

destination

Example: SWAPF REG, 1, 0

Before InstructionREG = 0x53

After InstructionREG = 0x35

PIC18F6585/8585/6680/8680

TBLRD Table Read

Syntax: [ label ] TBLRD ( *; *+; *-; +*)

Operands: None

Operation: if TBLRD *,(Prog Mem (TBLPTR)) → TABLAT;TBLPTR – No Change;if TBLRD *+,(Prog Mem (TBLPTR)) → TABLAT;(TBLPTR) + 1 → TBLPTR;if TBLRD *-,(Prog Mem (TBLPTR)) → TABLAT;(TBLPTR) – 1 → TBLPTR;if TBLRD +*,(TBLPTR) + 1 → TBLPTR;(Prog Mem (TBLPTR)) → TABLAT;

Status Affected:None

Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +*

Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used.The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range.

TBLPTR[0] = 0: Least Significant Byte of Program Memory Word

TBLPTR[0] = 1: Most Significant Byte of Program Memory Word

The TBLRD instruction can modify the value of TBLPTR as follows:• no change• post-increment• post-decrement• pre-increment

Words: 1

Cycles: 2

Q Cycle Activity:


operationNo

operationNo

operation

No operation

No operation(Read

Program Memory)

No operation

No operation(Write

TABLAT)

TBLRD Table Read (Continued)

Example1: TBLRD *+ ;

Before InstructionTABLAT = 0x55TBLPTR = 0x00A356MEMORY(0x00A356) = 0x34

After InstructionTABLAT = 0x34TBLPTR = 0x00A357

Example2: TBLRD +* ;

Before InstructionTABLAT = 0xAATBLPTR = 0x01A357MEMORY(0x01A357) = 0x12MEMORY(0x01A358) = 0x34

After InstructionTABLAT = 0x34TBLPTR = 0x01A358


PIC18F6585/8585/6680/8680

TBLWT Table Write

Syntax: [ label ] TBLWT ( *; *+; *-; +*)

Operands: None

Operation: if TBLWT*,(TABLAT) → Holding Register;TBLPTR – No Change;if TBLWT*+,(TABLAT) → Holding Register;(TBLPTR) + 1 → TBLPTR;if TBLWT*-,(TABLAT) → Holding Register;(TBLPTR) – 1 → TBLPTR;if TBLWT+*,(TBLPTR) + 1 → TBLPTR;(TABLAT) → Holding Register;


Encoding: 0000 0000 0000 11nnnn=0 * =1 *+ =2 *- =3 +*

Description: This instruction uses the 3 LSBs of TBLPTR to determine which of the 8 holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section 5.0 “Flash Program Memory” for additional details on programming Flash memory.)The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-MBtye address range. The LSb of the TBLPTR selects which byte of the program memory location to access.

TBLPTR[0] = 0:Least Significant Byte of Program Memory Word

TBLPTR[0] = 1:Most Significant Byte of Program Memory Word

The TBLWT instruction can modify the value of TBLPTR as follows:

• no change• post-increment• post-decrement

• pre-increment

TBLWT Table Write (Continued)

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No operation

No operation

No operation

No operation

No operation

(ReadTABLAT)

No operation

No operation(Write to Holding

Register )

Example1: TBLWT *+;

Before InstructionTABLAT = 0x55TBLPTR = 0x00A356HOLDING REGISTER (0x00A356) = 0xFF

After Instructions (table write completion)TABLAT = 0x55TBLPTR = 0x00A357HOLDING REGISTER (0x00A356) = 0x55

Example 2: TBLWT +*;

Before InstructionTABLAT = 0x34TBLPTR = 0x01389AHOLDING REGISTER (0x01389A) = 0xFFHOLDING REGISTER (0x01389B) = 0xFF

After Instruction (table write completion)TABLAT = 0x34TBLPTR = 0x01389BHOLDING REGISTER (0x01389A) = 0xFFHOLDING REGISTER (0x01389B) = 0x34


PIC18F6585/8585/6680/8680

TSTFSZ Test f, skip if 0

Syntax: [ label ] TSTFSZ f [,a]

Operands: 0 ≤ f ≤ 255a ∈ [0,1]

Operation: skip if f = 0



Description: If ‘f’ = 0, the next instruction, fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the BSR value (default).

Words: 1



Q Cycle Activity:



DataNo

operation

If skip:

Q1 Q2 Q3 Q4No

operationNo

operationNo

operationNo

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4No

operationNo

operationNo

operationNo

operation

No operation

No operation

No operation

No operation

Example: HERE TSTFSZ CNT, 1NZERO :ZERO :


After InstructionIf CNT = 0x00, PC = Address (ZERO)If CNT ≠ 0x00, PC = Address (NZERO)

XORLW Exclusive OR literal with W

Syntax: [ label ] XORLW k


Operation: (W) .XOR. k → W



Description: The contents of W are XORed with the 8-bit literal ‘k’. The result is placed in W.

Words: 1

Cycles: 1



Process Data

Write to W

Example: XORLW 0xAF

Before Instruction

W = 0xB5

After Instruction

W = 0x1A


PIC18F6585/8585/6680/8680

XORWF Exclusive OR W with f

Syntax: [ label ] XORWF f [,d [,a]]

Operands: 0 ≤ f ≤ 255d ∈ [0,1]a ∈ [0,1]

Operation: (W) .XOR. (f) → dest



Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the BSR value (default).

Words: 1

Cycles: 1



Process Data


Example: XORWF REG, 1, 0

Before InstructionREG = 0xAFW = 0xB5

After InstructionREG = 0x1AW = 0xB5


PIC18F6585/8585/6680/8680

26.0 DEVELOPMENT SUPPORT

The PICmicro® microcontrollers are supported with afull range of hardware and software development tools:

• Integrated Development Environment

- MPLAB® IDE Software• Assemblers/Compilers/Linkers

- MPASMTM Assembler

- MPLAB C17 and MPLAB C18 C Compilers- MPLINKTM Object Linker/

MPLIBTM Object Librarian- MPLAB C30 C Compiler- MPLAB ASM30 Assembler/Linker/Library

• Simulators- MPLAB SIM Software Simulator- MPLAB dsPIC30 Software Simulator

• Emulators- MPLAB ICE 2000 In-Circuit Emulator- MPLAB ICE 4000 In-Circuit Emulator

• In-Circuit Debugger- MPLAB ICD 2

• Device Programmers

- PRO MATE® II Universal Device Programmer- PICSTART® Plus Development Programmer- MPLAB PM3 Device Programmer

• Low-Cost Demonstration Boards- PICDEMTM 1 Demonstration Board- PICDEM.netTM Demonstration Board

- PICDEM 2 Plus Demonstration Board- PICDEM 3 Demonstration Board- PICDEM 4 Demonstration Board

- PICDEM 17 Demonstration Board- PICDEM 18R Demonstration Board- PICDEM LIN Demonstration Board

- PICDEM USB Demonstration Board• Evaluation Kits

- KEELOQ®

- PICDEM MSC- microID®

- CAN

- PowerSmart®

- Analog

26.1 MPLAB Integrated Development Environment Software

The MPLAB IDE software brings an ease of softwaredevelopment previously unseen in the 8/16-bit micro-controller market. The MPLAB IDE is a Windows®

based application that contains:

• An interface to debugging tools- simulator- programmer (sold separately)

- emulator (sold separately)- in-circuit debugger (sold separately)

• A full-featured editor with color coded context

• A multiple project manager• Customizable data windows with direct edit of

contents• High-level source code debugging• Mouse over variable inspection

• Extensive on-line help

The MPLAB IDE allows you to:

• Edit your source files (either assembly or C)• One touch assemble (or compile) and download

to PICmicro emulator and simulator tools (automatically updates all project information)

• Debug using:- source files (assembly or C)- mixed assembly and C

- machine code

MPLAB IDE supports multiple debugging tools in asingle development paradigm, from the cost effectivesimulators, through low-cost in-circuit debuggers, tofull-featured emulators. This eliminates the learningcurve when upgrading to tools with increasing flexibilityand power.

26.2 MPASM Assembler

The MPASM assembler is a full-featured, universalmacro assembler for all PICmicro MCUs.

The MPASM assembler generates relocatable objectfiles for the MPLINK object linker, Intel® standard HEXfiles, MAP files to detail memory usage and symbol ref-erence, absolute LST files that contain source lines andgenerated machine code and COFF files fordebugging.

The MPASM assembler features include:

• Integration into MPLAB IDE projects• User defined macros to streamline assembly code

• Conditional assembly for multi-purpose source files

• Directives that allow complete control over the assembly process


PIC18F6585/8585/6680/8680

26.3 MPLAB C17 and MPLAB C18 C Compilers

The MPLAB C17 and MPLAB C18 Code DevelopmentSystems are complete ANSI C compilers forMicrochip’s PIC17CXXX and PIC18CXXX family ofmicrocontrollers. These compilers provide powerfulintegration capabilities, superior code optimization andease of use not found with other compilers.

For easy source level debugging, the compilers providesymbol information that is optimized to the MPLAB IDEdebugger.

26.4 MPLINK Object Linker/MPLIB Object Librarian

The MPLINK object linker combines relocatableobjects created by the MPASM assembler and theMPLAB C17 and MPLAB C18 C compilers. It can linkrelocatable objects from precompiled libraries, usingdirectives from a linker script.

The MPLIB object librarian manages the creation andmodification of library files of precompiled code. Whena routine from a library is called from a source file, onlythe modules that contain that routine will be linked inwith the application. This allows large libraries to beused efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many smaller files

• Enhanced code maintainability by grouping related modules together

• Flexible creation of libraries with easy module listing, replacement, deletion and extraction

26.5 MPLAB C30 C Compiler

The MPLAB C30 C compiler is a full-featured, ANSIcompliant, optimizing compiler that translates standardANSI C programs into dsPIC30F assembly languagesource. The compiler also supports many commandline options and language extensions to take fulladvantage of the dsPIC30F device hardware capabili-ties and afford fine control of the compiler codegenerator.

MPLAB C30 is distributed with a complete ANSI Cstandard library. All library functions have been vali-dated and conform to the ANSI C library standard. Thelibrary includes functions for string manipulation,dynamic memory allocation, data conversion, time-keeping and math functions (trigonometric, exponentialand hyperbolic). The compiler provides symbolicinformation for high-level source debugging with theMPLAB IDE.

26.6 MPLAB ASM30 Assembler, Linker and Librarian

MPLAB ASM30 assembler produces relocatablemachine code from symbolic assembly language fordsPIC30F devices. MPLAB C30 compiler uses theassembler to produce it’s object file. The assemblergenerates relocatable object files that can then bearchived or linked with other relocatable object files andarchives to create an executable file. Notable featuresof the assembler include:

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data• Command line interface• Rich directive set

• Flexible macro language• MPLAB IDE compatibility

26.7 MPLAB SIM Software Simulator

The MPLAB SIM software simulator allows code devel-opment in a PC hosted environment by simulating thePICmicro series microcontrollers on an instructionlevel. On any given instruction, the data areas can beexamined or modified and stimuli can be applied froma file, or user defined key press, to any pin. The execu-tion can be performed in Single-Step, Execute UntilBreak or Trace mode.

The MPLAB SIM simulator fully supports symbolicdebugging using the MPLAB C17 and MPLAB C18C Compilers, as well as the MPASM assembler. Thesoftware simulator offers the flexibility to develop anddebug code outside of the laboratory environment,making it an excellent, economical softwaredevelopment tool.

26.8 MPLAB SIM30 Software Simulator

The MPLAB SIM30 software simulator allows codedevelopment in a PC hosted environment by simulatingthe dsPIC30F series microcontrollers on an instructionlevel. On any given instruction, the data areas can beexamined or modified and stimuli can be applied froma file, or user defined key press, to any of the pins.

The MPLAB SIM30 simulator fully supports symbolicdebugging using the MPLAB C30 C Compiler andMPLAB ASM30 assembler. The simulator runs in eithera Command Line mode for automated tasks, or fromMPLAB IDE. This high-speed simulator is designed todebug, analyze and optimize time intensive DSProutines.


PIC18F6585/8585/6680/8680

26.9 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator

The MPLAB ICE 2000 universal in-circuit emulator isintended to provide the product development engineerwith a complete microcontroller design tool set forPICmicro microcontrollers. Software control of theMPLAB ICE 2000 in-circuit emulator is advanced bythe MPLAB Integrated Development Environment,which allows editing, building, downloading and sourcedebugging from a single environment.

The MPLAB ICE 2000 is a full-featured emulator sys-tem with enhanced trace, trigger and data monitoringfeatures. Interchangeable processor modules allow thesystem to be easily reconfigured for emulation of differ-ent processors. The universal architecture of theMPLAB ICE in-circuit emulator allows expansion tosupport new PICmicro microcontrollers.

The MPLAB ICE 2000 in-circuit emulator system hasbeen designed as a real-time emulation system withadvanced features that are typically found on moreexpensive development tools. The PC platform andMicrosoft® Windows 32-bit operating system werechosen to best make these features available in asimple, unified application.

26.10 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator

The MPLAB ICE 4000 universal in-circuit emulator isintended to provide the product development engineerwith a complete microcontroller design tool set for high-end PICmicro microcontrollers. Software control of theMPLAB ICE in-circuit emulator is provided by theMPLAB Integrated Development Environment, whichallows editing, building, downloading and sourcedebugging from a single environment.

The MPLAB ICD 4000 is a premium emulator system,providing the features of MPLAB ICE 2000, but withincreased emulation memory and high-speed perfor-mance for dsPIC30F and PIC18XXXX devices. Itsadvanced emulator features include complex triggeringand timing, up to 2 Mb of emulation memory and theability to view variables in real-time.

The MPLAB ICE 4000 in-circuit emulator system hasbeen designed as a real-time emulation system withadvanced features that are typically found on moreexpensive development tools. The PC platform andMicrosoft Windows 32-bit operating system werechosen to best make these features available in asimple, unified application.

26.11 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is apowerful, low-cost, run-time development tool,connecting to the host PC via an RS-232 or high-speedUSB interface. This tool is based on the FlashPICmicro MCUs and can be used to develop for theseand other PICmicro microcontrollers. The MPLABICD 2 utilizes the in-circuit debugging capability builtinto the Flash devices. This feature, along withMicrochip’s In-Circuit Serial ProgrammingTM (ICSPTM)protocol, offers cost effective in-circuit Flash debuggingfrom the graphical user interface of the MPLABIntegrated Development Environment. This enables adesigner to develop and debug source code by settingbreakpoints, single-stepping and watching variables,CPU status and peripheral registers. Running at fullspeed enables testing hardware and applications inreal-time. MPLAB ICD 2 also serves as a developmentprogrammer for selected PICmicro devices.

26.12 PRO MATE II Universal Device Programmer

The PRO MATE II is a universal, CE compliant deviceprogrammer with programmable voltage verification atVDDMIN and VDDMAX for maximum reliability. It featuresan LCD display for instructions and error messagesand a modular detachable socket assembly to supportvarious package types. In Stand-Alone mode, thePRO MATE II device programmer can read, verify andprogram PICmicro devices without a PC connection. Itcan also set code protection in this mode.

26.13 MPLAB PM3 Device Programmer

The MPLAB PM3 is a universal, CE compliant deviceprogrammer with programmable voltage verification atVDDMIN and VDDMAX for maximum reliability. It featuresa large LCD display (128 x 64) for menus and errormessages and a modular detachable socket assemblyto support various package types. The ICSP™ cableassembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 device programmer canread, verify and program PICmicro devices without aPC connection. It can also set code protection in thismode. MPLAB PM3 connects to the host PC via anRS-232 or USB cable. MPLAB PM3 has high-speedcommunications and optimized algorithms for quickprogramming of large memory devices and incorpo-rates an SD/MMC card for file storage and secure dataapplications.


PIC18F6585/8585/6680/8680

26.14 PICSTART Plus Development Programmer

The PICSTART Plus development programmer is aneasy-to-use, low-cost, prototype programmer. It con-nects to the PC via a COM (RS-232) port. MPLABIntegrated Development Environment software makesusing the programmer simple and efficient. ThePICSTART Plus development programmer supportsmost PICmicro devices up to 40 pins. Larger pin countdevices, such as the PIC16C92X and PIC17C76X,may be supported with an adapter socket. ThePICSTART Plus development programmer is CEcompliant.

26.15 PICDEM 1 PICmicroDemonstration Board

The PICDEM 1 demonstration board demonstrates thecapabilities of the PIC16C5X (PIC16C54 toPIC16C58A), PIC16C61, PIC16C62X, PIC16C71,PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. Allnecessary hardware and software is included to runbasic demo programs. The sample microcontrollersprovided with the PICDEM 1 demonstration board canbe programmed with a PRO MATE II device program-mer or a PICSTART Plus development programmer.The PICDEM 1 demonstration board can be connectedto the MPLAB ICE in-circuit emulator for testing. Aprototype area extends the circuitry for additional appli-cation components. Features include an RS-232interface, a potentiometer for simulated analog input,push button switches and eight LEDs.

26.16 PICDEM.net Internet/Ethernet Demonstration Board

The PICDEM.net demonstration board is an Internet/Ethernet demonstration board using the PIC18F452microcontroller and TCP/IP firmware. The boardsupports any 40-pin DIP device that conforms to thestandard pinout used by the PIC16F877 orPIC18C452. This kit features a user friendly TCP/IPstack, web server with HTML, a 24L256 SerialEEPROM for Xmodem download to web pages intoSerial EEPROM, ICSP/MPLAB ICD 2 interface con-nector, an Ethernet interface, RS-232 interface and a16 x 2 LCD display. Also included is the book andCD-ROM “TCP/IP Lean, Web Servers for EmbeddedSystems,” by Jeremy Bentham

26.17 PICDEM 2 Plus Demonstration Board

The PICDEM 2 Plus demonstration board supportsmany 18, 28 and 40-pin microcontrollers, includingPIC16F87X and PIC18FXX2 devices. All the neces-sary hardware and software is included to run the dem-onstration programs. The sample microcontrollersprovided with the PICDEM 2 demonstration board canbe programmed with a PRO MATE II device program-mer, PICSTART Plus development programmer, orMPLAB ICD 2 with a Universal Programmer Adapter.The MPLAB ICD 2 and MPLAB ICE in-circuit emulatorsmay also be used with the PICDEM 2 demonstrationboard to test firmware. A prototype area extends thecircuitry for additional application components. Someof the features include an RS-232 interface, a 2 x 16LCD display, a piezo speaker, an on-board temperaturesensor, four LEDs and sample PIC18F452 andPIC16F877 Flash microcontrollers.

26.18 PICDEM 3 PIC16C92X Demonstration Board

The PICDEM 3 demonstration board supports thePIC16C923 and PIC16C924 in the PLCC package. Allthe necessary hardware and software is included to runthe demonstration programs.

26.19 PICDEM 4 8/14/18-Pin Demonstration Board

The PICDEM 4 can be used to demonstrate the capa-bilities of the 8, 14 and 18-pin PIC16XXXX andPIC18XXXX MCUs, including the PIC16F818/819,PIC16F87/88, PIC16F62XA and the PIC18F1320family of microcontrollers. PICDEM 4 is intended toshowcase the many features of these low pin countparts, including LIN and Motor Control using ECCP.Special provisions are made for low-power operationwith the supercapacitor circuit and jumpers allow on-board hardware to be disabled to eliminate currentdraw in this mode. Included on the demo board are pro-visions for Crystal, RC or Canned Oscillator modes, afive volt regulator for use with a nine volt wall adapteror battery, DB-9 RS-232 interface, ICD connector forprogramming via ICSP and development with MPLABICD 2, 2 x 16 liquid crystal display, PCB footprints forH-Bridge motor driver, LIN transceiver and EEPROM.Also included are: header for expansion, eight LEDs,four potentiometers, three push buttons and a proto-typing area. Included with the kit is a PIC16F627A anda PIC18F1320. Tutorial firmware is included along withthe User’s Guide.


PIC18F6585/8585/6680/8680

26.20 PICDEM 17 Demonstration Board

The PICDEM 17 demonstration board is an evaluationboard that demonstrates the capabilities of severalMicrochip microcontrollers, including PIC17C752,PIC17C756A, PIC17C762 and PIC17C766. A pro-grammed sample is included. The PRO MATE II deviceprogrammer, or the PICSTART Plus development pro-grammer, can be used to reprogram the device for usertailored application development. The PICDEM 17demonstration board supports program download andexecution from external on-board Flash memory. Agenerous prototype area is available for user hardwareexpansion.

26.21 PICDEM 18R PIC18C601/801 Demonstration Board

The PICDEM 18R demonstration board serves to assistdevelopment of the PIC18C601/801 family of Microchipmicrocontrollers. It provides hardware implementationof both 8-bit Multiplexed/Demultiplexed and 16-bitMemory modes. The board includes 2 Mb externalFlash memory and 128 Kb SRAM memory, as well asserial EEPROM, allowing access to the wide range ofmemory types supported by the PIC18C601/801.

26.22 PICDEM LIN PIC16C43X Demonstration Board

The powerful LIN hardware and software kit includes aseries of boards and three PICmicro microcontrollers.The small footprint PIC16C432 and PIC16C433 areused as slaves in the LIN communication and featureon-board LIN transceivers. A PIC16F874 Flashmicrocontroller serves as the master. All three micro-controllers are programmed with firmware to provideLIN bus communication.

26.23 PICkitTM 1 Flash Starter Kit

A complete “development system in a box”, the PICkitFlash Starter Kit includes a convenient multi-sectionboard for programming, evaluation and development of8/14-pin Flash PIC® microcontrollers. Powered viaUSB, the board operates under a simple Windows GUI.The PICkit 1 Starter Kit includes the User’s Guide (onCD ROM), PICkit 1 tutorial software and code forvarious applications. Also included are MPLAB® IDE(Integrated Development Environment) software,software and hardware “Tips 'n Tricks for 8-pin FlashPIC® Microcontrollers” Handbook and a USB interfacecable. Supports all current 8/14-pin Flash PICmicrocontrollers, as well as many future planneddevices.

26.24 PICDEM USB PIC16C7X5 Demonstration Board

The PICDEM USB Demonstration Board shows off thecapabilities of the PIC16C745 and PIC16C765 USBmicrocontrollers. This board provides the basis forfuture USB products.

26.25 Evaluation and Programming Tools

In addition to the PICDEM series of circuits, Microchiphas a line of evaluation kits and demonstration softwarefor these products.

• KEELOQ evaluation and programming tools for Microchip’s HCS Secure Data Products

• CAN developers kit for automotive network applications

• Analog design boards and filter design software

• PowerSmart battery charging evaluation/calibration kits

• IrDA® development kit• microID development and rfLabTM development

software• SEEVAL® designer kit for memory evaluation and

endurance calculations• PICDEM MSC demo boards for Switching mode

power supply, high-power IR driver, delta sigma ADC and flow rate sensor

Check the Microchip web page and the latest ProductSelector Guide for the complete list of demonstrationand evaluation kits.


PIC18F6585/8585/6680/8680

NOTES:


PIC18F6585/8585/6680/8680

27.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings (†)

Ambient temperature under bias............................................................................................................ .-55°C to +125°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ......................................... -0.3V to (VDD + 0.3V)

Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V

Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V

Voltage on RA4 with respect to Vss ............................................................................................................... 0V to +8.5V

Total power dissipation (Note 1) ...............................................................................................................................1.0W

Maximum current out of VSS pin ...........................................................................................................................300 mA

Maximum current into VDD pin ..............................................................................................................................250 mA

Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA

Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................25 mA

Maximum current sunk by all ports .......................................................................................................................200 mA

Maximum current sourced by all ports ..................................................................................................................200 mA

Note 1: Power dissipation is calculated as follows: Pdis = VDD x IDD – ∑ IOH + ∑ (VDD – VOH) x IOH + ∑(VOl x IOL)

2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin ratherthan pulling this pin directly to VSS.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

PIC18F6585/8585/6680/8680

FIGURE 27-1: PIC18F6585/8585/6680/8680 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)

FIGURE 27-2: PIC18LF6585/8585/6680/8680 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)

Frequency

Volta

ge

6.0V

5.5V

4.5V

4.0V

2.0V

FMAX

5.0V

3.5V

3.0V

2.5V

PIC18FXX8X

4.2V

FMAX = 40 MHz for PIC18F6X8X and PIC18F8X8X in Microcontroller mode.FMAX = 25 MHz for PIC18F8X8X in modes other than Microcontroller mode.

Frequency

Volta

ge

6.0V

5.5V

4.5V

4.0V

2.0V

FMAX

5.0V

3.5V

3.0V

2.5V

PIC18LFXX8X

FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN ≤ 4.2V;

Note: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.

4 MHz

4.2V

FMAX = 40 MHz, if VDDAPPMIN > 4.2V.

For PIC18F6X8X and PIC18F8X8X in Microcontroller mode:

FMAX = (9.55 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN ≤ 4.2V;FMAX = 25 MHz, if VDDAPPMIN > 4.2V.

For PIC18F8X8X in modes other than Microcontroller mode:


PIC18F6585/8585/6680/8680

FIGURE 27-3: PIC18F6585/8585/6680/8680 VOLTAGE-FREQUENCY GRAPH (EXTENDED)

Frequency

Vo

ltag

e

6.0V

5.5V

4.5V

4.0V

2.0V

25 MHz

5.0V

3.5V

3.0V

2.5V

PIC18FXX8X

4.2V


PIC18F6585/8585/6680/8680

27.1 DC Characteristics: Supply VoltagePIC18FXX8X (Industrial, Extended) PIC18LFXX8X (Industrial)

PIC18LFXX8X (Industrial)

Standard Operating Conditions (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for industrial

PIC18FXX8X (Industrial, Extended)


-40°C ≤ TA ≤ +125°C for extended

Param. No.

Symbol Characteristic Min Typ Max Units Conditions

D001 VDD Supply Voltage

PIC18LFXX8X 2.0 — 5.5 V HS, XT, RC and LP Oscillator mode

PIC18FXX8X 4.2 — 5.5 V

D001A AVDD Analog Supply Voltage

VDD – 0.3 — VDD + 0.3 V

D002 VDR RAM Data RetentionVoltage(1)

1.5 — — V

D003 VPOR VDD Start Voltage to ensure internal Power-on Reset signal

— — 0.7 V See section on Power-on Reset for details

D004 SVDD VDD Rise Rateto ensure internal Power-on Reset signal

0.05 — — V/ms See section on Power-on Reset for details

D005 VBOR Brown-out Reset Voltage

BORV1:BORV0 = 11 1.96 — 2.18 V

BORV1:BORV0 = 10 2.64 — 2.92 V

BORV1:BORV0 = 01 4.11 — 4.55 V

BORV1:BORV0 = 00 4.41 — 4.87 V

Legend: Shading of rows is to assist in readability of the table.Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM

data.


PIC18F6585/8585/6680/8680

27.2 DC Characteristics: Power-down and Supply CurrentPIC18FXX8X (Industrial, Extended) PIC18LFXX8X (Industrial)






Param. No.

Device Typ Max Units Conditions

Power-down Current (IPD)(1)

D020 PIC18LFXX8X 0.2 1 µA -40°CVDD = 2.0V,

(Sleep mode)0.2 1 µA +25°C

5.0 10 µA +85°C

D020A PIC18LFXX8X 0.4 1 µA -40°CVDD = 3.0V,


3.0 18 µA +85°C

D020B All devices 0.7 2 µA -40°CVDD = 5.0V,


15.0 32 µA +85°C

Legend: Shading of rows is to assist in readability of the table.Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is

measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption.The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;MCLR = VDD; WDT enabled/disabled as specified.

3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.


PIC18F6585/8585/6680/8680

Supply Current (IDD)(2,3)

D010 PIC18LFXX8X 500 500 µA -40°C

FOSC = 1 MHZ,EC oscillator

300 500 µA +25°C VDD = 2.0V

850 1000 µA +85°C

PIC18LFXX8X 500 900 µA -40°C

500 900 µA +25°C VDD = 3.0V

1 1.5 mA +85°C

All devices 1 2 mA -40°C

1 2 mA +25°C VDD = 5.0V

1.3 3 mA +85°C

PIC18LFXX8X 1 2 mA -40°C

FOSC = 4 MHz,EC oscillator

1 2 mA +25°C VDD = 2.0V

1.5 2.5 mA +85°C

PIC18LFXX8X 1.5 2 mA -40°C

1.5 2 mA +25°C VDD = 3.0V

2 2.5 mA +85°C

All devices 3 5 mA -40°C

3 5 mA +25°C VDD = 5.0V

4 6 mA +85°C

27.2 DC Characteristics: Power-down and Supply CurrentPIC18FXX8X (Industrial, Extended) PIC18LFXX8X (Industrial) (Continued)






Param. No.








PIC18F6585/8585/6680/8680

Supply Current (IDD)(2,3)

PIC18FXX8X 13 27 mA -40°C


15 27 mA +25°C VDD = 4.2V

19 29 mA +85°C


21 31 mA +25°C VDD = 5.0V

23 34 mA +85°C



24 34 mA +25°C VDD = 4.2V

29 44 mA +85°C


33 46 mA +25°C VDD = 5.0V

40 51 mA +85°C

D014 PIC18LFXX8X 27 45 µA -10°C

FOSC = 32 kHz, Timer1 as clock

30 50 µA +25°C VDD = 2.0V

32 54 µA +70°C

PIC18LFXX8X 33 55 µA -10°C

36 60 µA +25°C VDD = 3.0V

39 65 µA +70°C

All devices 75 125 µA -10°C

90 150 µA +25°C VDD = 5.0V

113 188 µA +70°C







Param. No.








PIC18F6585/8585/6680/8680

Module Differential Currents (∆IWDT, ∆IBOR, ∆ILVD, ∆IOSCB, ∆IAD)

D022(∆IWDT)

Watchdog Timer <1 1.5 µA -40°CVDD = 2.0V<1 2 µA +25°C

5 20 µA +85°C3 10 µA -40°C

VDD = 3.0V3 20 µA +25°C10 35 µA +85°C12 25 µA -40°C

VDD = 5.0V15 35 µA +25°C20 50 µA +85°C

D022A(∆IBOR)

Brown-out Reset 55 115 µA -40°C to +85°C VDD = 3.0V

105 175 µA -40°C to +85°C VDD = 5.0V

D022B(∆ILVD)

Low-Voltage Detect 45 125 µA -40°C to +85°C VDD = 2.0V

45 150 µA -40°C to +85°C VDD = 3.0V

45 225 µA -40°C to +85°C VDD = 5.0V

D025(∆IOSCB)

Timer1 Oscillator 20 27 µA -10°C20 30 µA +25°C VDD = 2.0V 32 kHz on Timer1

25 35 µA +70°C22 60 µA -10°C22 65 µA +25°C VDD = 3.0V 32 kHz on Timer1

25 75 µA +70°C30 75 µA -10°C30 85 µA +25°C VDD = 5.0V 32 kHz on Timer1

35 100 µA +70°CD026(∆IAD)

A/D Converter <1 2 µA +25°C VDD = 2.0V

<1 2 µA +25°C VDD = 3.0V A/D on, not converting

<1 2 µA +25°C VDD = 5.0V







Param. No.

PIC18F6585/8585/6680/8680

27.3 DC Characteristics: PIC18FXX8X (Industrial, Extended) PIC18LFXX8X (Industrial)

DC CHARACTERISTICSStandard Operating Conditions (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for industrial


ParamNo.

Symbol Characteristic Min Max Units Conditions

VIL Input Low Voltage

I/O ports:

D030 with TTL buffer VSS 0.15 VDD V VDD < 4.5V

D030A — 0.8 V 4.5V ≤ VDD ≤ 5.5V

D031 with Schmitt Trigger bufferRC3 and RC4

VSS

VSS

0.2 VDD

0.3 VDD

VV

D032 MCLR VSS 0.2 VDD V

D032A OSC1 (in XT, HS and LP modes) and T1OSI

VSS 0.3 VDD V

D033 OSC1 (in RC and EC mode)(1) VSS 0.2 VDD V

VIH Input High Voltage

I/O ports:

D040 with TTL buffer 0.25 VDD + 0.8V

VDD V VDD < 4.5V

D040A 2.0 VDD V 4.5V ≤ VDD ≤ 5.5V

D041 with Schmitt Trigger bufferRC3 and RC4

0.8 VDD

0.7 VDD

VDD

VDD

VV

D042 MCLR, OSC1 (EC mode) 0.8 VDD VDD V

D042A OSC1 (in XT, HS and LP modes) and T1OSI

0.7 VDD VDD V

D043 OSC1 (RC mode)(1) 0.9 VDD VDD V

IIL Input Leakage Current(2,3)

D060 I/O ports — ±1 µA VSS ≤ VPIN ≤ VDD, Pin at high-impedance

D061 MCLR — ±5 µA Vss ≤ VPIN ≤ VDD

D063 OSC1 — ±5 µA Vss ≤ VPIN ≤ VDD

IPU Weak Pull-up Current

D070 IPURB PORTB weak pull-up current 50 400 µA VDD = 5V, VPIN = VSS

Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PICmicro device be driven with an external clock while in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is defined as current sourced by the pin.4: Parameter is characterized but not tested.

PIC18F6585/8585/6680/8680

VOL Output Low Voltage

D080 I/O ports — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C

D080A — 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40°C to +125°C

D083 OSC2/CLKO (RC mode)

— 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40°C to +85°C

D083A — 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40°C to +125°C

VOH Output High Voltage(3)

D090 I/O ports VDD – 0.7 — V IOH = -3.0 mA, VDD = 4.5V, -40°C to +85°C

D090A VDD – 0.7 — V IOH = -2.5 mA, VDD = 4.5V, -40°C to +125°C

D092 OSC2/CLKO (RC mode)

VDD – 0.7 — V IOH = -1.3 mA, VDD = 4.5V, -40°C to +85°C

D092A VDD – 0.7 — V IOH = -1.0 mA, VDD = 4.5V, -40°C to +125°C

D150 VOD Open-Drain High Voltage — 8.5 V RA4 pin

Capacitive Loading Specson Output Pins

D100(4) COSC2 OSC2 pin — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1

D101 CIO All I/O pins and OSC2 (in RC mode)

— 50 pF To meet the AC Timing Specifications

D102 CB SCL, SDA — 400 pF In I2C mode

27.3 DC Characteristics: PIC18FXX8X (Industrial, Extended) PIC18LFXX8X (Industrial) (Continued)

DC CHARACTERISTICSStandard Operating Conditions (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for industrial


ParamNo.


Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PICmicro device be driven with an external clock while in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is defined as current sourced by the pin.4: Parameter is characterized but not tested.


PIC18F6585/8585/6680/8680

TABLE 27-1: COMPARATOR SPECIFICATIONS

TABLE 27-2: VOLTAGE REFERENCE SPECIFICATIONS

Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +125°C, unless otherwise stated

ParamNo.

Sym Characteristics Min Typ Max Units Comments

D300 VIOFF Input Offset Voltage — ± 5.0 ± 10 mV

D301 VICM Input Common Mode Voltage 0 — VDD – 1.5 V

D302 CMRR Common Mode Rejection Ratio 55 — — dB

300300A

TRESP Response Time(1) — 150 400600

nsns

PIC18FXX8XPIC18LFXX8X

301 TMC2OV Comparator Mode Change to Output Valid

— — 10 µs

Note 1: Response time measured with one comparator input at (VDD – 1.5)/2 while the other input transitions from VSS to VDD.

Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +125°C, unless otherwise stated

ParamNo.

Sym Characteristics Min Typ Max Units Comments

D310 VRES Resolution VDD/24 — VDD/32 LSb

D311 VRAA Absolute Accuracy ——

——

1/41/2

LSbLSb

Low Range (VRR = 1)High Range (VRR = 0)

D312 VRUR Unit Resistor Value (R) — 2k — Ω310 TSET Settling Time(1) — — 10 µs

Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.

PIC18F6585/8585/6680/8680

FIGURE 27-4: LOW-VOLTAGE DETECT CHARACTERISTICS

TABLE 27-3: LOW-VOLTAGE DETECT CHARACTERISTICS

VLVD

LVDIF

VDD

(LVDIF set by hardware)

(LVDIF can be cleared in software)



Param No.

Symbol Characteristic Min Typ† Max Units Conditions

D420 LVD Voltage on VDD transition high to low

LVV = 0000 — — — V

LVV = 0001 1.96 2.06 2.16 V

LVV = 0010 2.16 2.27 2.38 V

LVV = 0011 2.35 2.47 2.59 V

LVV = 0100 2.46 2.58 2.71 V

LVV = 0101 2.64 2.78 2.92 V

LVV = 0110 2.75 2.89 3.03 V

LVV = 0111 2.95 3.1 3.26 V

LVV = 1000 3.24 3.41 3.58 V

LVV = 1001 3.43 3.61 3.79 V

LVV = 1010 3.53 3.72 3.91 V

LVV = 1011 3.72 3.92 4.12 V

LVV = 1100 3.92 4.13 4.33 V

LVV = 1101 4.11 4.33 4.55 V

LVV = 1110 4.41 4.64 4.87 V

D423 VBG Band Gap Reference Voltage Value

— 1.22 — V

† Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization.


PIC18F6585/8585/6680/8680

TABLE 27-4: MEMORY PROGRAMMING REQUIREMENTS

DC CharacteristicsStandard Operating Conditions (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for industrial


ParamNo.

Sym Characteristic Min Typ† Max Units Conditions

Internal Program Memory Programming Specifications(Note 1)

D110 VPP Voltage on MCLR/VPP pin 9.00 — 13.25 V (Note 2)

D112 IPP Current into MCLR/VPP pin — — 5 µA

D113 IDDP Supply Current during Programming

— — 10 mA

Data EEPROM Memory

D120 ED Cell Endurance 100K 1M — E/W -40°C to +85°CD120A ED Cell Endurance 10K 100K — E/W +85°C to +125°CD121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON to read/write,

VMIN = Minimum operating voltage

D122 TDEW Erase/Write Cycle Time — 4 — ms

D123 TRETD Characteristic Retention 40 — — Year -40°C to +85°C (Note 3)

D123A TRETD Characteristic Retention 100 — — Year 25°C (Note 3)

Program Flash Memory

D130 EP Cell Endurance 10K 100K — E/W -40°C to +85°CD130A EP Cell Endurance 1000 10K — E/W +85°C to +125°CD131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating

voltage

D132 VIE VDD for Block Erase 4.5 — 5.5 V Using ICSP port

D132A VIW VDD for Externally Timed Erase or Write

4.5 — 5.5 V Using ICSP port

D132B VPEW VDD for Self-timed Write VMIN — 5.5 V VMIN = Minimum operating voltage

D133 TIE ICSP Block Erase Cycle Time — 5 — ms VDD > 4.5V

D133A TIW ICSP Erase or Write Cycle Time (externally timed)

1 — — ms VDD > 4.5V

D133A TIW Self-timed Write Cycle Time — 2.5 — ms

D134 TRETD Characteristic Retention 40 — — Year -40°C to +85°C (Note 3)

D134A TRETD Characteristic Retention 100 — — Year 25°C (Note 3)

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note 1: These specifications are for programming the on-chip program memory through the use of table write instructions.

2: The pin may be kept in this range at times other than programming but it is not recommended.3: Retention time is valid provided no other specifications are violated.


PIC18F6585/8585/6680/8680

27.4 AC (Timing) Characteristics

27.4.1 TIMING PARAMETER SYMBOLOGY

The timing parameter symbols have been createdfollowing one of the following formats:

1. TppS2ppS 3. TCC:ST (I2C specifications only)2. TppS 4. Ts (I2C specifications only)T

F Frequency T TimeLowercase letters (pp) and their meanings:pp

cc CCP1 osc OSC1ck CLKO rd RDcs CS rw RD or WR

di SDI sc SCKdo SDO ss SSdt Data in t0 T0CKI

io I/O port t1 T1CKImc MCLR wr WR

Uppercase letters and their meanings:

SF Fall P PeriodH High R Rise

I Invalid (high-impedance) V ValidL Low Z High-impedance

I2C only

AA output access High HighBUF Bus free Low Low

TCC:ST (I2C specifications only)

CCHD Hold SU Setup

ST

DAT DATA input hold STO Stop conditionSTA Start condition


PIC18F6585/8585/6680/8680

27.4.2 TIMING CONDITIONS

The temperature and voltages specified in Table 27-5apply to all timing specifications unless otherwisenoted. Figure 27-5 specifies the load conditions for thetiming specifications.

TABLE 27-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC

FIGURE 27-5: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

AC CHARACTERISTICS


-40°C ≤ TA ≤ +125°C for extendedOperating voltage VDD range as described in DC spec Section 27.1 and Section 27.3. LC parts operate for industrial temperatures only.

VDD/2

CL

RL

Pin

Pin

VSS

VSS

CL

RL = 464Ω

CL = 50 pF for all pins except OSC2/CLKOand including D and E outputs as ports

Load condition 1 Load condition 2


PIC18F6585/8585/6680/8680

27.4.3 TIMING DIAGRAMS AND SPECIFICATIONS

FIGURE 27-6: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)

TABLE 27-6: EXTERNAL CLOCK TIMING REQUIREMENTS

Param. No. Symbol Characteristic Min Max Units Conditions

1A FOSC External CLKI Frequency(1) DC 40 MHz EC, ECIO, -40°C to +85°CDC 25 MHz EC,ECIO, -40°C to +85°C, EMA

Oscillator Frequency(1) DC 25 MHz EC, ECIO, +85°C to +125°CDC 16 MHz EC, ECIO, +85°C to +125°C, EMADC 4 MHz RC oscillator0.1 4 MHz XT oscillator4 25 MHz HS oscillator, -40°C to +85°C4 25 MHz HS oscillator, -40°C to +85°C, EMA4 25 MHz HS oscillator, +85°C to +125°C4 16 MHz HS oscillator, +85°C to +125°C, EMA4 10 MHz HS + PLL oscillator, -40°C to +85°C4 6.25 MHz HS + PLL oscillator, +85°C to +125°C

DC 200 kHz LP oscillator1 TOSC External CLKI Period(1) 25 — ns EC, ECIO, -40°C to +85°C

Oscillator Period(1) 40 — ns EC,ECIO, -40°C to +85°C, EMA40 — ns EC, ECIO, +85°C to +125°C

62.5 — ns EC, ECIO, +85°C to +125°C, EMA250 — ns RC oscillator250 10,000 ns XT oscillator40 — ns HS oscillator, -40°C to +85°C40 — ns HS oscillator, -40°C to +85°C, EMA40 — ns HS oscillator, +85°C to +125°C

62.5 — ns HS oscillator, +85°C to +125°C, EMA100 250 ns HS + PLL oscillator, -40°C to +85°C160 250 ns HS + PLL oscillator, +85°C to +125°C

5 200 µs LP oscillator2 TCY Instruction Cycle Time(1) 100

160——

nsns

TCY = 4/FOSC, -40°C to +85°C TCY = 4/FOSC, +85°C to +125°C

3 TOSL,TOSH

External Clock in (OSC1) High or Low Time

302.510

———

nsµsns

XT oscillatorLP oscillatorHS oscillator

4 TOSR,TOSF

External Clock in (OSC1) Rise or Fall Time

— ——

20507.5

nsnsns

XT oscillatorLP oscillatorHS oscillator

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.

OSC1

CLKO

Q4 Q1 Q2 Q3 Q4 Q1

1

2

3 3 4 4


PIC18F6585/8585/6680/8680

TABLE 27-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2 TO 5.5V)

FIGURE 27-7: CLKO AND I/O TIMING

Param. No.

Sym Characteristic Min Typ† Max Units Conditions

— FOSC Oscillator Frequency Range 4 — 10 MHz HS mode

— FSYS On-Chip VCO System Frequency 16 — 40 MHz HS mode

— trc PLL Start-up Time (Lock Time) — — 2 ms

— ∆CLK CLKO Stability (Jitter) -2 — +2 %

† Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested.

Note: Refer to Figure 27-5 for load conditions.

OSC1

CLKO

I/O Pin(Input)

I/O Pin(Output)

Q4 Q1 Q2 Q3

10

1314

17

20, 21

19 18

15

11

12

16

Old Value New Value


PIC18F6585/8585/6680/8680

TABLE 27-8: CLKO AND I/O TIMING REQUIREMENTS

FIGURE 27-8: PROGRAM MEMORY READ TIMING DIAGRAM

Param. No.


10 TOSH2CKL OSC1 ↑ to CLKO ↓ — 75 200 ns (1)

11 TOSH2CKH OSC1 ↑ to CLKO ↑ — 75 200 ns (1)

12 TCKR CLKO Rise Time — 35 100 ns (1)

13 TCKF CLKO Fall Time — 35 100 ns (1)

14 TCKL2IOV CLKO ↓ to Port Out Valid — — 0.5 TCY + 20 ns (1)

15 TIOV2CKH Port In Valid before CLKO ↑ 0.25 TCY + 25 — — ns (1)

16 TCKH2IOI Port In Hold after CLKO ↑ 0 — — ns (1)

17 TOSH2IOV OSC1 ↑ (Q1 cycle) to Port Out Valid — 50 150 ns

18 TOSH2IOI OSC1 ↑ (Q2 cycle) to Port Input Invalid (I/O in hold time)

PIC18FXX8X 100 — — ns

18A PIC18LFXX8X 200 — — ns

19 TIOV2OSH Port Input Valid to OSC1 ↑ (I/O in setup time) 0 — — ns

20 TIOR Port Output Rise Time PIC18FXX8X — 10 25 ns

20A PIC18LFXX8X — — 60 ns

21 TIOF Port Output Fall Time PIC18FXX8X — 10 25 ns

21A PIC18LFXX8X — — 60 ns

22† TINP INT pin High or Low Time TCY — — ns

23† TRBP RB7:RB4 Change INT High or Low Time TCY — — ns

24† TRCP RC7:RC4 Change INT High or Low Time 20 ns

† These parameters are asynchronous events not related to any internal clock edges.Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.

Q1 Q2 Q3 Q4 Q1 Q2

OSC1

ALE

OE

Address Data from External

166

160

165

161151 162

163

AD<15:0>

167168

155

Address

Address

150

A<19:16> Address

169

BA0

CE171

171A

164

PIC18F6585/8585/6680/8680

TABLE 27-9: PROGRAM MEMORY READ TIMING REQUIREMENTS (VDD = 4.2 TO 5.5V)

FIGURE 27-9: PROGRAM MEMORY WRITE TIMING DIAGRAM

Param. No

Symbol Characteristics Min Typ Max Units

150 TADV2ALL Address Out Valid to ALE ↓ (address setup time)

0.25 TCY – 10 — — ns

151 TALL2ADL ALE ↓ to Address Out Invalid (address hold time)

5 — — ns

155 TALL2OEL ALE ↓ to OE ↓ 10 0.125 TCY — ns

160 TADZ2OEL AD High-Z to OE ↓ (bus release to OE) 0 — — ns

161 TOEH2ADD OE ↑ to AD Driven 0.125 TCY – 5 — — ns

162 TADV2OEH LS Data Valid before OE ↑ (data setup time) 20 — — ns

163 TOEH2ADL OE ↑ to Data In Invalid (data hold time) 0 — — ns

164 TALH2ALL ALE Pulse Width — 0.25 TCY — ns

165 TOEL2OEH OE Pulse Width 0.5 TCY – 5 0.5 TCY — ns

166 TALH2ALH ALE ↑ to ALE ↑ (cycle time) — 1 TCY — ns

167 TACC Address Valid to Data Valid 0.75 TCY – 25 — — ns

168 TOE OE ↓ to Data Valid — 0.5 TCY – 25 ns

169 TALL2OEH ALE ↓ to OE ↑ 0.625 TCY – 10 — 0.625 TCY + 10 ns

171 TALH2CSL Chip Select Active to ALE ↓ — — 10 ns

171A TUBL2OEH AD Valid to Chip Select Active 0.25 TCY – 20 — — ns

Q1 Q2 Q3 Q4 Q1 Q2

OSC1

ALE

Address Data

156150

151

153

AD<15:0> Address

WRH orWRL

UB orLB

157

154

157A

AddressA<19:16> AddressBA0

166

CE

171

171A

PIC18F6585/8585/6680/8680

TABLE 27-10: PROGRAM MEMORY WRITE TIMING REQUIREMENTS (VDD = 4.2 TO 5.5V)

FIGURE 27-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING

Param. No.

Symbol Characteristics Min Typ Max Units

150 TADV2ALL Address Out Valid to ALE ↓ (address setup time) 0.25 TCY – 10 — — ns

151 TALL2ADL ALE ↓ to Address Out Invalid (address hold time) 5 — — ns

153 TWRH2ADL WRn ↑ to Data Out Invalid (data hold time) 5 — — ns

154 TWRL WRn Pulse Width 0.5 TCY – 5 0.5 TCY — ns

156 TADV2WRH Data Valid before WRn ↑ (data setup time) 0.5 TCY – 10 — — ns

157 TBSV2WRL Byte Select Valid before WRn ↓ (byte select setup time) 0.25 TCY — — ns

157A TWRH2BSI WRn ↑ to Byte Select Invalid (byte select hold time) 0.125 TCY – 5 — — ns

166 TALH2ALH ALE ↑ to ALE ↑ (cycle time) — 0.25 TCY — ns

171 TALH2CSL Chip Enable Active to ALE ↓ — — 10 ns

171A TUBL2OEH AD Valid to Chip Enable Active 0.25 TCY – 20 — — ns

VDD

MCLR

InternalPOR

PWRTTime-out

OSCTime-out

InternalReset

WatchdogTimerReset

33

32

30

3134

I/O pins

34



PIC18F6585/8585/6680/8680

FIGURE 27-11: BROWN-OUT RESET TIMING

TABLE 27-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS

FIGURE 27-12: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

VDDBVDD

35VBGAP = 1.2V

VIRVST

Enable Internal

Internal Reference 36

Reference Voltage

Voltage Stable

Param. No.


30 TMCL MCLR Pulse Width (low) 2 — — µs

31 TWDT Watchdog Timer Time-out Period (No Postscaler)

7 18 33 ms

32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period

33 TPWRT Power up Timer Period 28 72 132 ms

34 TIOZ I/O High-Impedance from MCLR Low or Watchdog Timer Reset

— 2 — µs

35 TBOR Brown-out Reset Pulse Width 200 — — µs VDD ≤ BVDD (see )

36 TIVRST Time for Internal Reference Voltage to become stable

— 20 50 µs

37 TLVD Low-Voltage Detect Pulse Width 200 — — µs VDD ≤ VLVD


46

47

45

48

41

42

40

T0CKI

T1OSO/T1CKI

TMR0 orTMR1


PIC18F6585/8585/6680/8680

TABLE 27-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param. No.


40 TT0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns

With prescaler 10 — ns

41 TT0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns

With prescaler 10 — ns

42 TT0P T0CKI Period No prescaler TCY + 10 — ns

With prescaler Greater of:20 nS or TCY + 40

N

— ns N = prescalevalue (1, 2, 4,..., 256)

45 TT1H T1CKI High Time

Synchronous, no prescaler 0.5 TCY + 20 — ns

Synchronous,with prescaler

PIC18FXX8X 10 — ns

PIC18LFXX8X 25 — ns

Asynchronous PIC18FXX8X 30 — ns


46 TT1L T1CKI Low Time

Synchronous, no prescaler 0.5 TCY + 5 — ns

Synchronous, with prescaler



Asynchronous PIC18FXX8X 30 — ns

PIC18LFXX8X TBD TBD ns

47 TT1P T1CKI Input Period

Synchronous Greater of:20 nS or TCY + 40

N

— ns N = prescalevalue (1, 2, 4, 8)

Asynchronous 60 — ns

FT1 T1CKI Oscillator Input Frequency Range DC 50 kHz

48 TCKE2TMRI Delay from External T1CKI Clock Edge to Timer Increment

2 TOSC 7 TOSC —


PIC18F6585/8585/6680/8680

FIGURE 27-13: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES)

TABLE 27-13: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES)


CCPx(Capture Mode)

50 51

52

CCPx

53 54

(Compare or PWM Mode)

Param. No.


50 TCCL CCPx Input Low Time

No prescaler 0.5 TCY + 20 — ns

With prescaler



51 TCCH CCPx Input High Time

No prescaler 0.5 TCY + 20 — ns

Withprescaler



52 TCCP CCPx Input Period 3 TCY + 40N

— ns N = prescale value (1,4 or 16)

53 TCCR CCPx Output Rise Time PIC18FXX8X — 25 ns

PIC18LFXX8X — 45 ns

54 TCCF CCPx Output Fall Time PIC18FXX8X — 25 ns



PIC18F6585/8585/6680/8680

FIGURE 27-14: PARALLEL SLAVE PORT TIMING (PIC18FXX8X)

TABLE 27-14: PARALLEL SLAVE PORT REQUIREMENTS (PIC18FXX8X)


RE2/CS

RE0/RD

RE1/WR

RD7:RD0

62

63

64

65

Param. No.


62 TDTV2WRH Data In Valid before WR ↑ or CS ↑ (setup time)

2025

——

nsns Extended Temp. range

63 TWRH2DTI WR ↑ or CS ↑ to Data–In Invalid (hold time)



64 TRDL2DTV RD ↓ and CS ↓ to Data–Out Valid ——

8090

nsns Extended Temp. range

65 TRDH2DTI RD ↑ or CS ↓ to Data–Out Invalid 10 30 ns

66 TIBFINH Inhibit of the IBF flag bit being cleared from WR ↑ or CS ↑

— 3 TCY


PIC18F6585/8585/6680/8680

FIGURE 27-15: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)

TABLE 27-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)

SS

SCK(CKP = 0)

SCK(CKP = 1)

SDO

SDI

70

71 72

7374

75, 76

787980

7978

MSb LSbbit 6 - - - - - -1

MSb In LSb Inbit 6 - - - -1


Param. No.


70 TSSL2SCH, TSSL2SCL

SS ↓ to SCK ↓ or SCK ↑ Input TCY — ns

71 TSCH SCK Input High Time (Slave mode)

Continuous 1.25 TCY + 30 — ns

71A Single Byte 40 — ns (Note 1)

72 TSCL SCK Input Low Time (Slave mode)



73 TDIV2SCH, TDIV2SCL

Setup Time of SDI Data Input to SCK Edge 100 — ns

73A TB2B Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2

1.5 TCY + 40 — ns (Note 2)

74 TSCH2DIL, TSCL2DIL

Hold Time of SDI Data Input to SCK Edge 100 — ns

75 TDOR SDO Data Output Rise Time PIC18FXX8X — 25 ns


76 TDOF SDO Data Output Fall Time — 25 ns

78 TSCR SCK Output Rise Time (Master mode)

PIC18FXX8X — 25 ns


79 TSCF SCK Output Fall Time (Master mode) — 25 ns

80 TSCH2DOV,TSCL2DOV

SDO Data Output Valid after SCK Edge



Note 1: Requires the use of Parameter #73A.2: Only if Parameter #71A and #72A are used.


PIC18F6585/8585/6680/8680

FIGURE 27-16: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)

TABLE 27-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)

SS

SCK(CKP = 0)

SCK(CKP = 1)

SDO

SDI

81

71 72

74

75, 76

78

80

MSb

7973

MSb In

bit 6 - - - - - -1

LSb Inbit 6 - - - -1

LSb


Param. No.


71 TSCH SCK Input High Time (Slave mode)



72 TSCL SCK Input Low Time (Slave mode)





73A TB2B Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2

1.5 TCY + 40 — ns (Note 2)




PIC18LFXX8X 45 ns




PIC18LFXX8X 45 ns





PIC18LFXX8X 100 ns

81 TDOV2SCH,TDOV2SCL

SDO Data Output Setup to SCK Edge TCY — ns



PIC18F6585/8585/6680/8680

FIGURE 27-17: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)

TABLE 27-17: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)

Param. No.




71 TSCH SCK Input High Time (Slave mode) Continuous 1.25 TCY + 30 — ns


72 TSCL SCK Input Low Time (Slave mode) Continuous 1.25 TCY + 30 — ns




73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)




PIC18LFXX8X 45 ns


77 TSSH2DOZ SS ↑ to SDO Output High-Impedance 10 50 ns

78 TSCR SCK oUtput Rise Time (Master mode) PIC18FXX8X — 25 ns

PIC18LFXX8X 45 ns



SDO Data Output Valid after SCK Edge PIC18FXX8X — 50 ns

PIC18LFXX8X 100 ns

83 TSCH2SSH,TSCL2SSH

SS ↑ after SCK Edge 1.5 TCY + 40 — ns

Note 1: Requires the use of Parameter #73A.

2: Only if Parameter #71A and #72A are used.

SS

SCK(CKP = 0)

SCK(CKP = 1)

SDO

SDI

70

71 72

7374

75, 76 77

787980

7978

SDI

MSb LSbbit 6 - - - - - -1

MSb In bit 6 - - - -1 LSb In

83



PIC18F6585/8585/6680/8680

FIGURE 27-18: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)

TABLE 27-18: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)

Param. No.




71 TSCH SCK Input High Time (Slave mode) Continuous 1.25 TCY + 30 — ns


72 TSCL SCK Input Low Time (Slave mode) Continuous 1.25 TCY + 30 — ns


73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)




PIC18LFXX8X 45 ns


77 TSSH2DOZ SS ↑ to SDO Output High-Impedance 10 50 ns









82 TSSL2DOV SDO Data Output Valid after SS ↓ Edge



83 TSCH2SSH,TSCL2SSH

SS ↑ after SCK Edge 1.5 TCY + 40 — ns


SS

SCK(CKP = 0)

SCK(CKP = 1)

SDO

SDI

70

71 72

82

SDI

74

75, 76

MSb bit 6 - - - - - -1 LSb

77

MSb In bit 6 - - - -1 LSb In

80

83



PIC18F6585/8585/6680/8680

FIGURE 27-19: I2C BUS START/STOP BITS TIMING

TABLE 27-19: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)

FIGURE 27-20: I2C BUS DATA TIMING


91

92

93SCL

SDA

StartCondition

StopCondition

90

Param. No.


90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated Start conditionSetup Time 400 kHz mode 600 —

91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first clock pulse is generatedHold Time 400 kHz mode 600 —

92 TSU:STO Stop Condition 100 kHz mode 4700 — ns

Setup Time 400 kHz mode 600 —

93 THD:STO Stop Condition 100 kHz mode 4000 — ns

Hold Time 400 kHz mode 600 —


90

91 92

100

101

103

106 107

109 109110

102

SCL

SDAIn

SDAOut


PIC18F6585/8585/6680/8680

TABLE 27-20: I2C BUS DATA REQUIREMENTS (SLAVE MODE)

Param. No.


100 THIGH Clock High Time 100 kHz mode 4.0 — µs PIC18FXX8X must operate at a minimum of 1.5 MHz

400 kHz mode 0.6 — µs PIC18FXX8X must operate at a minimum of 10 MHz

SSP Module 1.5 TCY —

101 TLOW Clock Low Time 100 kHz mode 4.7 — µs PIC18FXX8X must operate at a minimum of 1.5 MHz

400 kHz mode 1.3 — µs PIC18FXX8X must operate at a minimum of 10 MHz

SSP Module 1.5 TCY —

102 TR SDA and SCL Rise Time

100 kHz mode — 1000 ns

400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF

103 TF SDA and SCL Fall Time


400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF

90 TSU:STA Start Condition Setup Time

100 kHz mode 4.7 — µs Only relevant for Repeated Start condition400 kHz mode 0.6 — µs

91 THD:STA Start Condition Hold Time

100 kHz mode 4.0 — µs After this period, the first clock pulse is generated400 kHz mode 0.6 — µs

106 THD:DAT Data Input Hold Time

100 kHz mode 0 — ns

400 kHz mode 0 0.9 µs

107 TSU:DAT Data Input Setup Time

100 kHz mode 250 — ns (Note 2)


92 TSU:STO Stop Condition Setup Time

100 kHz mode 4.7 — µs


109 TAA Output Valid from Clock

100 kHz mode — 3500 ns (Note 1)

400 kHz mode — — ns

110 TBUF Bus Free Time 100 kHz mode 4.7 — µs Time the bus must be free before a new transmission can Start


D102 CB Bus Capacitive Loading — 400 pF

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system but the requirement, TSU:DAT ≥ 250 ns, must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line.TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.


PIC18F6585/8585/6680/8680

FIGURE 27-21: MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS

TABLE 27-21: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS

FIGURE 27-22: MASTER SSP I2C BUS DATA TIMING


91 93SCL

SDA

StartCondition

StopCondition

90 92

Param.No.



100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for Repeated Start condition

400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1) 2(TOSC)(BRG + 1) —


100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the first clock pulse is generated



92 TSU:STO Stop ConditionSetup Time

100 kHz mode 2(TOSC)(BRG + 1) — ns



93 THD:STO Stop ConditionHold Time

100 kHz mode 2(TOSC)(BRG + 1) — ns



Note 1: Maximum pin capacitance = 10 pF for all I2C pins.


9091 92

100

101

103

106107

109 109 110

102

SCL

SDAIn

SDAOut


PIC18F6585/8585/6680/8680

TABLE 27-22: MASTER SSP I2C BUS DATA REQUIREMENTS Param.

No.Symbol Characteristic Min Max Units Conditions

100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) — ms

101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms



102 TR SDA and SCL Rise Time

100 kHz mode — 1000 ns CB is specified to be from 10 to 400 pF 400 kHz mode 20 + 0.1 CB 300 ns

1 MHz mode(1) — 300 ns

103 TF SDA and SCL Fall Time

100 kHz mode — 300 ns CB is specified to be from 10 to 400 pF 400 kHz mode 20 + 0.1 CB 300 ns

1 MHz mode(1) — 100 ns


100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for Repeated Start condition




100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first clock pulse is generated400 kHz mode 2(TOSC)(BRG + 1) — ms


106 THD:DAT Data Input Hold Time


400 kHz mode 0 0.9 ms

1 MHz mode(1) TBD — ns

107 TSU:DAT Data Input Setup Time

100 kHz mode 250 — ns (Note 2)


1 MHz mode(1) TBD — ns

92 TSU:STO Stop Condition Setup Time




109 TAA Output Valid from Clock



1 MHz mode(1) — — ns

110 TBUF Bus Free Time 100 kHz mode 4.7 — ms Time the bus must be free before a new transmission can start

400 kHz mode 1.3 — ms

1 MHz mode(1) TBD — ms

D102 CB Bus Capacitive Loading — 400 pF

Note 1: Maximum pin capacitance = 10 pF for all I2C pins.

2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107 ≥ 250 ns, must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the SCL line is released.


PIC18F6585/8585/6680/8680

FIGURE 27-23: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

TABLE 27-23: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS

FIGURE 27-24: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

TABLE 27-24: USART SYNCHRONOUS RECEIVE REQUIREMENTS

121 121

120122

RC6/TX/CK

RC7/RX/DTpin

pin


Param. No.


120 TCKH2DTV SYNC XMIT (MASTER & SLAVE)Clock High to Data Out Valid PIC18FXX8X — 40 ns


121 TCKRF Clock Out Rise Time and Fall Time (Master mode)



122 TDTRF Data Out Rise Time and Fall Time PIC18FXX8X — 20 ns


125

126

RC6/TX/CK

RC7/RX/DT

pin

pin


Param. No.


125 TDTV2CKL SYNC RCV (MASTER & SLAVE)Data Hold before CK ↓ (DT hold time) 10 — ns

126 TCKL2DTL Data Hold after CK ↓ (DT hold time) 15 — ns


PIC18F6585/8585/6680/8680

TABLE 27-25: A/D CONVERTER CHARACTERISTICS:PIC18F6585/8585/6680/8680 (INDUSTRIAL, EXTENDED) PIC18LF6585/8585/6680/8680 (INDUSTRIAL)

Param No.


A01 NR Resolution ——

——

10TBD

bitbit

VREF = VDD ≥ 3.0V VREF = VDD < 3.0V

A03 EIL Integral Linearity Error ——

——

<±1 TBD

LSbLSb


A04 EDL Differential Linearity Error ——

——

<±1TBD

LSbLSb


A05 EFS Full-Scale Error ——

——

<±1TBD

LSbLSb


A06 EOFF Offset Error ——

——

<±1TBD

LSbLSb


A10 — Monotonicity guaranteed(3) — VSS ≤ VAIN ≤ VREF

A20 VREF Reference Voltage(VREFH – VREFL)

0V — — V

A20A 3V — — V For 10-bit resolution

A21 VREFH Reference Voltage High AVss — AVDD + 0.3V V

A22 VREFL Reference Voltage Low AVss – 0.3V — AVDD V

A25 VAIN Analog Input Voltage AVSS – 0.3V — VREF + 0.3V V

A30 ZAIN Recommended Impedance of Analog Voltage Source

— — 10.0 kΩ

A40 IAD A/D ConversionCurrent (VDD)

PIC18FXX8X — 180 — µA Average current consumption when A/D is on (Note 1)

PIC18LFXX8X — 90 — µA

A50 IREF VREF Input Current (Note 2) ——

——

5150

µAµA

During VAIN acquisition.During A/D conversion cycle.

Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module.VREF current is from RA2/AN2/VREF- and RA3/AN3/VREF+ pins or AVDD and AVSS pins, whichever is selected as reference input.

2: Vss ≤ VAIN ≤ VREF

3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

PIC18F6585/8585/6680/8680

FIGURE 27-25: A/D CONVERSION TIMING

TABLE 27-26: A/D CONVERSION REQUIREMENTS

131

130

132

BSF ADCON0, GO

Q4

A/D CLK

A/D DATA

ADRES

ADIF

GO

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

(Note 2)

9 8 7 2 1 0

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to beexecuted.

2: This is a minimal RC delay (typically 100 ns) which also disconnects the holding capacitor from the analog input.

. . . . . .

TCY

Param. No.


130 TAD A/D Clock Period PIC18FXX8X 1.6 20(5) µs TOSC based, VREF ≥ 3.0V

PIC18LFXX8X 3.0 20(5) µs TOSC based, VREF full range

PIC18FXX8X 2.0 6.0 µs A/D RC mode

PIC18LFXX8X 3.0 9.0 µs A/D RC mode

131 TCNV Conversion Time (not including acquisition time) (Note 1)

11 12 TAD

132 TACQ Acquisition Time (Note 3) 1510

——

µsµs

-40°C ≤ Temp ≤ +125°C0°C ≤ Temp ≤ +125°C

135 TSWC Switching Time from Convert → Sample — (Note 4)

136 TAMP Amplifier Settling Time (Note 2) 1 — µs This may be used if the “new” input voltage has not changed by more than 1 LSb (i.e., 5 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD).

Note 1: ADRES register may be read on the following TCY cycle.

2: See Section 19.0 “10-bit Analog-to-Digital Converter (A/D) Module” for minimum conditions when input voltage has changed more than 1 LSb.

3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (AVDD to AVSS, or AVSS to AVDD). The source impedance (RS) on the input channels is 50Ω.

4: On the next Q4 cycle of the device clock.

5: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.


PIC18F6585/8585/6680/8680

NOTES:


PIC18F6585/8585/6680/8680

28.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES

“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3σ) or (mean – 3σ)respectively, where σ is a standard deviation, over the whole temperature range.

FIGURE 28-1: TYPICAL IDD vs. FOSC OVER VDD (HS MODE)

FIGURE 28-2: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)

Note: The graphs and tables provided following this note are a statistical summary based on a limited number ofsamples and are provided for informational purposes only. The performance characteristics listed hereinare not tested or guaranteed. In some graphs or tables, the data presented may be outside the specifiedoperating range (e.g., outside specified power supply range) and therefore, outside the warranted range.

0

4

8

12

16

20

24

28

32

36

40

4 8 12 16 20 24 28 32 36 40

FOSC (MHz)

I DD

(m

A)

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V

Typical: statistical mean @ 25°CMaximum: mean + 3σ (-40°C to +85°C) Minimum: mean – 3σ (-40°C to +85°C)

0

4

8

12

16

20

24

28

32

36

40

44

48

4 8 12 16 20 24 28 32 36 40

FOSC (MHz)

I DD

(m

A)

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V



PIC18F6585/8585/6680/8680

FIGURE 28-3: TYPICAL IDD vs. FOSC OVER VDD (HS/PLL MODE)

FIGURE 28-4: MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE)

0

4

8

12

16

20

24

28

32

36

40

4 5 6 7 8 9 10

FOSC (MHz)

IDD

(m

A)

5.5V

5.0V

4.5V

4.2V


0

5

10

15

20

25

30

35

40

45

4 5 6 7 8 9 10

FOSC (MHz)

IDD

(m

A)

5.5V

5.0V

4.5V

4.2V



PIC18F6585/8585/6680/8680

FIGURE 28-5: TYPICAL IDD vs. FOSC OVER VDD (XT MODE)

FIGURE 28-6: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE)

0

1

2

3

4

5

0 0.5 1 1.5 2 2.5 3 3.5 4

FOSC (MHz)

IDD

(m

A)

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V


0

1

2

3

4

5

6

7

0 0.5 1 1.5 2 2.5 3 3.5 4

FOSC (MHz)

IDD

(m

A)

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V



PIC18F6585/8585/6680/8680

FIGURE 28-7: TYPICAL IDD vs. FOSC OVER VDD (LP MODE)

FIGURE 28-8: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE)

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

20 30 40 50 60 70 80 90 100

FOSC (kHz)

IDD

(m

A)

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V


0

1

2

3

4

5

6

20 30 40 50 60 70 80 90 100

FOSC (kHz)

IDD

(m

A)

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V



PIC18F6585/8585/6680/8680

FIGURE 28-9: TYPICAL IDD vs. FOSC OVER VDD (EC MODE)

FIGURE 28-10: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE)

0

4

8

12

16

20

24

28

32

36

40

4 8 12 16 20 24 28 32 36 40

FOSC (MHz)

IDD

(m

A)

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V

4.2V


0

4

8

12

16

20

24

28

32

36

40

44

48

4 8 12 16 20 24 28 32 36 40

FOSC (MHz)

IDD

(m

A)

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V

4.2V



PIC18F6585/8585/6680/8680

FIGURE 28-11: TYPICAL AND MAXIMUM IT1OSC vs. VDD (TIMER1 AS SYSTEM CLOCK)

FIGURE 28-12: AVERAGE FOSC vs. VDD FOR VARIOUS R’s (RC MODE, C = 20 pF, TEMP = 25°C)

0

20

40

60

80

100

120

140

160

180

200

220

240

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IDD

(u

A)

Typ (25°C)

Max (70°C)


0

1,000

2,000

3,000

4,000

5,000

6,000

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Fre

q (

kHz)

3.3kΩ

5.1kΩ

10kΩ

100kΩ

Operation above 4MHz is not recomended.

3.3kΩ

100 kΩ

10 kΩ

5.1 kΩ

3.3 kΩ


PIC18F6585/8585/6680/8680



100 k

0

200

400

600

800

1,000

1,200

1,400

1,600

1,800

2,000

2,200

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Fre

q (

kHz)

3.3kΩ

5.1kΩ

10kΩ

100kΩ

3.3 kΩ

5.1 kΩ

10 kΩ

100 kΩ

0

100

200

300

400

500

600

700

800

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Fre

q (

MH

z)

3.3kΩ

5.1kΩ

10kΩ

100kΩ

3.3 kΩ

5.1 kΩ

10 kΩ

100 kΩ


PIC18F6585/8585/6680/8680

FIGURE 28-15: IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)

FIGURE 28-16: TYPICAL AND MAXIMUM ∆IBOR vs. VDD OVER TEMPERATURE, VBOR = 2.00V-2.16V

0.01

0.1

1

10

100

1000

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD

(u

A)

Max(-40°C to +125°C)

Typ (25°C)

Max(85°C)


0

50

100

150

200

250

300

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IDD

(u

A)

Max (+125°C)

Max (+85°C)

Typ (+25°C)

Device Held in Reset

Device in Sleep



PIC18F6585/8585/6680/8680

FIGURE 28-17: IT1OSC vs. VDD (SLEEP MODE, TIMER1 AND OSCILLATOR ENABLED)

FIGURE 28-18: IPD vs. VDD (SLEEP MODE, WDT ENABLED)

0

10

20

30

40

50

60

70

80

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD

(u

A)

Typ (25°C)

Max (70°C)


0.1

1

10

100

1000

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD

(u

A)

Max(-40°C to +125°C)

Typ (25°C)

Max(85°C)



PIC18F6585/8585/6680/8680

FIGURE 28-19: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD

FIGURE 28-20: ∆ILVD vs. VDD OVER TEMPERATURE, VLVD = 4.5-4.78V

0

5

10

15

20

25

30

35

40

2.5 3.0 3.5 4.0 4.5 5.0 5.5VDD (V)

WD

T P

erio

d (

ms)

Max (125°C)

Min (-40°C)

Typ (25°C)

Max (85°C)


0

50

100

150

200

250

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IDD

(µA

)

Max (125°C)

Typ (25°C)

Max (125°C)

Typ (25°C)

LVDIF is set by hardware

LVDIF can be cleared by firmware

LVDIF state is unknown



PIC18F6585/8585/6680/8680

FIGURE 28-21: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40°C TO +125°C)

FIGURE 28-22: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40°C TO +125°C)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

0 5 10 15 20 25

IOH (-mA)

VO

H (

V)

Typ (25C)

Max

Min

Max

Typ (+25°C)

Min

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0 5 10 15 20 25

IOH (-mA)

VO

H (

V)

Typ (25C)

Max

Min

Typ (+25°C)

Min

Max


PIC18F6585/8585/6680/8680

FIGURE 28-23: TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 5V, -40°C TO +125°C)

FIGURE 28-24: TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 3V, -40°C TO +125°C)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

0 5 10 15 20 25

IOL (-mA)

VO

L (

V)

Max

Typ (25C)


Typ (+25°C)

Max

0.0

0.5

1.0

1.5

2.0

2.5

0 5 10 15 20 25

IOL (-mA)

VO

L (

V)

Max

Typ (25C)


Typ (+25°C)

Max


PIC18F6585/8585/6680/8680

FIGURE 28-25: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40°C TO +125°C)

FIGURE 28-26: MINIMUM AND MAXIMUM VIN vs. VDD (TTL INPUT, -40°C TO +125°C)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

VIN

(V

)

VIH Max

VIH Min

VIL Max

VIL Min


0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

VIN

(V

)

VTH (Max)

VTH (Min)



PIC18F6585/8585/6680/8680

FIGURE 28-27: MINIMUM AND MAXIMUM VIN vs. VDD (I2C INPUT, -40°C TO +125°C)

FIGURE 28-28: A/D NONLINEARITY vs. VREFH (VDD = VREFH, -40°C TO +125°C)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

VIN

(V

)

VIH Max

VIH Min

VILMax

VIL Min


VIL Max

0

0.5

1

1.5

2

2.5

3

3.5

4

2 2.5 3 3.5 4 4.5 5 5.5

VDD and VREFH (V)

Dif

fere

nti

al o

r In

teg

ral N

on

linea

rity

(L

SB

)

-40C

25C

85C

125C

-40°C

+25°C

+85°C

+125°C


PIC18F6585/8585/6680/8680

FIGURE 28-29: A/D NON-LINEARITY vs. VREFH (VDD = 5V, -40°C TO +125°C)

0

0.5

1

1.5

2

2.5

3

2 2.5 3 3.5 4 4.5 5 5.5

VREFH (V)

Dif

fere

nti

al o

r In

teg

ral N

on

linea

rilt

y (L

SB

)

Max (-40C to 125C)

Typ (25C)Typ (+25°C)

Max (-40°C to +125°C)


PIC18F6585/8585/6680/8680

NOTES:


PIC18F6585/8585/6680/8680

29.0 PACKAGING INFORMATION

29.1 Package Marking Information

68-Lead PLCC

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

YYWWNNN

Example

PIC18F6680-I/L0410017

64-Lead TQFP

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

YYWWNNN

Example

PIC18F6680-I/PT

0410017

80-Lead TQFP

XXXXXXXXXXXXXXXXXXXXXXXX

YYWWNNN

Example

PIC18F8680-E/PT

0410017

Legend: XX...X Customer specific information*Y Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability code

Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line thus limiting the number of available charactersfor customer specific information.

* Standard PICmicro device marking consists of Microchip part number, year code, week code, andtraceability code. For PICmicro device marking beyond this, certain price adders apply. Please checkwith your Microchip Sales Office. For QTP devices, any special marking adders are included in QTPprice.


PIC18F6585/8585/6680/8680

29.2 Package Details

The following sections give the technical details of the packages.

64-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

* Controlling Parameter

Notes:Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed.010” (0.254mm) per side.JEDEC Equivalent: MS-026Drawing No. C04-085

1510515105βMold Draft Angle Bottom1510515105αMold Draft Angle Top

0.270.220.17.011.009.007BLead Width0.230.180.13.009.007.005cLead Thickness

1616n1Pins per Side

10.1010.009.90.398.394.390D1Molded Package Length10.1010.009.90.398.394.390E1Molded Package Width12.2512.0011.75.482.472.463DOverall Length12.2512.0011.75.482.472.463EOverall Width

73.5073.50φFoot Angle

0.750.600.45.030.024.018LFoot Length0.250.150.05.010.006.002A1Standoff §1.051.000.95.041.039.037A2Molded Package Thickness1.201.101.00.047.043.039AOverall Height

0.50.020pPitch6464nNumber of Pins

MAXNOMMINMAXNOMMINDimension LimitsMILLIMETERS*INCHESUnits

c

21

n

DD1

B

p

#leads=n1

E1

E

A2

A1

A

L

CH x 45°

βφ

α

(F)

Footprint (Reference) (F) .039 1.00

Pin 1 Corner Chamfer CH .025 .035 .045 0.64 0.89 1.14

§ Significant Characteristic


PIC18F6585/8585/6680/8680

68-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)

10501050βMold Draft Angle Bottom10501050αMold Draft Angle Top

0.530.510.33.021.020.013BLower Lead Width0.810.740.66.032.029.026B1Upper Lead Width0.330.270.20.013.011.008cLead Thickness

1717n1Pins per Side

23.6223.3722.61.930.920.890D2Footprint Length23.6223.3722.61.930.920.890E2Footprint Width24.3324.2324.13.958.954.950D1Molded Package Length24.3324.2324.13.958.954.950E1Molded Package Width25.2725.1525.02.995.990.985DOverall Length25.2725.1525.02.995.990.985EOverall Width

0.250.130.00.010.005.000CH2Corner Chamfer (others)1.271.141.02.050.045.040CH1Corner Chamfer 10.860.740.61.034.029.024A3Side 1 Chamfer Height

0.51.020A1Standoff §A2Molded Package Thickness

4.574.394.19.180.173.165AOverall Height

1.27.050pPitch68nNumber of Pins

MAXNOMMINMAXNOMMINDimension LimitsMILLIMETERSINCHES*Units

β

A2

c

E2

2

DD1

n

#leads=n1

E

E1

1α

pB

A3

A

B1

32°

D2

68

A1

.145 .153 .160 3.68 3.87 4.06.028 .035 0.71 0.89

CH1 x 45 °CH2 x 45 °


Notes:Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.JEDEC Equivalent: MO-047Drawing No. C04-049



PIC18F6585/8585/6680/8680

80-Lead Plastic Thin Quad Flatpack (PT) 12x12x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)


Notes:Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.JEDEC Equivalent: MS-026Drawing No. C04-092

1.101.00.043.039

1.140.890.64.045.035.025CHPin 1 Corner Chamfer

1.00.039(F)Footprint (Reference)

(F)

EE1

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p

B

D1 D

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c

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Units INCHES MILLIMETERS*Dimension Limits MIN NOM MAX MIN NOM MAX

Number of Pins n 80 80Pitch p .020 0.50

Overall Height A .047 1.20Molded Package Thickness A2 .037 .039 .041 0.95 1.00 1.05Standoff § A1 .002 .004 .006 0.05 0.10 0.15Foot Length L .018 .024 .030 0.45 0.60 0.75

Foot Angle φ 0 3.5 7 0 3.5 7Overall Width E .541 .551 .561 13.75 14.00 14.25Overall Length D .541 .551 .561 13.75 14.00 14.25Molded Package Width E1 .463 .472 .482 11.75 12.00 12.25Molded Package Length D1 .463 .472 .482 11.75 12.00 12.25

Pins per Side n1 20 20

Lead Thickness c .004 .006 .008 0.09 0.15 0.20Lead Width B .007 .009 .011 0.17 0.22 0.27

Mold Draft Angle Top α 5 10 15 5 10 15Mold Draft Angle Bottom β 5 10 15 5 10 15

CH x 45°



PIC18F6585/8585/6680/8680

APPENDIX A: REVISION HISTORY

Revision A (February 2003)

Original data sheet for PIC18F6585/8585/6680/8680family.

Revision B (June 2003)

This revision includes updates to the Special FunctionRegisters in Table 4-2 and Table 23-1 and minorcorrections to the data sheet text.

Revision C (February 2004)

This revision includes the DC and AC CharacteristicsGraphs and Tables. The Electrical Specifications inSection 27.0 “Electrical Characteristics” have beenupdated and there have been minor corrections to thedata sheet text.

APPENDIX B: DEVICE DIFFERENCES

The differences between the devices listed in this datasheet are shown in Table B-1.

TABLE B-1: DEVICE DIFFERENCES

Feature PIC18F6585 PIC18F6680 PIC18F8585 PIC18F8680

On-Chip Program Memory (Kbytes) 48 64 48 64

I/O Ports Ports A, B, C, D, E, F, G

Ports A, B, C, D, E, F, G

Ports A, B, C, D, E, F, G, H, J

Ports A, B, C, D, E, F, G, H, J

A/D Channels 12 12 16 16

External Memory Interface No No Yes Yes

Package Types 64-pin TQFP, 68-pin PLCC

64-pin TQFP, 68-pin PLCC

80-pin TQFP 80-pin TQFP


PIC18F6585/8585/6680/8680

APPENDIX C: CONVERSION CONSIDERATIONS

This appendix discusses the considerations for con-verting from previous versions of a device to the oneslisted in this data sheet. Typically, these changes aredue to the differences in the process technology used.An example of this type of conversion is from aPIC17C756 to a PIC18F8720.

Not Applicable

APPENDIX D: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES

A detailed discussion of the differences between themid-range MCU devices (i.e., PIC16CXXX) and theenhanced devices (i.e., PIC18FXXX) is provided inAN716, “Migrating Designs from PIC16C74A/74B toPIC18C442.” The changes discussed, while devicespecific, are generally applicable to all mid-range toenhanced device migrations.

This Application Note is available as Literature NumberDS00716.


PIC18F6585/8585/6680/8680

APPENDIX E: MIGRATION FROM HIGH-END TO ENHANCED DEVICES

A detailed discussion of the migration pathway anddifferences between the high-end MCU devices (i.e.,PIC17CXXX) and the enhanced devices (i.e.,PIC18FXXXX) is provided in AN726, “PIC17CXXX toPIC18CXXX Migration.” This Application Note isavailable as Literature Number DS00726.


PIC18F6585/8585/6680/8680

NOTES:


PIC18F6585/8585/6680/8680

INDEX

AA/D .................................................................................... 249

A/D Converter Interrupt, Configuring ....................................................... 253

Acquisition Requirements ......................................... 254Acquisition Time........................................................ 254ADCON0 Register..................................................... 249ADCON1 Register..................................................... 249ADCON2 Register..................................................... 249ADRESH Register..................................................... 249ADRESH/ADRESL Registers ................................... 252ADRESL Register ..................................................... 249Analog Port Pins ....................................................... 152Analog Port Pins,

Configuring ....................................................... 255Associated Register

Summary .......................................................... 257Automatic Acquisition Time....................................... 255Calculating Minimum Required

Acquisition Time (Example) .............................. 254CCP2 Trigger ............................................................ 256Configuring the Module............................................. 253Conversion Clock (TAD) ............................................ 255Conversion Requirements ........................................ 447Conversion Status

(GO/DONE Bit) ................................................. 252Conversions .............................................................. 256Converter Characteristics ......................................... 446Minimum Charging Time........................................... 254Special Event Trigger

(CCP)................................................................ 171Special Event Trigger

(CCP2).............................................................. 256VREF+ and VREF- References ................................... 254

Absolute Maximum Ratings .............................................. 413AC (Timing) Characteristics .............................................. 426

Load Conditions for Device Timing Specifications........................................ 427

Parameter Symbology .............................................. 426Temperature and Voltage

Specifications.................................................... 427Timing Conditions ..................................................... 427

ACKSTAT Status Flag ...................................................... 219ADCON0 Register............................................................. 249

GO/DONE Bit............................................................ 252ADCON1 Register............................................................. 249ADCON2 Register............................................................. 249ADDLW ............................................................................. 371ADDWF............................................................................. 371ADDWFC .......................................................................... 372ADRESH Register............................................................. 249ADRESH/ADRESL Registers ........................................... 252ADRESL Register ............................................................. 249Analog-to-Digital Converter.

See A/D.

ANDLW............................................................................. 372ANDWF............................................................................. 373Assembler

MPASM Assembler .................................................. 407Auto-Wake-up on Sync

Break Character ....................................................... 242

BBaud Rate Generator ....................................................... 215BC..................................................................................... 373BCF .................................................................................. 374BF Status Flag.................................................................. 219Bit Timing Configuration Registers

BRGCON1................................................................ 340BRGCON2................................................................ 340BRGCON3................................................................ 340

Block Diagrams16-bit Byte Select Mode ............................................. 9816-bit Byte Write Mode ............................................... 9616-bit Word Write Mode.............................................. 97A/D............................................................................ 252Analog Input Model................................................... 253Baud Rate Generator ............................................... 215CAN Buffers and Protocol Engine ............................ 276Capture Mode Operation .......................................... 170Comparator

Analog Input Model .......................................... 263Comparator I/O Operating Modes

(diagram) .......................................................... 260Comparator Output................................................... 262Comparator Voltage Reference................................ 266Compare Mode Operation ................................ 171, 176Enhanced PWM........................................................ 178Low-Voltage Detect (LVD)........................................ 270Low-Voltage Detect (LVD) with

External Input ................................................... 270MSSP (I2C Master Mode)......................................... 213MSSP (I2C Mode)..................................................... 198MSSP (SPI Mode) .................................................... 189On-Chip Reset Circuit................................................. 33PIC18F6X8X Architecture .......................................... 10PIC18F8X8X Architecture .......................................... 11PLL ............................................................................. 25PORT/LAT/TRIS Operation ...................................... 125PORTA

RA3:RA0 and RA5 Pins.................................... 126RA4/T0CKI Pin ................................................. 126RA6 Pin (When Enabled as I/O)....................... 126

PORTBRB2:RB0 Pins................................................... 129RB3 Pin ............................................................ 129RB7:RB4 Pins................................................... 128

PORTC (Peripheral Output Override)........................................................... 131

PORTD and PORTE (Parallel Slave Port).......................................... 152


PIC18F6585/8585/6680/8680

PORTD in I/O Port Mode .......................................... 133PORTD in System Bus Mode ................................... 134PORTE in I/O Mode .................................................. 137PORTE in System Bus Mode.................................... 137PORTF

RF1/AN6/C2OUT and RF2/AN7/C1OUT Pins .............................. 139

RF6:RF3 and RF0 Pins..................................... 140RF7 Pin ............................................................. 140

PORTGRG0/CANTX1 Pin ............................................. 142RG1/CANTX2 Pin ............................................. 143RG2/CANRX Pin............................................... 143RG3 Pin ............................................................ 143RG4/P1D Pin .................................................... 144RG5/MCLR/VPP Pin .......................................... 144

PORTHRH3:RH0 Pins in I/O Mode ............................... 146RH3:RH0 Pins in

System Bus Mode..................................... 147RH7:RH4 Pins in I/O Mode ............................... 146

PORTJRJ4:RJ0 Pins in

System Bus Mode..................................... 150RJ7:RJ6 Pins in

System Bus Mode..................................... 150PORTJ in I/O Mode................................................... 149PWM (CCP Module) ................................................. 173Reads from Flash Program

Memory ............................................................... 87Single Comparator .................................................... 261Table Read Operation................................................. 83Table Write Operation ................................................. 84Table Writes to Flash Program

Memory ............................................................... 89Timer0 in 16-bit Mode ............................................... 156Timer0 in 8-bit Mode ................................................. 156Timer1....................................................................... 160Timer1 (16-bit Read/Write Mode) ............................. 160Timer2....................................................................... 163Timer3....................................................................... 165Timer3 in 16-bit Read/Write Mode ............................ 165USART Receive........................................................ 240USART Transmit ....................................................... 238Voltage Reference

Output Buffer (example).................................... 267Watchdog Timer........................................................ 356

BN ..................................................................................... 374BNC................................................................................... 375BNN................................................................................... 375BNOV................................................................................ 376BNZ ................................................................................... 376BOR. See Brown-out Reset.BOV................................................................................... 379BRA................................................................................... 377Break Character (12-bit)

Transmit and Receive ............................................... 243BRG. See Baud Rate Generator.Brown-out Reset (BOR) .............................................. 34, 345BSF ................................................................................... 377BTFSC .............................................................................. 378BTFSS............................................................................... 378BTG................................................................................... 379BZ...................................................................................... 380

CC Compilers

MPLAB C17.............................................................. 408MPLAB C18.............................................................. 408MPLAB C30.............................................................. 408

CALL................................................................................. 380Capture (CCP Module) ..................................................... 169

CAN Message Time-Stamp...................................... 170CCP Pin Configuration.............................................. 169CCPRxH:CCPRxL Registers .................................... 169Software Interrupt ..................................................... 170Timer1/Timer3 Mode Selection................................. 169

Capture, Compare (CCP Module), Timer1 and Timer3Associated Registers ................................................ 172

Capture/Compare/PWM (CCP) ........................................ 167Capture Mode.

See Capture (CCP Module).CCP Module ............................................................. 169CCPRxH Register..................................................... 169CCPRxL Register ..................................................... 169Compare Mode.

See Compare (CCP Module).Interaction of CCP1 and

CCP2 Modules ................................................. 169PWM Mode.

See PWM (CCP Module).Timer Resources ...................................................... 169

Capture/Compare/PWM Requirements ........................................................... 435

CLKO and I/O Timing Requirements ........................ 430, 431Clocking Scheme/Instruction Cycle .................................... 56CLRF ................................................................................ 381CLRWDT .......................................................................... 381Code Examples

16 x 16 Signed Multiply Routine ............................... 10816 x 16 Unsigned Multiply Routine ........................... 1088 x 8 Signed Multiply Routine ................................... 1078 x 8 Unsigned Multiply Routine ............................... 107Changing Between Capture

Prescalers......................................................... 170Changing to Configuration Mode.............................. 281Data EEPROM Read................................................ 103Data EEPROM Refresh Routine............................... 104Data EEPROM Write ................................................ 103Erasing a Flash Program

Memory Row ...................................................... 88Fast Register Stack .................................................... 56How to Clear RAM (Bank 1) Using

Indirect Addressing............................................. 79Initializing PORTA..................................................... 125Initializing PORTB..................................................... 128Initializing PORTC .................................................... 131Initializing PORTD .................................................... 133Initializing PORTE..................................................... 136Initializing PORTF..................................................... 139Initializing PORTG .................................................... 142Initializing PORTH .................................................... 146Initializing PORTJ ..................................................... 149Loading the SSPBUF (SSPSR)

Register ............................................................ 192Reading a Flash Program

Memory Word ..................................................... 87


PIC18F6585/8585/6680/8680

Saving Status, WREG and BSR Registers in RAM .............................................................. 124

Transmitting a CAN Message Using Banked Method................................................. 289

Transmitting a CAN Message Using WIN Bits ............................................................ 290

WIN and ICODE Bits Usage in Interrupt Service Routine to Access TX/RX Buffers ................................................... 281

Writing to Flash Program Memory ........................ 90–91Code Protection ................................................................ 345COMF ............................................................................... 382Comparator ....................................................................... 259

Analog Input Connection Considerations.................................................. 263

Associated Registers ................................................ 264Configuration............................................................. 260Effects of a Reset...................................................... 263Interrupts................................................................... 262Operation .................................................................. 261Operation During Sleep ............................................ 263Outputs ..................................................................... 261Reference ................................................................. 261

External Signal.................................................. 261Internal Signal ................................................... 261

Response Time......................................................... 261Comparator Specifications................................................ 423Comparator Voltage

Reference ................................................................. 265Accuracy and Error ................................................... 266Associated Registers ................................................ 267Configuring................................................................ 265Connection Considerations....................................... 266Effects of a Reset...................................................... 266Operation During Sleep ............................................ 266

Compare (CCP Module) ................................................... 171CCP Pin Configuration.............................................. 171CCPRx Register........................................................ 171Software Interrupt ..................................................... 171Special Event Trigger................................ 161, 166, 171Timer1/Timer3 Mode

Selection ........................................................... 171Compare (CCP2 Module)

Special Event Trigger................................................ 256Configuration Bits.............................................................. 345Configuration Mode........................................................... 328Control Registers

EECON1 and EECON2 .............................................. 84TABLAT (Table Latch)

Register .............................................................. 86TBLPTR (Table Pointer)

Register .............................................................. 86Conversion Considerations ............................................... 470CPFSEQ ........................................................................... 382CPFSGT ........................................................................... 383CPFSLT ............................................................................ 383

DData EEPROM Memory

Associated Registers................................................ 105EEADRH

EEADR Register Pair ....................................... 101EECON1 Register .................................................... 101EECON2 Register .................................................... 101Operation During

Code-Protect .................................................... 104Protection Against

Spurious Write .................................................. 104Reading .................................................................... 103Using ........................................................................ 104Write Verify ............................................................... 104Writing to .................................................................. 103

Data Memory ...................................................................... 59General Purpose Registers ........................................ 59Map for PIC18FXX80/XX85

Devices............................................................... 60Special Function Registers......................................... 59

DAW ................................................................................. 384DC and AC Characteristics

Graphs and Tables ................................................... 449DC Characteristics

PIC18FXX8X (Industrial and Extended), PIC18LFXX8X (Industrial)......................................................... 421

Power-down and Supply Current.................................................. 417

Supply Voltage ......................................................... 416DCFSNZ ........................................................................... 385DECF................................................................................ 384DECFSZ ........................................................................... 385Demonstration Boards

PICDEM 1................................................................. 410PICDEM 17............................................................... 411PICDEM 18R ............................................................ 411PICDEM 2 Plus......................................................... 410PICDEM 3................................................................. 410PICDEM 4................................................................. 410PICDEM LIN ............................................................. 411PICDEM USB ........................................................... 411PICDEM.net Internet/

Ethernet ............................................................ 410Development Support ....................................................... 407Device Differences............................................................ 469Device Features.................................................................... 9Device Overview................................................................... 9Direct Addressing ............................................................... 78Disable Mode.................................................................... 328


PIC18F6585/8585/6680/8680

EECAN Module ................................................................... 275

Baud Rate Setting..................................................... 337Bit Time Partitioning.................................................. 337Bit Timing Configuration

Registers........................................................... 340Calculating TQ, Nominal Bit Rate and

Nominal Bit Time............................................... 338CAN Baud Rate Registers ........................................ 315CAN Control and Status

Registers........................................................... 277CAN Controller Register Map ................................... 323CAN I/O Control Register.......................................... 318CAN Interrupt Registers............................................ 319CAN Interrupts .......................................................... 342

Acknowledge..................................................... 343Bus Activity Wake-up ........................................ 343Bus-Off.............................................................. 343Code Bits .......................................................... 342Error .................................................................. 343Message Error .................................................. 343Receive ............................................................. 343Receiver Bus Passive ....................................... 343Receiver Overflow............................................. 343Receiver Warning ............................................. 343Transmit ............................................................ 342Transmitter Bus Passive ................................... 343Transmitter Warning ......................................... 343

CAN Message Buffers .............................................. 331Dedicated Receive............................................ 331Dedicated Transmit........................................... 331Programmable Auto-RTR ................................. 332Programmable

Transmit/Receive...................................... 331CAN Message Transmission .................................... 332

Aborting............................................................. 332Initiating............................................................. 332Priority............................................................... 333

CAN Modes of Operation.......................................... 328CAN Registers .......................................................... 277Configuration Mode................................................... 328Dedicated CAN Receive

Buffer Registers ................................................ 291Dedicated CAN Transmit

Buffer Registers ................................................ 285Disable Mode ............................................................ 328Error Detection.......................................................... 341

Acknowledge..................................................... 341Bit...................................................................... 341CRC .................................................................. 341Error Modes and Counters................................ 341Error States....................................................... 341Form.................................................................. 341Stuff Bit ............................................................. 341

Error Modes State (diagram) .................................... 342Error Recognition Mode ............................................ 330Filter-Mask Truth (table)............................................ 335Functional Modes...................................................... 330

Mode 0 - Legacy Mode ..................................... 330Mode 1 - Enhanced

Legacy Mode ............................................ 330Mode 2 - Enhanced

FIFO Mode................................................ 331

Information Processing Time (IPT).................................................................. 338

Lengthening a Bit Period .......................................... 339Listen Only Mode...................................................... 330Loopback Mode ........................................................ 330Message Acceptance Filters

and Masks ................................................ 306, 335Message Acceptance Mask and

Filter Operation................................................. 336Message Reception.................................................. 334

Enhanced FIFO Mode ...................................... 335Priority .............................................................. 334Time-Stamping ................................................. 335

Normal Mode ............................................................ 328Oscillator Tolerance.................................................. 340Overview................................................................... 275Phase Buffer Segments............................................ 338Programmable TX/RX and

Auto-RTR Buffers ............................................. 297Programming Time Segments .................................. 340Propagation Segment ............................................... 338Sample Point ............................................................ 338Shortening a Bit Period............................................. 340Synchronization ........................................................ 339

Hard.................................................................. 339Resynchronization ............................................ 339Rules ................................................................ 339

Synchronization Segment......................................... 338Time Quanta............................................................. 338

Electrical Characteristics .................................................. 413Enhanced Capture/Compare/PWM

(ECCP) ..................................................................... 175Outputs ..................................................................... 176

Enhanced PWM Mode. See PWM (ECCP Module).

Enhanced Universal Synchronous Asynchronous Receiver Transmitter (USART) ................................................ 229

Errata .................................................................................... 7Error Recognition Mode.................................................... 328Evaluation and Programming Tools.................................. 411Example SPI Mode Requirements

(Master Mode, CKE = 0)........................................... 437Example SPI Mode Requirements

(Master Mode, CKE = 1)........................................... 438Example SPI Mode Requirements

(Slave Mode, CKE = 0)............................................. 439Example SPI Slave Mode Requirements

(CKE = 1).................................................................. 440External Clock Timing

Requirements ........................................................... 428External Memory Interface.................................................. 93

16-bit Byte Select Mode.............................................. 9816-bit Byte Write Mode ............................................... 9616-bit Mode................................................................. 9616-bit Mode Timing ..................................................... 9916-bit Word Write Mode.............................................. 97PIC18F8X8X External Bus -

I/O Port Functions............................................... 95Program Memory Modes ............................................ 93


PIC18F6585/8585/6680/8680

FFirmware Instructions........................................................ 365Flash Program Memory ...................................................... 83

Associated Registers .................................................. 92Control Registers ........................................................ 84Erase Sequence ......................................................... 88Erasing........................................................................ 88Operation During Code

Protection............................................................ 92Reading....................................................................... 87Table Pointer

Boundaries Based on Operation......................... 86Table Pointer Boundaries ........................................... 86Table Reads and Table Writes ................................... 83Write Sequence .......................................................... 90Writing to..................................................................... 89

Protection Against Spurious Writes.......................................................... 92

Unexpected Termination..................................... 92Write Verify ......................................................... 92

GGeneral Call Address Support .......................................... 212GOTO ............................................................................... 386

HHardware Multiplier ........................................................... 107

Introduction ............................................................... 107Operation .................................................................. 107Performance Comparison

(table)................................................................ 107

II/O Ports ............................................................................ 125I2C Bus Data Requirements

(Slave Mode)............................................................. 442I2C Bus Start/Stop Bits Requirements

(Slave Mode)............................................................. 441I2C Mode

General Call Address Support .................................. 212Master Mode

Operation .......................................................... 214Read/Write Bit Information

(R/W Bit) ................................................... 202, 203Serial Clock (RC3/SCK/SCL).................................... 203

ID Locations .............................................................. 345, 362INCF.................................................................................. 386INCFSZ ............................................................................. 387In-Circuit Debugger ........................................................... 362

Resources (table)...................................................... 362In-Circuit Serial Programming

(ICSP) ............................................................... 345, 362Indirect Addressing

INDF and FSR Registers ............................................ 79Operation .................................................................... 79

Indirect File Operand .......................................................... 59INFSNZ ............................................................................. 387Instruction Flow/Pipelining .................................................. 57Instruction Format ............................................................. 367

Instruction Set................................................................... 365ADDLW..................................................................... 371ADDWF .................................................................... 371ADDWFC.................................................................. 372ANDLW..................................................................... 372ANDWF .................................................................... 373BC............................................................................. 373BCF .......................................................................... 374BN............................................................................. 374BNC .......................................................................... 375BNN .......................................................................... 375BNOV ....................................................................... 376BNZ .......................................................................... 376BOV .......................................................................... 379BRA .......................................................................... 377BSF........................................................................... 377BTFSC...................................................................... 378BTFSS ...................................................................... 378BTG .......................................................................... 379BZ ............................................................................. 380CALL......................................................................... 380CLRF ........................................................................ 381CLRWDT .................................................................. 381COMF ....................................................................... 382CPFSEQ................................................................... 382CPFSGT ................................................................... 383CPFSLT.................................................................... 383DAW ......................................................................... 384DCFSNZ ................................................................... 385DECF........................................................................ 384DECFSZ ................................................................... 385GOTO ....................................................................... 386INCF ......................................................................... 386INCFSZ..................................................................... 387INFSNZ..................................................................... 387IORLW...................................................................... 388IORWF...................................................................... 388LFSR ........................................................................ 389MOVF ....................................................................... 389MOVFF ..................................................................... 390MOVLB..................................................................... 390MOVLW .................................................................... 391MOVWF.................................................................... 391MULLW..................................................................... 392MULWF .................................................................... 392NEGF........................................................................ 393NOP.......................................................................... 393POP .......................................................................... 394PUSH........................................................................ 394RCALL ...................................................................... 395RESET...................................................................... 395RETFIE..................................................................... 396RETLW ..................................................................... 396RETURN................................................................... 397RLCF ........................................................................ 397RLNCF...................................................................... 398RRCF........................................................................ 398RRNCF ..................................................................... 399SETF ........................................................................ 399


PIC18F6585/8585/6680/8680

SLEEP ...................................................................... 400SUBFWP................................................................... 400SUBLW ..................................................................... 401SUBWF ..................................................................... 401SUBWFB................................................................... 402SWAPF ..................................................................... 402TBLRD ...................................................................... 403TBLWT...................................................................... 404TSTFSZ .................................................................... 405XORLW..................................................................... 405XORWF..................................................................... 406Summary Table......................................................... 368

INT Interrupt (RB0/INT). See Interrupt Sources.

INTCON Registers ............................................................ 111Inter-Integrated Circuit. See I2C.Interrupt Sources............................................................... 345

A/D Conversion Complete ........................................ 253Capture Complete (CCP).......................................... 170Compare Complete (CCP)........................................ 171ECAN Module ........................................................... 342INT0 .......................................................................... 124Interrupt-on-Change

(RB7:RB4)......................................................... 128PORTB, Interrupt-on-Change ................................... 124RB0/INT Pin, External ............................................... 124TMR0 ........................................................................ 124TMR0 Overflow ......................................................... 157TMR1 Overflow ................................................. 159, 161TMR2 to PR2 Match ................................................. 163TMR2 to PR2 Match (PWM) ..................... 162, 173, 177TMR3 Overflow ................................................. 164, 166

Interrupts ........................................................................... 109Context Saving During

Interrupts........................................................... 124Control Registers ...................................................... 111Enable Registers....................................................... 117Flag Registers........................................................... 114Logic (diagram) ......................................................... 110Priority Registers....................................................... 120Reset Control Registers............................................ 123

Interrupts, Flag BitsCCP Flag (CCPxIF Bit) ............................. 169, 170, 171

IORLW .............................................................................. 388IORWF .............................................................................. 388IPR Registers .................................................................... 120

LLFSR ................................................................................. 389Listen Only Mode .............................................................. 328Look-up Tables

Computed GOTO........................................................ 58Table Reads/Table Writes .......................................... 58

Loopback Mode................................................................. 328Low-Voltage Detect........................................................... 269

Characteristics .......................................................... 424Converter Characteristics ......................................... 424Effects of a Reset...................................................... 273Operation .................................................................. 272

Current Consumption........................................ 273During Sleep ..................................................... 273Reference Voltage Set Point............................. 273

Typical Application .................................................... 269Low-Voltage ICSP Programming ...................................... 363LVD. See Low-Voltage Detect.

MMaster SSP I2C Bus

Data Requirements................................................... 444Master SSP I2C Bus Start/Stop Bits

Requirements ........................................................... 443Master Synchronous Serial Port (MSSP).

See MSSP.Memory Organization

Data Memory .............................................................. 59PIC18F8X8X Program Memory Modes ...................... 51

Extended Microcontroller.................................... 51Microcontroller .................................................... 51Microprocessor ................................................... 51Microprocessor with

Boot Block .................................................. 51Program Memory ........................................................ 51

Memory Programming Requirements............................... 425Migration from High-End to

Enhanced Devices.................................................... 471Migration from Mid-Range to

Enhanced Devices.................................................... 470MOVF ............................................................................... 389MOVFF ............................................................................. 390MOVLB ............................................................................. 390MOVLW ............................................................................ 391MOVWF ............................................................................ 391MPLAB ASM30 Assembler,

Linker, Librarian........................................................ 408MPLAB ICD 2 In-Circuit Debugger ................................... 409MPLAB ICE 2000 High-Performance Universal

In-Circuit Emulator .................................................... 409MPLAB ICE 4000 High-Performance Universal

In-Circuit Emulator .................................................... 409MPLAB Integrated Development

Environment Software .............................................. 407MPLAB PM3 Device Programmer .................................... 409MPLINK Object Linker/

MPLIB Object Librarian............................................. 408MSSP................................................................................ 189

ACK Pulse ........................................................ 202, 203Clock Stretching........................................................ 208

10-bit Slave Receive Mode (SEN = 1).................................................. 208

10-bit Slave Transmit Mode.............................. 2087-bit Slave Receive Mode

(SEN = 1).................................................. 2087-bit Slave Transmit Mode................................ 208

Clock Synchronization and the CKP Bit ............................................................. 209

Control Registers (general)....................................... 189I2C Mode .................................................................. 198

Acknowledge Sequence Timing ....................... 222Baud Rate Generator ....................................... 215Bus Collision

During a Repeated Start Condition.................................. 226

Bus Collision During a Start Condition.......................................... 224

Bus Collision During a Stop Condition.......................................... 227

Clock Arbitration ............................................... 216Effect of a Reset ............................................... 223I2C Clock Rate w/BRG ..................................... 215


PIC18F6585/8585/6680/8680

Master Mode..................................................... 213Reception.................................................. 219Repeated Start Condition

Timing............................................... 218Transmission ............................................ 219

Master Mode Start Condition ............................ 217Module Operation ............................................. 202Multi-Master Communication,

Bus Collision and Arbitration ................................................. 223

Multi-Master Mode ............................................ 223Registers........................................................... 198Slave Mode....................................................... 202Slave Mode, Addressing................................... 202Slave Mode, Reception..................................... 203Slave Mode, Transmission ............................... 203Sleep Operation................................................ 223Stop Condition Timing ...................................... 222

I2C Mode. See I2C.Overview ................................................................... 189SPI Mode .................................................................. 189

Associated Registers ........................................ 197Bus Mode Compatibility .................................... 197Effects of a Reset ............................................. 197Enabling SPI I/O ............................................... 193Master Mode..................................................... 194Operation .......................................................... 192Slave Mode....................................................... 195Slave Select

Synchronization ........................................ 195Sleep Operation................................................ 197SPI Clock .......................................................... 194Typical Connection ........................................... 193

SPI Mode. See SPI.SSPBUF Register ..................................................... 194SSPSR Register ....................................................... 194

MSSP ModuleSPI Master/Slave Connection ................................... 193

MULLW ............................................................................. 392MULWF............................................................................. 392

NNEGF ................................................................................ 393NOP .................................................................................. 393Normal Operation Mode.................................................... 328

OOpcode Field Descriptions................................................ 366OPTION_REG Register

PSA Bit...................................................................... 157T0CS Bit.................................................................... 157T0PS2:T0PS0 Bits .................................................... 157T0SE Bit.................................................................... 157

Oscillator Configuration....................................................... 23EC ............................................................................... 23ECIO ........................................................................... 23ECIO+PLL................................................................... 23ECIO+SPLL ................................................................ 23HS............................................................................... 23HS+PLL ...................................................................... 23HS+SPLL .................................................................... 23LP................................................................................ 23RC............................................................................... 23RCIO........................................................................... 23XT ............................................................................... 23

Oscillator Selection ........................................................... 345Oscillator Start-up Timer (OST) .................................. 34, 345Oscillator Switching Feature

System Clock Switch Bit............................................. 27Oscillator, Timer1.............................................. 159, 161, 166Oscillator, Timer3.............................................................. 164Oscillator, WDT................................................................. 355

PPackaging......................................................................... 465

Details....................................................................... 466Marking..................................................................... 465

Parallel Slave Port (PSP).......................................... 133, 152Associated Registers................................................ 154RE0/RD/AD8 Pin ...................................................... 152RE1/WR/AD9 Pin ..................................................... 152RE2/CS/AD10 Pin .................................................... 152Select (PSPMODE Bit) ..................................... 133, 152

Parallel Slave Port Requirements (PIC18FXX8X).......................................................... 436

Phase Locked Loop (PLL) .................................................. 25PICkit 1 Flash Starter Kit .................................................. 411PICSTART Plus Development

Programmer.............................................................. 410PIE Registers.................................................................... 117Pin Functions

AVDD........................................................................... 21AVSS........................................................................... 21OSC1/CLKI................................................................. 12OSC2/CLKO/RA6 ....................................................... 12RA0/AN0..................................................................... 13RA1/AN1..................................................................... 13RA2/AN2/VREF- .......................................................... 13RA3/AN3/VREF+ ......................................................... 13RA4/T0CKI ................................................................. 13RA5/AN4/LVDIN ......................................................... 13RA6............................................................................. 13RB0/INT0.................................................................... 14RB1/INT1.................................................................... 14RB2/INT2.................................................................... 14RB3/INT3/CCP2 ......................................................... 14RB4/KBI0.................................................................... 14RB5/KBI1/PGM........................................................... 14RB6/KBI2/PGC ........................................................... 14RB7/KBI3/PGD ........................................................... 14RC0/T1OSO/T13CKI .................................................. 15RC1/T1OSI/CCP2 ...................................................... 15RC2/CCP1/P1A .......................................................... 15RC3/SCK/SCL ............................................................ 15RC4/SDI/SDA ............................................................. 15RC5/SDO.................................................................... 15RC6/TX/CK................................................................. 15RC7/RX/DT................................................................. 15RD0/PSP0/AD0 .......................................................... 16RD1/PSP1/AD1 .......................................................... 16RD2/PSP2/AD2 .......................................................... 16RD3/PSP3/AD3 .......................................................... 16RD4/PSP4/AD4 .......................................................... 16RD5/PSP5/AD5 .......................................................... 16RD6/PSP6/AD6 .......................................................... 16RD7/PSP7/AD7 .......................................................... 16RE0/RD/AD8 .............................................................. 17RE1/WR/AD9.............................................................. 17


PIC18F6585/8585/6680/8680

RE2/CS/AD10 ............................................................. 17RE3/AD11 ................................................................... 17RE4/AD12 ................................................................... 17RE5/AD13/P1C ........................................................... 17RE6/AD14/P1B ........................................................... 17RE7/CCP2/AD15 ........................................................ 17RF0/AN5 ..................................................................... 18RF1/AN6/C2OUT ........................................................ 18RF2/AN7/C1OUT ........................................................ 18RF3/AN8/C2IN+ .......................................................... 18RF4/AN9/C2IN-........................................................... 18RF5/AN10/C1IN+/CVREF ............................................ 18RF6/AN11/C1IN-......................................................... 18RF7/SS ....................................................................... 18RG0/CANTX1 ............................................................. 19RG1/CANTX2 ............................................................. 19RG2/CANRX ............................................................... 19RG3............................................................................. 19RG4/P1D..................................................................... 19RG5/MCLR/VPP .......................................................... 12RH0/A16 ..................................................................... 20RH1/A17 ..................................................................... 20RH2/A18 ..................................................................... 20RH3/A19 ..................................................................... 20RH4/AN12................................................................... 20RH5/AN13................................................................... 20RH6/AN14/P1C........................................................... 20RH7/AN15/P1B ........................................................... 20RJ0/ALE...................................................................... 21RJ1/OE ....................................................................... 21RJ2/WRL..................................................................... 21RJ3/WRH .................................................................... 21RJ4/BA0...................................................................... 21RJ5/CE........................................................................ 21RJ6/LB ........................................................................ 21RJ7/UB........................................................................ 21VDD.............................................................................. 21VSS.............................................................................. 21

PIR Registers .................................................................... 114PLL Clock Timing Specifications....................................... 429PLL Lock Time-out .............................................................. 34Pointer, FSR........................................................................ 79POP................................................................................... 394POR. See Power-on Reset.PORTA

Associated Registers ................................................ 127Functions .................................................................. 127LATA Register........................................................... 125PORTA Register ....................................................... 125TRISA Register ......................................................... 125

PORTBAssociated Registers ................................................ 130Functions .................................................................. 130LATB Register........................................................... 128PORTB Register ....................................................... 128RB0/INT Pin, External ............................................... 124TRISB Register ......................................................... 128

PORTCAssociated Registers ................................................ 132Functions .................................................................. 132LATC Register .......................................................... 131PORTC Register ....................................................... 131RC3/SCK/SCL Pin .................................................... 203TRISC Register ......................................................... 131

PORTD ............................................................................. 152Associated Registers ................................................ 135Functions .................................................................. 135LATD Register .......................................................... 133Parallel Slave Port (PSP)

Function............................................................ 133PORTD Register....................................................... 133TRISD Register......................................................... 133

PORTEAnalog Port Pins ....................................................... 152Associated Registers ................................................ 138Functions .................................................................. 138LATE Register .......................................................... 136PORTE Register ....................................................... 136PSP Mode Select

(PSPMODE Bit) ........................................ 133, 152RE0/RD/AD8 Pin ...................................................... 152RE1/WR/AD9 Pin...................................................... 152RE2/CS/AD10 Pin..................................................... 152TRISE Register......................................................... 136

PORTFAssociated Registers ................................................ 141Functions .................................................................. 141LATF Register........................................................... 139PORTF Register ....................................................... 139TRISF Register ......................................................... 139

PORTGAssociated Registers ................................................ 145Functions .................................................................. 145LATG Register .......................................................... 142PORTG Register....................................................... 142TRISG Register ........................................................ 142

PORTHAssociated Registers ................................................ 148Functions .................................................................. 148LATH Register .......................................................... 146PORTH Register....................................................... 146TRISH Register......................................................... 146

PORTJAssociated Registers ................................................ 151Functions .................................................................. 151LATJ Register ........................................................... 149PORTJ Register........................................................ 149TRISJ Register ......................................................... 149

Postscaler, WDTAssignment (PSA Bit) ............................................... 157Rate Select

(T0PS2:T0PS0 Bits) ......................................... 157Power-down Mode. See Sleep.Power-on Reset (POR)............................................... 34, 345Power-up Delays ................................................................ 31Power-up Timer (PWRT) ............................................ 34, 345Prescaler

Timer2 ...................................................................... 177Prescaler, Capture............................................................ 170Prescaler, Timer0 ............................................................. 157

Assignment (PSA Bit) ............................................... 157Rate Select

(T0PS2:T0PS0 Bits) ......................................... 157Prescaler, Timer2 ............................................................. 173PRO MATE II Universal Device

Programmer.............................................................. 409


PIC18F6585/8585/6680/8680

Product Identification System ........................................... 487Program Counter

PCL, PCLATH and PCLATU Registers............................................................. 56

Program MemoryInstructions.................................................................. 57

Two-Word ........................................................... 58Interrupt Vector ........................................................... 51Map and Stack for

PIC18F6585/8585............................................... 52Map and Stack for

PIC18F6680/8680............................................... 52Memory Access for

PIC18F8X8X Modes ........................................... 52Memory Maps for

PIC18F8X8X Modes ........................................... 53Reset Vector ............................................................... 51

Program Memory ModesExtended Microcontroller ............................................ 93Microcontroller ............................................................ 93Microprocessor ........................................................... 93Microprocessor with

Boot Block........................................................... 93Program Memory Write Timing

Requirements............................................................ 432Program Verification and

Code Protection ........................................................ 359Associated Registers ................................................ 359Configuration Register

Protection.......................................................... 362Data EEPROM Code

Protection.......................................................... 362Memory Code Protection .......................................... 360

Programming, Device Instructions .................................... 365PSP. See Parallel Slave Port.PUSH ................................................................................ 394PWM (CCP Module) ......................................................... 173

CCPR1H:CCPR1L Registers.................................... 177CCPR1L:CCPR1H Registers.................................... 173Duty Cycle......................................................... 173, 177Example Frequencies/

Resolutions ............................................... 174, 178Period................................................................ 173, 177Registers Associated with PWM

and Timer2........................................................ 187Setup for PWM Operation......................................... 174TMR2 to PR2 Match ................................. 162, 173, 177

PWM (CCP Module) and Timer2Associated Registers ................................................ 174

PWM (ECCP Module) ....................................................... 177Effects of a Reset...................................................... 187Enhanced PWM Auto-Shutdown .............................. 184Full-Bridge Application

Example............................................................ 182Full-Bridge Mode....................................................... 181

Direction Change .............................................. 182Half-Bridge Mode ...................................................... 180Half-Bridge Output Mode

Applications Example ....................................... 180Output Configurations ............................................... 177Output Relationships

(Active-High State)............................................ 178

Output Relationships (Active-Low State) ............................................ 179

Programmable Dead-Band Delay............................. 184PWM Direction Change (diagram)............................ 183PWM Direction Change at Near 100%

Duty Cycle (diagram)........................................ 183Setup for Operation .................................................. 187Start-up Considerations............................................ 186

QQ Clock ..................................................................... 173, 177

RRAM. See Data Memory.RC Oscillator....................................................................... 24RCALL .............................................................................. 395RCON Register................................................................. 123RCSTA Register

SPEN Bit................................................................... 229Register File........................................................................ 59Register File Summary ................................................. 67–77Registers

ADCON0 (A/D Control 0).......................................... 249ADCON1 (A/D Control 1).......................................... 250ADCON2 (A/D Control 2).......................................... 251BAUDCON (Baud Rate Control)............................... 232BIE0 (Buffer Interrupt Enable 0) ............................... 322BnCON (TX/RX Buffer n Control,

Receive Mode) ................................................. 297BnCON (TX/RX Buffer n Control,

Transmit Mode) ................................................ 298BnDLC (TX/RX Buffer n Data Length

Code in Receive Mode) .................................... 304BnDLC (TX/RX Buffer n Data Length

Code in Transmit Mode) ................................... 305BnDm (TX/RX Buffer n Data Field Byte m

in Receive Mode).............................................. 303BnDm (TX/RX Buffer n Data Field Byte m

in Transmit Mode)............................................. 303BnEIDH (TX/RX Buffer n Extended

Identifier, High Byte in Receive Mode) ................................................. 301

BnEIDH (TX/RX Buffer n Extended Identifier, High Byte in Transmit Mode) ................................................ 301

BnEIDL (TX/RX Buffer n ExtendedIdentifier, Low Byte in Receive Mode) ................................................. 302

BnEIDL (TX/RX Buffer n Extended Identifier, Low Byte in Transmit Mode) ................................................ 302

BnSIDH (TX/RX Buffer n Standard Identifier, High Byte in Receive Mode) ................................................. 299

BnSIDH (TX/RX Buffer n StandardIdentifier, High Byte in Transmit Mode) ................................................ 299

BnSIDL (TX/RX Buffer n Standard Identifier, Low Byte in Receive Mode) ................................................. 300


PIC18F6585/8585/6680/8680

BnSIDL (TX/RX Buffer n Standard Identifier, Low Byte in Transmit Mode)................................................. 300

BRGCON1 (Baud Rate Control 1) ............................ 315BRGCON2 (Baud Rate Control 2) ............................ 316BRGCON3 (Baud Rate Control 3) ............................ 317BSEL0 (Buffer Select 0) ............................................ 305CANCON (CAN Control) ........................................... 278CANSTAT (CAN Status) ........................................... 279CCP1CON (CCP1 Control) ............................... 167, 175CCP2CON (CCP2 Control) ....................................... 168CIOCON (CAN I/O Control) ...................................... 318CMCON (Comparator Control) ................................. 259COMSTAT

(CAN Communication Status)........................... 284CONFIG1H (Configuration 1 High) ........................... 347CONFIG2H (Configuration 2 High) ........................... 349CONFIG2L (Configuration 2 Low)............................. 348CONFIG3H (Configuration 3 High) ........................... 350CONFIG3L (Configuration 3 Low)............................. 349CONFIG3L (Configuration Byte) ................................. 53CONFIG4L (Configuration 4 Low)............................. 350CONFIG5H (Configuration 5 High) ........................... 351CONFIG5L (Configuration 5 Low)............................. 351CONFIG6H (Configuration 6 High) ........................... 352CONFIG6L (Configuration 6 Low)............................. 352CONFIG7H (Configuration 7 High) ........................... 353CONFIG7L (Configuration 7 Low)............................. 353CVRCON (Comparator Voltage

Reference Control)............................................ 265Device ID 1 ............................................................... 354Device ID 2 ............................................................... 354ECANCON (Enhanced CAN Control) ....................... 283ECCP1AS (ECCP1 Auto-Shutdown

Control) ............................................................. 185ECCP1DEL (ECCP1 Delay) ..................................... 184EECON1 (Data EEPROM

Control 1) .................................................... 85, 102INTCON (Interrupt Control) ....................................... 111INTCON2 (Interrupt Control 2) .................................. 112INTCON3 (Interrupt Control 3) .................................. 113IPR1 (Peripheral Interrupt

Priority 1)........................................................... 120IPR2 (Peripheral Interrupt

Priority 2)........................................................... 121IPR3 (Peripheral Interrupt

Priority 3)................................................... 122, 321LVDCON (LVD Control) ............................................ 271MEMCON (Memory Control)....................................... 94OSCCON (Oscillator Control) ..................................... 27PIE1 (Peripheral Interrupt

Enable 1)........................................................... 117PIE2 (Peripheral Interrupt

Enable 2)........................................................... 118PIE3 (Peripheral Interrupt

Enable 3)................................................... 119, 320PIR1 (Peripheral Interrupt

Request 1) ........................................................ 114PIR2 (Peripheral Interrupt

Request 2) ........................................................ 115PIR3 (Peripheral Interrupt

Flag 3)............................................................... 319

PIR3 (Peripheral Interrupt Request 3) ........................................................ 116

PSPCON (Parallel Slave Port Control)............................................................. 153

RCON (Reset Control).................................. 35, 82, 123RCSTA (Receive Status and

Control)............................................................. 231RXB0CON (Receive Buffer 0

Control)............................................................. 291RXB1CON (Receive Buffer 1

Control)............................................................. 293RXBnDLC (Receive Buffer n

Data Length Code) ........................................... 295RXBnDm (Receive Buffer n

Data Field Byte m)............................................ 296RXBnEIDH (Receive Buffer n

Extended Identifier, High Byte)......................... 294RXBnEIDL (Receive Buffer n

Extended Identifier, Low Byte).......................... 295RXBnSIDH (Receive Buffer n

Standard Indentifier, High Byte) ....................... 294RXBnSIDL (Receive Buffer n

Standard Identifier, Low Byte) .......................... 294RXERRCNT (Receive Error Count).......................... 296RXFnEIDH (Receive Acceptance

Filter n Extended Identifier, High Byte)......................................................... 307

RXFnEIDL (Receive Acceptance Filter n Extended Identifier, Low Byte).......................................................... 307

RXFnSIDH (Receive Acceptance Filter n Standard Identifier Filter, High Byte)......................................................... 306

RXFnSIDL (Receive Acceptance Filter n Standard Identifier Filter, Low Byte).......................................................... 306

RXMnEIDH (Receive Acceptance Mask n Extended Identifier Mask, High Byte)......................................................... 308

RXMnEIDL (Receive Acceptance Mask n Extended Identifier Mask, Low Byte).......................................................... 308

RXMnSIDH (Receive Acceptance Mask n Standard Identifier Mask, High Byte)......................................................... 307

RXMnSIDL (Receive Acceptance Mask n Standard Identifier Mask, Low Byte).......................................................... 308

SSPCON1 (MSSP Control 1 in SPI Mode)..................................................... 191

SSPCON2 (MSSP Control 2 in I2C Mode) ..................................................... 201

SSPSTAT (MSSP Status in SPI Mode).................................................... 190

Status ......................................................................... 81STKPTR (Stack Pointer)............................................. 55T0CON (Timer0 Control) .......................................... 155T1CON (Timer 1 Control) ......................................... 159T2CON (Timer2 Control) .......................................... 162T3CON (Timer3 Control) .......................................... 164


PIC18F6585/8585/6680/8680

TXBIE (Transmit Buffers Interrupt Enable) ............................................... 322

TXBnCON (Transmit Buffer n Control) ............................................................. 285

TXBnDLC (Transmit Buffer n Data Length Code) ........................................... 288

TXBnDm (Transmit Buffer n Data Field Byte m) ............................................ 287

TXBnEIDH (Transmit Buffer n Extended Identifier, High Byte) ......................... 286

TXBnEIDL (Transmit Buffer n Extended Identifier, Low Byte) .......................... 287

TXBnSIDH (Transmit Buffer n Standard Identifier, High Byte).......................... 286

TXBnSIDL (Transmit Buffer n Standard Identifier, Low Byte) .......................... 286

TXERRCNT (Transmit Error Count) ......................... 288TXSTA (Transmit Status and

Control) ............................................................. 230WDTCON (Watchdog Timer

Control) ............................................................. 355RESET .............................................................................. 395Reset........................................................................... 33, 345Reset, Watchdog Timer, Oscillator

Start-up Timer, Power-up Timer and Brown-out Reset Requirements................................ 433

RETFIE ............................................................................. 396RETLW ............................................................................. 396RETURN ........................................................................... 397Return Address Stack

and Associated Registers ........................................... 55Stack Pointer (STKPTR) ............................................. 54Top-of-Stack Access................................................... 54

Revision History ................................................................ 469RLCF................................................................................. 397RLNCF .............................................................................. 398RRCF ................................................................................ 398RRNCF ............................................................................. 399

SSCK................................................................................... 189SDI .................................................................................... 189SDO .................................................................................. 189Serial Clock, SCK ............................................................. 189Serial Data In, SDI ............................................................ 189Serial Data Out, SDO........................................................ 189Serial Peripheral Interface. See SPI.SETF................................................................................. 399Slave Select, SS ............................................................... 189SLEEP .............................................................................. 400Sleep......................................................................... 345, 357Software Simulator

(MPLAB SIM) ............................................................ 408Software Simulator

(MPLAB SIM30) ........................................................ 408Special Event Trigger. See Compare.Special Features of the CPU ............................................ 345

Configuration Registers .................................... 347–353Special Function Registers ................................................. 59

Map ............................................................................. 61

SPISerial Clock .............................................................. 189Serial Data In............................................................ 189Serial Data Out ......................................................... 189Slave Select.............................................................. 189SPI Mode.................................................................. 189

SPI Master/Slave Connection........................................... 193SPI Mode

Master/Slave Connection ......................................... 193SS..................................................................................... 189SSP

TMR2 Output for Clock Shift............................. 162, 163SSPOV Status Flag .......................................................... 219SSPSTAT Register

R/W Bit ............................................................. 202, 203Status Bits

Significance and Initialization Condition for RCON Register ............................. 35

SUBFWP .......................................................................... 400SUBLW............................................................................. 401SUBWF............................................................................. 401SUBWFB .......................................................................... 402SWAPF............................................................................. 402

TTable Pointer Operations

(table) ......................................................................... 86TBLRD.............................................................................. 403TBLWT ............................................................................. 404Time-out in Various

Situations.................................................................... 35Time-out Sequence ............................................................ 34Timer0 .............................................................................. 155

16-bit Mode Timer Reads and Writes ............................................................... 157

Associated Registers................................................ 157Clock Source Edge Select

(T0SE Bit) ......................................................... 157Clock Source Select

(T0CS Bit)......................................................... 157Operation.................................................................. 157Overflow Interrupt ..................................................... 157Prescaler .................................................................. 157

Switching Assignment ...................................... 157Prescaler. See Prescaler, Timer0.

Timer0 and Timer1 External Clock Requirements ........................................................... 434

Timer1 .............................................................................. 15916-bit Read/Write Mode............................................ 161Associated Registers................................................ 161Operation.................................................................. 160Oscillator........................................................... 159, 161Overflow Interrupt ............................................. 159, 161Special Event Trigger

(CCP)........................................................ 161, 171TMR1H Register....................................................... 159TMR1L Register ....................................................... 159


PIC18F6585/8585/6680/8680

Timer2 ............................................................................... 162Associated Registers ................................................ 163Operation .................................................................. 162Postscaler. See Postscaler, Timer2.PR2 Register............................................. 162, 173, 177Prescaler. See Prescaler, Timer2.SSP Clock Shift................................................. 162, 163TMR2 Register .......................................................... 162TMR2 to PR2 Match

Interrupt..................................... 162, 163, 173, 177Timer3 ............................................................................... 164

Associated Registers ................................................ 166Operation .................................................................. 165Oscillator ........................................................... 164, 166Overflow Interrupt ............................................. 164, 166Special Event Trigger

(CCP) ................................................................ 166TMR3H Register ....................................................... 164TMR3L Register ........................................................ 164

Timing DiagramsA/D Conversion......................................................... 447Acknowledge Sequence ........................................... 222Asynchronous Reception .......................................... 241Asynchronous Transmission..................................... 238Asynchronous Transmission

(Back to Back)................................................... 238Automatic Baud Rate

Calculation ........................................................ 236Auto-Wake-up Bit (WUE) During

Normal Operation.............................................. 242Auto-Wake-up Bit (WUE)

During Sleep ..................................................... 242Baud Rate Generator with

Clock Arbitration................................................ 216BRG Reset Due to SDA Arbitration During

Start Condition .................................................. 225Brown-out Reset (BOR) ............................................ 433Bus Collision During a Repeated

Start Condition (Case 1) ................................... 226Bus Collision During a Repeated

Start Condition (Case 2) ................................... 226Bus Collision During a Stop Condition

(Case 1) ............................................................ 227Bus Collision During a Stop Condition

(Case 2) ............................................................ 227Bus Collision During Start Condition

(SCL = 0) .......................................................... 225Bus Collision During Start Condition

(SDA only)......................................................... 224Bus Collision for Transmit and

Acknowledge.................................................... 223Capture/Compare/PWM

(All CCP Modules) ............................................ 435CLKO and I/O ........................................................... 429Clock Synchronization .............................................. 209Clock/Instruction Cycle ............................................... 56Example SPI Master Mode

(CKE = 0) .......................................................... 437Example SPI Master Mode

(CKE = 1) .......................................................... 438

Example SPI Slave Mode (CKE = 0).......................................................... 439

Example SPI Slave Mode (CKE = 1).......................................................... 440

External Clock (All Modes except PLL) ...................................................... 428

External Program Memory Bus (16-bit Mode) ...................................................... 99

First Start Bit ............................................................. 217Full-Bridge PWM Output........................................... 181Half-Bridge PWM Output .......................................... 180I2C Bus Data............................................................. 441I2C Bus Start/Stop Bits ............................................. 441I2C Master Mode (7 or

10-bit Transmission) ......................................... 220I2C Master Mode

(7-bit Reception) ............................................... 221I2C Slave Mode (10-bit Reception,

SEN = 0) ........................................................... 206I2C Slave Mode (10-bit Reception,

SEN = 1) ........................................................... 211I2C Slave Mode

(10-bit Transmission)........................................ 207I2C Slave Mode (7-bit Reception,

SEN = 0) ........................................................... 204I2C Slave Mode (7-bit Reception,

SEN = 1) ........................................................... 210I2C Slave Mode

(7-bit Transmission).......................................... 205Low-Voltage Detect .................................................. 272Master SSP I2C Bus Data......................................... 443Master SSP I2C Bus

Start/Stop Bits................................................... 443Parallel Slave Port

(PIC18FXX8X).................................................. 436Parallel Slave Port (PSP)

Read ................................................................. 154Parallel Slave Port (PSP)

Write ................................................................. 153Program Memory Read ............................................ 430Program Memory Write............................................. 431PWM Auto-Shutdown (PRSEN = 0,

Auto-Restart Disabled) ..................................... 186PWM Auto-Shutdown (PRSEN = 1,

Auto-Restart Enabled) ...................................... 186PWM Output ............................................................. 173Repeat Start Condition ............................................. 218Reset, Watchdog Timer (WDT),

Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) ........................... 432

Send Break Character Sequence............................. 243Slave Mode General Call Address

Sequence (7 or 10-bit Address Mode) ................................................. 212

Slave Synchronization .............................................. 195Slow Rise Time (MCLR Tied to VDD

via 1 kΩ Resistor) ............................................... 50SPI Mode (Master Mode).......................................... 194SPI Mode (Slave Mode with

CKE = 0) ........................................................... 196


PIC18F6585/8585/6680/8680

SPI Mode (Slave Mode with CKE = 1) ........................................................... 196

Stop Condition Receive or Transmit Mode.................................................. 222

Synchronous Reception (Master Mode, SREN) ...................................... 246

Synchronous Transmission....................................... 244Synchronous Transmission

(Through TXEN) ............................................... 245Time-out Sequence on POR w/PLL

Enabled (MCLR Tied to VDD via 1 kΩ Resistor) ............................................... 50

Time-out Sequence on Power-up (MCLR Not Tied to VDD)Case 1 ................................................................ 49Case 2 ................................................................ 49

Time-out Sequence on Power-up (MCLR Tied to VDD via 1 kΩ Resistor) ............................................... 49

Timer0 and Timer1 External Clock ........................... 433Transition Between Timer1 and OSC1

(EC with PLL Active, SCS1 = 1) ......................... 29Transition Between Timer1 and OSC1

(HS with PLL Active, SCS1 = 1) ......................... 29Transition Between Timer1 and OSC1

(HS, XT, LP) ....................................................... 28Transition Between Timer1 and

OSC1 (RC, EC) .................................................. 30Transition from OSC1 to

Timer1 Oscillator................................................. 28USART Synchronous Receive

(Master/Slave) .................................................. 445USART Synchronous Transmission

(Master/Slave) .................................................. 445Wake-up from Sleep via Interrupt ............................. 358

TRISE RegisterPSPMODE Bit................................................... 133, 152

TSTFSZ ............................................................................ 405Two-Word Instructions

Example Cases........................................................... 58TXSTA Register

BRGH Bit .................................................................. 233

UUSART

Asynchronous Mode ................................................. 23712-bit Break Transmit and

Receive..................................................... 243Associated Registers, Receive ......................... 241Associated Registers, Transmit ........................ 239Auto-Wake-up on Sync Break .......................... 242Receiver............................................................ 240Setting up 9-bit Mode with

Address Detect ......................................... 240Transmitter........................................................ 237

Baud Rate Generator (BRG) .................................... 233Associated Registers........................................ 233Auto-Baud Rate Detect..................................... 236Baud Rate Error, Calculating............................ 233Baud Rates, Asynchronous

Modes....................................................... 234High Baud Rate Select

(BRGH Bit) ............................................... 233Sampling .......................................................... 233

Serial Port Enable (SPEN Bit) .................................. 229Synchronous Master Mode....................................... 244

Associated Registers, Reception ................................................. 246

Associated Registers, Transmit ................................................... 245

Reception ......................................................... 246Transmission .................................................... 244

Synchronous Slave Mode......................................... 247Associated Registers,

Receive .................................................... 248Associated Registers,

Transmit ................................................... 247Reception ......................................................... 248Transmission .................................................... 247

USART Synchronous Receive Requirements ........................................................... 445

USART Synchronous Transmission Requirements ........................................................... 445

VVoltage Reference Specifications..................................... 423

WWake-up from Sleep ................................................. 345, 357

Using Interrupts ........................................................ 357Watchdog Timer (WDT)............................................ 345, 355

Associated Registers................................................ 356Control Register........................................................ 355Postscaler......................................................... 355, 356Programming Considerations ................................... 355RC Oscillator ............................................................ 355Time-out Period ........................................................ 355

WCOL............................................................................... 217WCOL Status Flag.................................... 217, 218, 219, 222WWW, On-Line Support ....................................................... 7

XXORLW ............................................................................ 405XORWF ............................................................................ 406


PIC18F6585/8585/6680/8680

NOTES:


PIC18F6585/8585/6680/8680

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PIC18F6585/8585/6680/8680

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DS30491CPIC18F6585/8585/6680/8680

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PIC18F6585/8585/6680/8680

PIC18F6585/8585/6680/8680 PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. – X /XX XXX

PatternPackageTemperatureRange

Device

Device PIC18FXX8X(1), PIC18FXX8XT(2);

VDD range 4.2V to 5.5VPIC18LFXX8X(1), PIC18LFXX8XT(2);

VDD range 2.0V to 5.5V

Temperature Range

I = -40°C to +85°C (Industrial)E = -40°C to +125°C (Extended)

Package PT = TQFP (Thin Quad Flatpack)

Pattern QTP, SQTP, Code or Special Requirements (blank otherwise)

Examples:

a) PIC18LF6680 - I/PT 301 = Industrial temp., TQFP package, Extended VDD limits, QTP pattern #301.

b) PIC18F8585 - I/PT = Industrial temp., TQFP package, normal VDD limits.

c) PIC18F8680 - E/PT = Extended temp., TQFP package, standard VDD limits.

Note 1: F = Standard Voltage RangeLF = Extended Voltage Range

2: T = in tape and reel


PIC18F6585/8585/6680/8680

NOTES:


AMERICASCorporate Office2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 480-792-7200 Fax: 480-792-7277Technical Support: 480-792-7627Web Address: http://www.microchip.com

Atlanta3780 Mansell Road, Suite 130Alpharetta, GA 30022Tel: 770-640-0034 Fax: 770-640-0307

Boston2 Lan Drive, Suite 120Westford, MA 01886Tel: 978-692-3848 Fax: 978-692-3821

Chicago333 Pierce Road, Suite 180Itasca, IL 60143Tel: 630-285-0071 Fax: 630-285-0075

Dallas4570 Westgrove Drive, Suite 160Addison, TX 75001Tel: 972-818-7423 Fax: 972-818-2924

DetroitTri-Atria Office Building 32255 Northwestern Highway, Suite 190Farmington Hills, MI 48334Tel: 248-538-2250Fax: 248-538-2260

Kokomo2767 S. Albright Road Kokomo, IN 46902Tel: 765-864-8360Fax: 765-864-8387

Los Angeles18201 Von Karman, Suite 1090Irvine, CA 92612Tel: 949-263-1888 Fax: 949-263-1338

San Jose1300 Terra Bella AvenueMountain View, CA 94043Tel: 650-215-1444Fax: 650-961-0286

Toronto6285 Northam Drive, Suite 108Mississauga, Ontario L4V 1X5, CanadaTel: 905-673-0699 Fax: 905-673-6509

ASIA/PACIFICAustraliaSuite 22, 41 Rawson StreetEpping 2121, NSWAustraliaTel: 61-2-9868-6733 Fax: 61-2-9868-6755

China - BeijingUnit 706BWan Tai Bei Hai Bldg.No. 6 Chaoyangmen Bei Str. Beijing, 100027, ChinaTel: 86-10-85282100 Fax: 86-10-85282104China - ChengduRm. 2401-2402, 24th Floor, Ming Xing Financial TowerNo. 88 TIDU StreetChengdu 610016, ChinaTel: 86-28-86766200 Fax: 86-28-86766599China - FuzhouUnit 28F, World Trade PlazaNo. 71 Wusi RoadFuzhou 350001, ChinaTel: 86-591-7503506 Fax: 86-591-7503521China - Hong Kong SARUnit 901-6, Tower 2, Metroplaza223 Hing Fong RoadKwai Fong, N.T., Hong KongTel: 852-2401-1200 Fax: 852-2401-3431China - ShanghaiRoom 701, Bldg. BFar East International PlazaNo. 317 Xian Xia RoadShanghai, 200051Tel: 86-21-6275-5700 Fax: 86-21-6275-5060China - ShenzhenRm. 1812, 18/F, Building A, United PlazaNo. 5022 Binhe Road, Futian DistrictShenzhen 518033, ChinaTel: 86-755-82901380 Fax: 86-755-8295-1393China - ShundeRoom 401, Hongjian Building, No. 2 Fengxiangnan Road, Ronggui Town, ShundeDistrict, Foshan City, Guangdong 528303, ChinaTel: 86-757-28395507 Fax: 86-757-28395571China - QingdaoRm. B505A, Fullhope Plaza,No. 12 Hong Kong Central Rd.Qingdao 266071, ChinaTel: 86-532-5027355 Fax: 86-532-5027205IndiaDivyasree Chambers1 Floor, Wing A (A3/A4)No. 11, O’Shaugnessey RoadBangalore, 560 025, IndiaTel: 91-80-22290061 Fax: 91-80-22290062JapanBenex S-1 6F3-18-20, ShinyokohamaKohoku-Ku, Yokohama-shiKanagawa, 222-0033, JapanTel: 81-45-471- 6166 Fax: 81-45-471-6122

Korea168-1, Youngbo Bldg. 3 FloorSamsung-Dong, Kangnam-KuSeoul, Korea 135-882Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934Singapore200 Middle Road#07-02 Prime CentreSingapore, 188980Tel: 65-6334-8870 Fax: 65-6334-8850TaiwanKaohsiung Branch30F - 1 No. 8Min Chuan 2nd RoadKaohsiung 806, TaiwanTel: 886-7-536-4818Fax: 886-7-536-4803TaiwanTaiwan Branch11F-3, No. 207Tung Hua North RoadTaipei, 105, TaiwanTel: 886-2-2717-7175 Fax: 886-2-2545-0139

EUROPEAustriaDurisolstrasse 2A-4600 WelsAustriaTel: 43-7242-2244-399Fax: 43-7242-2244-393DenmarkRegus Business CentreLautrup hoj 1-3Ballerup DK-2750 DenmarkTel: 45-4420-9895 Fax: 45-4420-9910FranceParc d’Activite du Moulin de Massy43 Rue du Saule TrapuBatiment A - ler Etage91300 Massy, FranceTel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79GermanySteinheilstrasse 10D-85737 Ismaning, GermanyTel: 49-89-627-144-0 Fax: 49-89-627-144-44ItalyVia Quasimodo, 1220025 Legnano (MI)Milan, Italy Tel: 39-0331-742611 Fax: 39-0331-466781NetherlandsP. A. De Biesbosch 14NL-5152 SC Drunen, NetherlandsTel: 31-416-690399 Fax: 31-416-690340United Kingdom505 Eskdale RoadWinnersh TriangleWokingham Berkshire, England RG41 5TUTel: 44-118-921-5869Fax: 44-118-921-5820

02/17/04

WORLDWIDE SALES AND SERVICE


PIC18F6585/8585/6680/8680 Data Sheet

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