PIC18F4550

2009 Microchip Technology Inc. DS39632E

PIC18F2455/2550/4455/4550Data Sheet

28/40/44-Pin, High-Performance,Enhanced Flash, USB Microcontrollers

with nanoWatt Technology

Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

There are dishonest and possibly illegal methods used to breacher ou of in

rned

r cane.

mitteay b

workInformation contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyers risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,

knowledge, require using the Microchip products in a mannSheets. Most likely, the person doing so is engaged in theft

Microchip is willing to work with the customer who is conce

Neither Microchip nor any other semiconductor manufacturemean that we are guaranteeing the product as unbreakabl

Code protection is constantly evolving. We at Microchip are comproducts. Attempts to break Microchips code protection feature mallow unauthorized access to your software or other copyrightedDS39632E-page ii

suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified

the code protection feature. All of these methods, to our tside the operating specifications contained in Microchips Data tellectual property.

about the integrity of their code.

guarantee the security of their code. Code protection does not

d to continuously improving the code protection features of oure a violation of the Digital Millennium Copyright Act. If such acts, you may have a right to sue for relief under that Act. 2009 Microchip Technology Inc.

logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Companys quality system processes and procedures are for its PIC MCUs and dsPIC DSCs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchips quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

PIC18F2455/2550/4455/4550

Universal Serial Bus Features: USB V2.0 Compliant Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s) Supports Control, Interrupt, Isochronous and Bulk

Transfers Supports up to 32 Endpoints (16 bidirectional) 1 Kbyte Dual Access RAM for USB On-Chip USB Transceiver with On-Chip Voltage

Regulator Interface for Off-Chip USB Transceiver Streaming Parallel Port (SPP) for USB streaming

transfers (40/44-pin devices only)

Power-Managed Modes: Run: CPU on, Peripherals on Idle: CPU off, Peripherals on Sleep: CPU off, Peripherals off Idle mode Currents Down to 5.8 A Typical Sleep mode Currents Down to 0.1 A Typical Timer1 Oscillator: 1.1 A Typical, 32 kHz, 2V Watchdog Timer: 2.1 A Typical Two-Speed Oscillator Start-up

Flexible Oscillator Structure: Four Crystal modes, including High-Precision PLL

for USB Two External Clock modes, Up to 48 MHz Internal Oscillator Block:

- 8 user-selectable frequencies, from 31 kHz to 8 MHz

- User-tunable to compensate for frequency drift Secondary Oscillator using Timer1 @ 32 kHz Dual Oscillator Options allow Microcontroller and

USB module to Run at Different Clock Speeds Fail-Safe Clock Monitor:

- Allows for safe shutdown if any clock stops

Peripheral Highlights: High-Current Sink/Source: 25 mA/25 mA Three External Interrupts Four Timer modules (Timer0 to Timer3) Up to 2 Capture/Compare/PWM (CCP) modules:

- Capture is 16-bit, max. resolution 5.2 ns (TCY/16)- Compare is 16-bit, max. resolution 83.3 ns (TCY)- PWM output: PWM resolution is 1 to 10-bit

Enhanced Capture/Compare/PWM (ECCP) module:- Multiple output modes - Selectable polarity- Programmable dead time- Auto-shutdown and auto-restart

Enhanced USART module:- LIN bus support

Master Synchronous Serial Port (MSSP) module Supporting 3-Wire SPI (all 4 modes) and I2C Master and Slave modes

10-Bit, Up to 13-Channel Analog-to-Digital Converter (A/D) module with Programmable Acquisition Time

Dual Analog Comparators with Input Multiplexing

Special Microcontroller Features: C Compiler Optimized Architecture with Optional

Extended Instruction Set 100,000 Erase/Write Cycle Enhanced Flash

Program Memory Typical 1,000,000 Erase/Write Cycle Data EEPROM

Memory Typical Flash/Data EEPROM Retention: > 40 Years Self-Programmable under Software Control Priority Levels for Interrupts 8 x 8 Single-Cycle Hardware Multiplier Extended Watchdog Timer (WDT):

- Programmable period from 41 ms to 131s Programmable Code Protection Single-Supply 5V In-Circuit Serial

Programming (ICSP) via Two Pins In-Circuit Debug (ICD) via Two Pins Optional Dedicated ICD/ICSP Port (44-pin, TQFP

package only)

28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology 2009 Microchip Technology Inc. DS39632E-page 1

Wide Operating Voltage Range (2.0V to 5.5V)

Device

Program Memory Data Memory

I/O 10-Bit A/D (ch)CCP/ECCP

(PWM) SPP

MSSP

EUSA

RT

Com

para

tors

Timers8/16-BitFlash

(bytes)# Single-WordInstructions

SRAM(bytes)

EEPROM(bytes) SPI

MasterI2C

PIC18F2455 24K 12288 2048 256 24 10 2/0 No Y Y 1 2 1/3PIC18F2550 32K 16384 2048 256 24 10 2/0 No Y Y 1 2 1/3PIC18F4455 24K 12288 2048 256 35 13 1/1 Yes Y Y 1 2 1/3PIC18F4550 32K 16384 2048 256 35 13 1/1 Yes Y Y 1 2 1/3

PIC18F2455/2550/4455/4550

Pin Diagrams

40-Pin PDIP

PIC

18F2

455

28-Pin PDIP, SOIC

PIC

18F2

550

1011

23456

1

87

9

121314 15

1617181920

232425262728

2221

MCLR/VPP/RE3RA0/AN0RA1/AN1

RA2/AN2/VREF-/CVREFRA3/AN3/VREF+

RA4/T0CKI/C1OUT/RCVRA5/AN4/SS/HLVDIN/C2OUT

VSSOSC1/CLKI

OSC2/CLKO/RA6RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2(1)/UOERC2/CCP1

VUSB

RB7/KBI3/PGDRB6/KBI2/PGCRB5/KBI1/PGMRB4/AN11/KBI0RB3/AN9/CCP2(1)/VPORB2/AN8/INT2/VMORB1/AN10/INT1/SCK/SCLRB0/AN12/INT0/FLT0/SDI/SDAVDDVSSRC7/RX/DT/SDORC6/TX/CKRC5/D+/VPRC4/D-/VM

RB7/KBI3/PGDRB6/KBI2/PGCRB5/KBI1/PGMRB4/AN11/KBI0/CSSPPRB3/AN9/CCP2(1)/VPORB2/AN8/INT2/VMORB1/AN10/INT1/SCK/SCLRB0/AN12/INT0/FLT0/SDI/SDAVDDVSSRD7/SPP7/P1DRD6/SPP6/P1CRD5/SPP5/P1BRD4/SPP4RC7/RX/DT/SDORC6/TX/CKRC5/D+/VPRC4/D-/VMRD3/SPP3RD2/SPP2

MCLR/VPP/RE3RA0/AN0RA1/AN1

RA2/AN2/VREF-/CVREFRA3/AN3/VREF+


RE0/AN5/CK1SPPRE1/AN6/CK2SPPRE2/AN7/OESPP

VDDVSS

OSC1/CLKIOSC2/CLKO/RA6

RC0/T1OSO/T13CKIRC1/T1OSI/CCP2(1)/UOE

RC2/CCP1/P1AVUSB

RD0/SPP0RD1/SPP1

1234567891011121314151617181920

4039383736353433323130292827262524232221

PIC

18F4

455

PIC

18F4

550

Note 1: RB3 is the alternate pin for CCP2 multiplexing.DS39632E-page 2 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

Pin Diagrams (Continued)

PIC18F4455

44-Pin TQFP

44-Pin QFN

PIC18F4455

PIC18F4550

PIC18F4550

1011

23

6

1

18 19 20 21 2212 13 14 15

38

87

44 43 42 41 40 3916 17

2930313233

232425262728

36 3435

9

37

RA

3/A

N3/

VRE

F+R

A2/A

N2/

VREF

-/CVR

EFR

A1/

AN

1R

A0/

AN

0M

CLR

/VP

P/R

E3

NC

/ICC

K(2

) /IC

PG

C(2

)

RB

7/KB

I3/P

GD

RB

6/KB

I2/P

GC

RB5

/KB

I1/P

GM

RB4

/AN

11/K

BI0/

CSS

PPN

C/IC

DT(

2)/IC

PG

D(2

)R

C6/

TX/C

KR

C5/

D+/

VP

RC

4/D

-/VM

RD

3/S

PP

3R

D2/

SP

P2

RD

1/S

PP

1R

D0/

SP

P0

V US

BR

C2/

CC

P1/

P1A

RC

1/T1

OSI

/CC

P2(1

) /UO

EN

C/IC

PO

RTS

(2)

NC/ICRST(2)/ICVPP(2)RC0/T1OSO/T13CKIOSC2/CLKO/RA6OSC1/CLKIVSSVDDRE2/AN7/OESPPRE1/AN6/CK2SPPRE0/AN5/CK1SPPRA5/AN4/SS/HLVDIN/C2OUTRA4/T0CKI/C1OUT/RCV

RC7/RX/DT/SDORD4/SPP4

RD5/SPP5/P1BRD6/SPP6/P1C

VSSVDD

RB0/AN12/INT0/FLT0/SDI/SDARB1/AN10/INT1/SCK/SCL

RB2/AN8/INT2/VMORB3/AN9/CCP2(1)/VPO

RD7/SPP7/P1D 54

1011

23

6

1

18 19 20 21 2212 13 14 15

38

87

44 43 42 41 40 3916 17

2930313233

232425262728

36 3435

9

37

RA3

/AN

3/V R

EF+

RA2

/AN

2/VR

EF-/C

VREF

RA

1/A

N1

RA

0/A

N0

MC

LR/V

PP/R

E3

RB

7/K

BI3/

PG

DR

B6/

KBI

2/P

GC

RB

5/K

BI1

/PG

MR

B4/A

N11

/KBI

0/C

SSPPN

CR

C6/

TX/C

KR

C5/

D+/

VP

RC

4/D

-/VM

RD

3/S

PP

3R

D2/

SP

P2

RD

1/S

PP

1R

D0/

SP

P0

V US

BR

C2/

CC

P1/P

1AR

C1/

T1O

SI/C

CP2

(1) /U

OE

RC

0/T1

OS

O/T

13C

KI

OSC2/CLKO/RA6OSC1/CLKIVSS

VDDRE2/AN7/OESPPRE1/AN6/CK2SPPRE0/AN5/CK1SPPRA5/AN4/SS/HLVDIN/C2OUTRA4/T0CKI/C1OUT/RCV

RC7/RX/DT/SDORD4/SPP4

RD5/SPP5/P1BRD6/SPP6/P1C

VSS

VDDRB0/AN12/INT0/FLT0/SDI/SDA

RB1/AN10/INT1/SCK/SCLRB2/AN8/INT2/VMO

RB3

/AN

9/C

CP2

(1) /V

PO

RD7/SPP7/P1D 54 VSS

VDD

VDD

Note 1: RB3 is the alternate pin for CCP2 multiplexing.2: Special ICPORT features available in select circumstances. See Section 25.9 Special ICPORT Features (44-Pin TQFP

Package Only) for more information. 2009 Microchip Technology Inc. DS39632E-page 3

PIC18F2455/2550/4455/4550

Table of Contents1.0 Device Overview .......................................................................................................................................................................... 72.0 Oscillator Configurations ............................................................................................................................................................ 233.0 Power-Managed Modes ............................................................................................................................................................. 354.0 Reset .......................................................................................................................................................................................... 455.0 Memory Organization ................................................................................................................................................................. 596.0 Flash Program Memory.............................................................................................................................................................. 817.0 Data EEPROM Memory ............................................................................................................................................................. 918.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 979.0 Interrupts .................................................................................................................................................................................... 9910.0 I/O Ports ................................................................................................................................................................................... 11311.0 Timer0 Module ......................................................................................................................................................................... 12712.0 Timer1 Module ......................................................................................................................................................................... 13113.0 Timer2 Module ......................................................................................................................................................................... 13714.0 Timer3 Module ......................................................................................................................................................................... 13915.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 14316.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 15117.0 Universal Serial Bus (USB) ...................................................................................................................................................... 16518.0 Streaming Parallel Port ............................................................................................................................................................ 19119.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 19720.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 24321.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 26522.0 Comparator Module.................................................................................................................................................................. 27523.0 Comparator Voltage Reference Module................................................................................................................................... 28124.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 28525.0 Special Features of the CPU.................................................................................................................................................... 29126.0 Instruction Set Summary .......................................................................................................................................................... 31327.0 Development Support............................................................................................................................................................... 36328.0 Electrical Characteristics .......................................................................................................................................................... 36729.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 40730.0 Packaging Information.............................................................................................................................................................. 409Appendix A: Revision History............................................................................................................................................................. 419Appendix B: Device Differences......................................................................................................................................................... 419Appendix C: Conversion Considerations ........................................................................................................................................... 420Appendix D: Migration From Baseline to Enhanced Devices............................................................................................................. 420Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 421Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 421Index .................................................................................................................................................................................................. 423The Microchip Web Site ..................................................................................................................................................................... 433Customer Change Notification Service .............................................................................................................................................. 433Customer Support .............................................................................................................................................................................. 433Reader Response .............................................................................................................................................................................. 434PIC18F2455/2550/4455/4550 Product Identification System ............................................................................................................ 435DS39632E-page 4 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550TO OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchipproducts. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department viaE-mail at [email protected] or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. Wewelcome your feedback.

Most Current Data SheetTo obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.comYou can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for currentdevices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revisionof silicon and revision of document to which it applies.To determine if an errata sheet exists for a particular device, please check with one of the following: Microchips Worldwide Web site; http://www.microchip.com Your local Microchip sales office (see last page)When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you areusing.

Customer Notification SystemRegister on our web site at www.microchip.com to receive the most current information on all of our products. 2009 Microchip Technology Inc. DS39632E-page 5

PIC18F2455/2550/4455/4550

NOTES:DS39632E-page 6 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/45501.0 DEVICE OVERVIEWThis document contains device-specific information forthe following devices:

This family of devices offers the advantages of allPIC18 microcontrollers namely, high computationalperformance at an economical price with the additionof high-endurance, Enhanced Flash programmemory. In addition to these features, thePIC18F2455/2550/4455/4550 family introduces designenhancements that make these microcontrollers a log-ical choice for many high-performance, power sensitiveapplications.

1.1 New Core Features

1.1.1 nanoWatt TECHNOLOGYAll of the devices in the PIC18F2455/2550/4455/4550family incorporate a range of features that can signifi-cantly reduce power consumption during operation.Key items include:

Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%.

Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further, to as little as 4%, of normal operation requirements.

On-the-Fly Mode Switching: The power-managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their applications software design.

Low Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer are minimized. See Section 28.0 Electrical Characteristics for values.

1.1.2 UNIVERSAL SERIAL BUS (USB)Devices in the PIC18F2455/2550/4455/4550 familyincorporate a fully featured Universal Serial Buscommunications module that is compliant with the USBSpecification Revision 2.0. The module supports bothlow-speed and full-speed communication for all sup-ported data transfer types. It also incorporates its ownon-chip transceiver and 3.3V regulator and supportsthe use of external transceivers and voltage regulators.

1.1.3 MULTIPLE OSCILLATOR OPTIONS AND FEATURES

All of the devices in the PIC18F2455/2550/4455/4550family offer twelve different oscillator options, allowingusers a wide range of choices in developing applicationhardware. These include:

Four Crystal modes using crystals or ceramic resonators.

Four External Clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general I/O).

An internal oscillator block which provides an 8 MHz clock (2% accuracy) and an INTRC source (approximately 31 kHz, stable over temperature and VDD), as well as a range of 6 user-selectable clock frequencies, between 125 kHz to 4 MHz, for a total of 8 clock frequencies. This option frees an oscillator pin for use as an additional general purpose I/O.

A Phase Lock Loop (PLL) frequency multiplier, available to both the High-Speed Crystal and External Oscillator modes, which allows a wide range of clock speeds from 4 MHz to 48 MHz.

Asynchronous dual clock operation, allowing the USB module to run from a high-frequency oscillator while the rest of the microcontroller is clocked from an internal low-power oscillator.

Besides its availability as a clock source, the internaloscillator block provides a stable reference source thatgives the family additional features for robustoperation:

Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued low-speed operation or a safe application shutdown.

Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available.

PIC18F2455 PIC18LF2455 PIC18F2550 PIC18LF2550 PIC18F4455 PIC18LF4455 PIC18F4550 PIC18LF4550 2009 Microchip Technology Inc. DS39632E-page 7

PIC18F2455/2550/4455/4550

1.2 Other Special Features Memory Endurance: The Enhanced Flash cells

for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years.

Self-Programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine, located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field.

Extended Instruction Set: The PIC18F2455/2550/4455/4550 family introduces an optional extension to the PIC18 instruction set, which adds 8 new instructions and an Indexed Literal Offset Addressing mode. This extension, enabled as a device configuration option, has been specifically designed to optimize re-entrant application code originally developed in high-level languages such as C.

Enhanced CCP Module: In PWM mode, this module provides 1, 2 or 4 modulated outputs for controlling half-bridge and full-bridge drivers. Other features include auto-shutdown for disabling PWM outputs on interrupt or other select conditions, and auto-restart to reactivate outputs once the condition has cleared.

Enhanced Addressable USART: This serial communication module is capable of standard RS-232 operation and provides support for the LIN bus protocol. The TX/CK and RX/DT signals can be inverted, eliminating the need for inverting buffers. Other enhancements include Automatic Baud Rate Detection and a 16-bit Baud Rate Generator for improved resolution. When the microcontroller is using the internal oscillator block, the EUSART provides stable operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement).

10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated, without waiting for a sampling period and thus, reducing code overhead.

Dedicated ICD/ICSP Port: These devices introduce the use of debugger and programming pins that are not multiplexed with other micro-controller features. Offered as an option in select packages, this feature allows users to develop I/O intensive applications while retaining the ability to program and debug in the circuit.

1.3 Details on Individual Family Members

Devices in the PIC18F2455/2550/4455/4550 family areavailable in 28-pin and 40/44-pin packages. Blockdiagrams for the two groups are shown in Figure 1-1and Figure 1-2.

The devices are differentiated from each other in sixways:

1. Flash program memory (24 Kbytes forPIC18FX455 devices, 32 Kbytes forPIC18FX550 devices).

2. A/D channels (10 for 28-pin devices, 13 for40/44-pin devices).

3. I/O ports (3 bidirectional ports and 1 input onlyport on 28-pin devices, 5 bidirectional ports on40/44-pin devices).

4. CCP and Enhanced CCP implementation(28-pin devices have two standard CCPmodules, 40/44-pin devices have one standardCCP module and one ECCP module).

5. Streaming Parallel Port (present only on40/44-pin devices).

All other features for devices in this family are identical.These are summarized in Table 1-1.

The pinouts for all devices are listed in Table 1-2 andTable 1-3.

Like all Microchip PIC18 devices, members of thePIC18F2455/2550/4455/4550 family are available asboth standard and low-voltage devices. Standarddevices with Enhanced Flash memory, designated withan F in the part number (such as PIC18F2550),accommodate an operating VDD range of 4.2V to 5.5V.Low-voltage parts, designated by LF (such asPIC18LF2550), function over an extended VDD rangeof 2.0V to 5.5V. DS39632E-page 8 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

TABLE 1-1: DEVICE FEATURES

Features PIC18F2455 PIC18F2550 PIC18F4455 PIC18F4550

Operating Frequency DC 48 MHz DC 48 MHz DC 48 MHz DC 48 MHzProgram Memory (Bytes) 24576 32768 24576 32768Program Memory (Instructions) 12288 16384 12288 16384Data Memory (Bytes) 2048 2048 2048 2048Data EEPROM Memory (Bytes) 256 256 256 256Interrupt Sources 19 19 20 20I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, ETimers 4 4 4 4Capture/Compare/PWM Modules 2 2 1 1Enhanced Capture/Compare/PWM Modules

0 0 1 1

Serial Communications MSSP, Enhanced USART

MSSP, Enhanced USART



Universal Serial Bus (USB)Module

1 1 1 1

Streaming Parallel Port (SPP) No No Yes Yes10-Bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input ChannelsComparators 2 2 2 2Resets (and Delays) POR, BOR,

RESET Instruction, Stack Full,

Stack Underflow (PWRT, OST),

MCLR (optional),WDT

POR, BOR, RESET Instruction,

Stack Full, Stack Underflow (PWRT, OST),

MCLR (optional),WDT



MCLR (optional),WDT



MCLR (optional),WDT

Programmable Low-Voltage Detect

Yes Yes Yes Yes

Programmable Brown-out Reset Yes Yes Yes YesInstruction Set 75 Instructions;

83 with Extended Instruction Set

enabled

75 Instructions; 83 with Extended

Instruction Set enabled





Packages 28-Pin PDIP28-Pin SOIC

28-Pin PDIP28-Pin SOIC

40-Pin PDIP44-Pin QFN

44-Pin TQFP

40-Pin PDIP44-Pin QFN

44-Pin TQFP 2009 Microchip Technology Inc. DS39632E-page 9

PIC18F2455/2550/4455/4550

FIGURE 1-1: PIC18F2455/2550 (28-PIN) BLOCK DIAGRAM

Data Latch

Data Memory(2 Kbytes)

Address Latch

Data Address12

AccessBSR4 4

PCH PCL

PCLATH

8

31 Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

8

88

ALU

Address Latch

Program Memory(24/32 Kbytes)

Data Latch

20

8

8

Table Pointer

inc/dec logic

21

8

Data Bus

Table Latch8

IR

12

3

ROM Latch

PCLATU

PCU

PORTE

MCLR/VPP/RE3(1)

Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer

to Section 2.0 Oscillator Configurations for additional information.3: RB3 is the alternate pin for CCP2 multiplexing.

W

Instruction Bus

STKPTR Bank

8

8

8

BITOP

FSR0FSR1FSR2

inc/dec

Address

12

Decode

logic

EUSARTComparator MSSP 10-Bit ADC

Timer2Timer1 Timer3Timer0HLVD

CCP2

BOR DataEEPROM

USB

InstructionDecode &

Control

State MachineControl Signals

Power-upTimer

OscillatorStart-up Timer

Power-onReset

WatchdogTimer

OSC1(2)

OSC2(2)

VDD,

Brown-outReset

InternalOscillator

Fail-SafeClock Monitor

ReferenceBand Gap

VSS

MCLR(1)

Block

INTRCOscillator

8 MHzOscillator

Single-SupplyProgramming

In-CircuitDebugger

T1OSI

T1OSO

USB VoltageRegulatorVUSB

PORTB

PORTC

RB0/AN12/INT0/FLT0/SDI/SDA

RC0/T1OSO/T13CKIRC1/T1OSI/CCP2(3)/UOERC2/CCP1RC4/D-/VMRC5/D+/VPRC6/TX/CKRC7/RX/DT/SDO

RB1/AN10/INT1/SCK/SCLRB2/AN8/INT2/VMORB3/AN9/CCP2(3)/VPORB4/AN11/KBI0RB5/KBI1/PGMRB6/KBI2/PGCRB7/KBI3/PGD

PORTA


RA3/AN3/VREF+RA2/AN2/VREF-/CVREFRA1/AN1RA0/AN0

OSC2/CLKO/RA6

CCP1DS39632E-page 10 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

FIGURE 1-2: PIC18F4455/4550 (40/44-PIN) BLOCK DIAGRAM

InstructionDecode &

Control

Data Latch

Data Memory(2 Kbytes)

Address Latch

Data Address12

AccessBSR4 4

PCH PCL

PCLATH

8

31 Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

8

BITOP88

ALU

Address Latch

Program Memory(24/32 Kbytes)

Data Latch

20

8

8

Table Pointer

inc/dec logic

21

8

Data Bus

Table Latch8

IR

12

3

ROM Latch

PORTD

RD0/SPP0:RD4/SPP4

PCLATU

PCU

PORTE

MCLR/VPP/RE3(1)RE2/AN7/OESPP

RE0/AN5/CK1SPPRE1/AN6/CK2SPP

Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer

to Section 2.0 Oscillator Configurations for additional information.3: These pins are only available on 44-pin TQFP packages under certain conditions. Refer to Section 25.9 Special ICPORT Features

(44-Pin TQFP Package Only) for additional information.4: RB3 is the alternate pin for CCP2 multiplexing.

EUSARTComparator MSSP 10-Bit ADC

Timer2Timer1 Timer3Timer0

CCP2

HLVD

ECCP1

BOR DataEEPROM

W

Instruction Bus

STKPTR Bank

8

State MachineControl Signals

8

8

Power-upTimer

OscillatorStart-up Timer

Power-onReset

WatchdogTimer

OSC1(2)

OSC2(2)

VDD, VSS

Brown-outReset

InternalOscillator

Fail-SafeClock Monitor

ReferenceBand Gap

MCLR(1)

Block

INTRCOscillator

8 MHzOscillator

Single-SupplyProgramming

In-CircuitDebugger

T1OSI

T1OSO

RD5/SPP5/P1BRD6/SPP6/P1CRD7/SPP7/P1D

PORTA

PORTB

PORTC



RC0/T1OSO/T13CKIRC1/T1OSI/CCP2(4)/UOERC2/CCP1/P1ARC4/D-/VMRC5/D+/VPRC6/TX/CKRC7/RX/DT/SDO

RA3/AN3/VREF+RA2/AN2/VREF-/CVREFRA1/AN1RA0/AN0

RB1/AN10/INT1/SCK/SCLRB2/AN8/INT2/VMORB3/AN9/CCP2(4)/VPO

OSC2/CLKO/RA6

RB4/AN11/KBI0/CSSPPRB5/KBI1/PGMRB6/KBI2/PGCRB7/KBI3/PGD

USB

FSR0FSR1FSR2

inc/dec

Address

12

Decode

logic

USB VoltageRegulator

VUSB

ICRST(3)

ICPGC(3)

ICPGD(3)

ICPORTS(3) 2009 Microchip Technology Inc. DS39632E-page 11

PIC18F2455/2550/4455/4550

TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number Pin

TypeBufferType DescriptionPDIP,

SOIC

MCLR/VPP/RE3MCLR

VPPRE3

1I

PI

ST

ST

Master Clear (input) or programming voltage (input).Master Clear (Reset) input. This pin is an active-low Reset to the device.Programming voltage input.Digital input.

OSC1/CLKIOSC1CLKI

9II

AnalogAnalog

Oscillator crystal or external clock input.Oscillator crystal input or external clock source input. External clock source input. Always associated with pin function OSC1. (See OSC2/CLKO pin.)

OSC2/CLKO/RA6OSC2

CLKO

RA6

10O

O

I/O

TTL

Oscillator crystal or clock output.Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode.In select modes, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.2: Default assignment for CCP2 when CCP2MX Configuration bit is set.DS39632E-page 12 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550PORTA is a bidirectional I/O port.RA0/AN0

RA0AN0

2I/OI

TTLAnalog

Digital I/O.Analog input 0.

RA1/AN1RA1AN1

3I/OI

TTLAnalog


RA2/AN2/VREF-/CVREFRA2AN2VREF-CVREF

4I/OIIO

TTLAnalogAnalogAnalog

Digital I/O.Analog input 2.A/D reference voltage (low) input.Analog comparator reference output.

RA3/AN3/VREF+RA3AN3VREF+

5I/OII

TTLAnalogAnalog

Digital I/O.Analog input 3.A/D reference voltage (high) input.

RA4/T0CKI/C1OUT/RCVRA4T0CKIC1OUTRCV

6I/OIOI

STST

TTL

Digital I/O.Timer0 external clock input.Comparator 1 output.External USB transceiver RCV input.

RA5/AN4/SS/HLVDIN/C2OUT

RA5AN4SSHLVDINC2OUT

7

I/OIIIO

TTLAnalog

TTLAnalog

Digital I/O.Analog input 4.SPI slave select input.High/Low-Voltage Detect input.Comparator 2 output.

RA6 See the OSC2/CLKO/RA6 pin.

TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number Pin


SOIC


Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.2: Default assignment for CCP2 when CCP2MX Configuration bit is set. 2009 Microchip Technology Inc. DS39632E-page 13

PIC18F2455/2550/4455/4550PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.


RB0AN12INT0FLT0SDISDA

21

I/OIIII

I/O

TTLAnalog

STSTSTST

Digital I/O.Analog input 12. External interrupt 0.PWM Fault input (CCP1 module).SPI data in.I2C data I/O.

RB1/AN10/INT1/SCK/SCL

RB1AN10INT1SCKSCL

22

I/OII

I/OI/O

TTLAnalog

STSTST

Digital I/O.Analog input 10. External interrupt 1.Synchronous serial clock input/output for SPI mode.Synchronous serial clock input/output for I2C mode.

RB2/AN8/INT2/VMORB2AN8INT2VMO

23I/OIIO

TTLAnalog

ST

Digital I/O.Analog input 8.External interrupt 2.External USB transceiver VMO output.

RB3/AN9/CCP2/VPORB3AN9CCP2(1)VPO

24I/OI

I/OO

TTLAnalog

ST

Digital I/O.Analog input 9. Capture 2 input/Compare 2 output/PWM2 output.External USB transceiver VPO output.

RB4/AN11/KBI0RB4AN11KBI0

25I/OII

TTLAnalog

TTL

Digital I/O.Analog input 11.Interrupt-on-change pin.

RB5/KBI1/PGMRB5KBI1PGM

26I/OI

I/O

TTLTTLST

Digital I/O.Interrupt-on-change pin.Low-Voltage ICSP Programming enable pin.

RB6/KBI2/PGCRB6KBI2PGC

27I/OI

I/O

TTLTTLST

Digital I/O.Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin.

RB7/KBI3/PGDRB7KBI3PGD

28I/OI

I/O

TTLTTLST

Digital I/O.Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin.


Pin Name

Pin Number Pin


SOIC


Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.2: Default assignment for CCP2 when CCP2MX Configuration bit is set.DS39632E-page 14 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550PORTC is a bidirectional I/O port.RC0/T1OSO/T13CKI

RC0T1OSOT13CKI

11I/OOI

STST

Digital I/O.Timer1 oscillator output. Timer1/Timer3 external clock input.

RC1/T1OSI/CCP2/UOERC1T1OSICCP2(2)UOE

12I/OI

I/OO

STCMOS

ST

Digital I/O.Timer1 oscillator input.Capture 2 input/Compare 2 output/PWM2 output.External USB transceiver OE output.

RC2/CCP1RC2CCP1

13I/OI/O

STST

Digital I/O.Capture 1 input/Compare 1 output/PWM1 output.

RC4/D-/VMRC4D-VM

15I

I/OI

TTL

TTL

Digital input.USB differential minus line (input/output).External USB transceiver VM input.

RC5/D+/VPRC5D+VP

16I

I/OO

TTL

TTL

Digital input.USB differential plus line (input/output).External USB transceiver VP input.

RC6/TX/CKRC6TXCK

17I/OOI/O

STST

Digital I/O.EUSART asynchronous transmit. EUSART synchronous clock (see RX/DT).

RC7/RX/DT/SDORC7RXDTSDO

18I/OI

I/OO

STSTST

Digital I/O.EUSART asynchronous receive.EUSART synchronous data (see TX/CK).SPI data out.

RE3 See MCLR/VPP/RE3 pin.VUSB 14 P Internal USB 3.3V voltage regulator output, positive supply for

internal USB transceiver. VSS 8, 19 P Ground reference for logic and I/O pins.VDD 20 P Positive supply for logic and I/O pins.


Pin Name

Pin Number Pin


SOIC


Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.2: Default assignment for CCP2 when CCP2MX Configuration bit is set. 2009 Microchip Technology Inc. DS39632E-page 15

PIC18F2455/2550/4455/4550

TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS

Pin NamePin Number Pin

TypeBufferType DescriptionPDIP QFN TQFP

MCLR/VPP/RE3MCLR

VPPRE3

1 18 18I

PI

ST

ST

Master Clear (input) or programming voltage (input).Master Clear (Reset) input. This pin is an active-low Reset to the device.Programming voltage input.Digital input.

OSC1/CLKIOSC1CLKI

13 32 30II

AnalogAnalog

Oscillator crystal or external clock input.Oscillator crystal input or external clock source input. External clock source input. Always associated with pin function OSC1. (See OSC2/CLKO pin.)

OSC2/CLKO/RA6OSC2

CLKO

RA6

14 33 31O

O

I/O

TTL

Oscillator crystal or clock output.Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode.In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin.


Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.2: Default assignment for CCP2 when CCP2MX Configuration bit is set.3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No

Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.DS39632E-page 16 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550PORTA is a bidirectional I/O port.RA0/AN0

RA0AN0

2 19 19I/OI

TTLAnalog


RA1/AN1RA1AN1

3 20 20I/OI

TTLAnalog


RA2/AN2/VREF-/CVREF

RA2AN2VREF-CVREF

4 21 21

I/OIIO

TTLAnalogAnalogAnalog

Digital I/O.Analog input 2.A/D reference voltage (low) input.Analog comparator reference output.

RA3/AN3/VREF+RA3AN3VREF+

5 22 22I/OII

TTLAnalogAnalog

Digital I/O.Analog input 3.A/D reference voltage (high) input.

RA4/T0CKI/C1OUT/RCV

RA4T0CKIC1OUTRCV

6 23 23

I/OIOI

STST

TTL

Digital I/O.Timer0 external clock input.Comparator 1 output.External USB transceiver RCV input.

RA5/AN4/SS/HLVDIN/C2OUT

RA5AN4SSHLVDINC2OUT

7 24 24

I/OIIIO

TTLAnalog

TTLAnalog

Digital I/O.Analog input 4.SPI slave select input.High/Low-Voltage Detect input.Comparator 2 output.

RA6 See the OSC2/CLKO/RA6 pin.






Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. 2009 Microchip Technology Inc. DS39632E-page 17

PIC18F2455/2550/4455/4550PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.


RB0AN12INT0FLT0SDISDA

33 9 8

I/OIIII

I/O

TTLAnalog

STSTSTST

Digital I/O.Analog input 12. External interrupt 0.Enhanced PWM Fault input (ECCP1 module).SPI data in.I2C data I/O.

RB1/AN10/INT1/SCK/SCL

RB1AN10INT1SCKSCL

34 10 9

I/OII

I/OI/O

TTLAnalog

STSTST

Digital I/O.Analog input 10. External interrupt 1.Synchronous serial clock input/output for SPI mode.Synchronous serial clock input/output for I2C mode.

RB2/AN8/INT2/VMORB2AN8INT2VMO

35 11 10I/OIIO

TTLAnalog

ST

Digital I/O.Analog input 8.External interrupt 2.External USB transceiver VMO output.

RB3/AN9/CCP2/VPORB3AN9CCP2(1)VPO

36 12 11I/OI

I/OO

TTLAnalog

ST

Digital I/O.Analog input 9. Capture 2 input/Compare 2 output/PWM2 output.External USB transceiver VPO output.

RB4/AN11/KBI0/CSSPPRB4AN11KBI0CSSPP

37 14 14I/OIIO

TTLAnalog

TTL

Digital I/O.Analog input 11.Interrupt-on-change pin.SPP chip select control output.

RB5/KBI1/PGMRB5KBI1PGM

38 15 15I/OI

I/O

TTLTTLST

Digital I/O.Interrupt-on-change pin.Low-Voltage ICSP Programming enable pin.

RB6/KBI2/PGCRB6KBI2PGC

39 16 16I/OI

I/O

TTLTTLST

Digital I/O.Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin.

RB7/KBI3/PGDRB7KBI3PGD

40 17 17I/OI

I/O

TTLTTLST

Digital I/O.Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin.







PIC18F2455/2550/4455/4550PORTC is a bidirectional I/O port.RC0/T1OSO/T13CKI

RC0T1OSOT13CKI

15 34 32I/OOI

STST

Digital I/O.Timer1 oscillator output. Timer1/Timer3 external clock input.

RC1/T1OSI/CCP2/UOE

RC1T1OSICCP2(2)UOE

16 35 35

I/OI

I/OO

STCMOS

ST

Digital I/O.Timer1 oscillator input.Capture 2 input/Compare 2 output/PWM2 output.External USB transceiver OE output.

RC2/CCP1/P1ARC2CCP1P1A

17 36 36I/OI/OO

STSTTTL

Digital I/O.Capture 1 input/Compare 1 output/PWM1 output.Enhanced CCP1 PWM output, channel A.

RC4/D-/VMRC4D-VM

23 42 42I

I/OI

TTL

TTL

Digital input.USB differential minus line (input/output).External USB transceiver VM input.

RC5/D+/VPRC5D+VP

24 43 43I

I/OI

TTL

TTL

Digital input.USB differential plus line (input/output).External USB transceiver VP input.

RC6/TX/CKRC6TXCK

25 44 44I/OO

I/O

STST

Digital I/O.EUSART asynchronous transmit. EUSART synchronous clock (see RX/DT).

RC7/RX/DT/SDORC7RXDTSDO

26 1 1I/OI

I/OO

STSTST

Digital I/O.EUSART asynchronous receive.EUSART synchronous data (see TX/CK).SPI data out.







PIC18F2455/2550/4455/4550PORTD is a bidirectional I/O port or a Streaming Parallel Port (SPP). These pins have TTL input buffers when the SPP module is enabled.

RD0/SPP0RD0SPP0

19 38 38I/OI/O

STTTL

Digital I/O.Streaming Parallel Port data.

RD1/SPP1RD1SPP1

20 39 39I/OI/O

STTTL


RD2/SPP2RD2SPP2

21 40 40I/OI/O

STTTL


RD3/SPP3RD3SPP3

22 41 41I/OI/O

STTTL


RD4/SPP4RD4SPP4

27 2 2I/OI/O

STTTL


RD5/SPP5/P1BRD5SPP5P1B

28 3 3I/OI/OO

STTTL

Digital I/O.Streaming Parallel Port data.Enhanced CCP1 PWM output, channel B.

RD6/SPP6/P1CRD6SPP6P1C

29 4 4I/OI/OO

STTTL

Digital I/O.Streaming Parallel Port data.Enhanced CCP1 PWM output, channel C.

RD7/SPP7/P1DRD7SPP7P1D

30 5 5I/OI/OO

STTTL

Digital I/O.Streaming Parallel Port data.Enhanced CCP1 PWM output, channel D.







PIC18F2455/2550/4455/4550PORTE is a bidirectional I/O port.RE0/AN5/CK1SPP

RE0AN5CK1SPP

8 25 25I/OIO

STAnalog

Digital I/O.Analog input 5.SPP clock 1 output.

RE1/AN6/CK2SPPRE1AN6CK2SPP

9 26 26I/OIO

STAnalog

Digital I/O.Analog input 6.SPP clock 2 output.

RE2/AN7/OESPPRE2AN7OESPP

10 27 27I/OIO

STAnalog

Digital I/O.Analog input 7.SPP output enable output.

RE3 See MCLR/VPP/RE3 pin.VSS 12, 31 6, 30,

316, 29 P Ground reference for logic and I/O pins.

VDD 11, 32 7, 8, 28, 29

7, 28 P Positive supply for logic and I/O pins.

VUSB 18 37 37 P Internal USB 3.3V voltage regulator output, positive supply for the USB transceiver.

NC/ICCK/ICPGC(3)ICCKICPGC

12I/OI/O

STST

No Connect or dedicated ICD/ICSP port clock.In-Circuit Debugger clock. ICSP programming clock.

NC/ICDT/ICPGD(3)ICDTICPGD

13I/OI/O

STST

No Connect or dedicated ICD/ICSP port clock.In-Circuit Debugger data.ICSP programming data.

NC/ICRST/ICVPP(3)ICRSTICVPP

33IP

No Connect or dedicated ICD/ICSP port Reset.Master Clear (Reset) input.Programming voltage input.

NC/ICPORTS(3)ICPORTS

34 P No Connect or 28-pin device emulation.Enable 28-pin device emulation when connectedto VSS.

NC 13 No Connect.







PIC18F2455/2550/4455/4550

NOTES:DS39632E-page 22 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/45502.0 OSCILLATOR CONFIGURATIONS

2.1 OverviewDevices in the PIC18F2455/2550/4455/4550 familyincorporate a different oscillator and microcontrollerclock system than previous PIC18F devices. The addi-tion of the USB module, with its unique requirementsfor a stable clock source, make it necessary to providea separate clock source that is compliant with bothUSB low-speed and full-speed specifications.To accommodate these requirements, PIC18F2455/2550/4455/4550 devices include a new clock branch toprovide a 48 MHz clock for full-speed USB operation.Since it is driven from the primary clock source, anadditional system of prescalers and postscalers hasbeen added to accommodate a wide range of oscillatorfrequencies. An overview of the oscillator structure isshown in Figure 2-1.Other oscillator features used in PIC18 enhancedmicrocontrollers, such as the internal oscillator blockand clock switching, remain the same. They arediscussed later in this chapter.

2.1.1 OSCILLATOR CONTROLThe operation of the oscillator in PIC18F2455/2550/4455/4550 devices is controlled through two Configu-ration registers and two control registers. Configurationregisters, CONFIG1L and CONFIG1H, select theoscillator mode and USB prescaler/postscaler options.As Configuration bits, these are set when the device isprogrammed and left in that configuration until thedevice is reprogrammed. The OSCCON register (Register 2-2) selects the ActiveClock mode; it is primarily used in controlling clockswitching in power-managed modes. Its use isdiscussed in Section 2.4.1 Oscillator ControlRegister.The OSCTUNE register (Register 2-1) is used to trimthe INTRC frequency source, as well as select thelow-frequency clock source that drives several specialfeatures. Its use is described in Section 2.2.5.2OSCTUNE Register.

2.2 Oscillator TypesPIC18F2455/2550/4455/4550 devices can be operatedin twelve distinct oscillator modes. In contrast with pre-vious PIC18 enhanced microcontrollers, four of thesemodes involve the use of two oscillator types at once.Users can program the FOSC3:FOSC0 Configurationbits to select one of these modes:1. XT Crystal/Resonator2. HS High-Speed Crystal/Resonator3. HSPLL High-Speed Crystal/Resonator

with PLL Enabled4. EC External Clock with FOSC/4 Output5. ECIO External Clock with I/O on RA66. ECPLL External Clock with PLL Enabled

and FOSC/4 Output on RA67. ECPIO External Clock with PLL Enabled,

I/O on RA68. INTHS Internal Oscillator used as

Microcontroller Clock Source, HS Oscillator used as USB Clock Source

9. INTIO Internal Oscillator used as Microcontroller Clock Source, ECOscillator used as USB Clock Source,Digital I/O on RA6

10. INTCKO Internal Oscillator used as Microcontroller Clock Source, EC Oscillator used as USB Clock Source, FOSC/4 Output on RA6

2.2.1 OSCILLATOR MODES AND USB OPERATION

Because of the unique requirements of the USB module,a different approach to clock operation is necessary. Inprevious PIC devices, all core and peripheral clockswere driven by a single oscillator source; the usualsources were primary, secondary or the internal oscilla-tor. With PIC18F2455/2550/4455/4550 devices, the pri-mary oscillator becomes part of the USB module andcannot be associated to any other clock source. Thus,the USB module must be clocked from the primary clocksource; however, the microcontroller core and otherperipherals can be separately clocked from thesecondary or internal oscillators as before.

Because of the timing requirements imposed by USB,an internal clock of either 6 MHz or 48 MHz is requiredwhile the USB module is enabled. Fortunately, themicrocontroller and other peripherals are not requiredto run at this clock speed when using the primaryoscillator. There are numerous options to achieve theUSB module clock requirement and still provide flexibil-ity for clocking the rest of the device from the primaryoscillator source. These are detailed in Section 2.3Oscillator Settings for USB. 2009 Microchip Technology Inc. DS39632E-page 23

PIC18F2455/2550/4455/4550

FIGURE 2-1: PIC18F2455/2550/4455/4550 CLOCK DIAGRAM

PIC18F2455/2550/4455/4550

FOSC3:FOSC0

Secondary Oscillator

T1OSCENEnableOscillator

T1OSO

T1OSI

Clock Source Option for Other Modules

OSC1

OSC2

Sleep

Primary Oscillator

XT, HS, EC, ECIO

T1OSC

CPU

Peripherals

IDLEN

INTO

SC

Pos

tsca

ler

MU

X

MU

X

8 MHz

4 MHz

2 MHz

1 MHz500 kHz

125 kHz

250 kHz

OSCCON

11111010110001101000100031 kHz

INTRCSource

InternalOscillator

Block

WDT, PWRT, FSCM

8 MHz

Internal Oscillator

(INTOSC)

ClockControl

OSCCON Source8 MHz

31 kHz (INTRC)01

OSCTUNE

and Two-Speed Start-up

96 MHzPLL

PLLDIV

CPUDIV

01

01 2

PLL

Pre

scal

er

MU

X

111110101100011010001000 1

2 3 4 5 6

10 12

11100100PL

L P

osts

cale

r 2 3 4 6

USB

USBDIV

FOSC3:FOSC0

HSPLL, ECPLL,

11100100

Osc

illato

r Pos

tsca

ler

1 2 3 4

CPUDIV

1

0

Peripheral

FSEN

4

USB Clock Source

XTPLL, ECPIO

PrimaryClock

(4 MHz Input Only)DS39632E-page 24 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

2.2.2 CRYSTAL OSCILLATOR/CERAMIC

RESONATORSIn HS, HSPLL, XT and XTPLL Oscillator modes, acrystal or ceramic resonator is connected to the OSC1and OSC2 pins to establish oscillation. Figure 2-2shows the pin connections.

The oscillator design requires the use of a parallel cutcrystal.

FIGURE 2-2: CRYSTAL/CERAMIC RESONATOR OPERATION (XT, HS OR HSPLL CONFIGURATION)

TABLE 2-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS

Note: Use of a series cut crystal may give a fre-quency out of the crystal manufacturersspecifications.

Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2.

2: A series resistor (RS) may be required for AT strip cut crystals.

3: RF varies with the oscillator mode chosen.

C1(1)

C2(1)

XTAL

OSC2

OSC1

RF(3)

Sleep

To

Logic

PIC18FXXXXRS(2)

Internal

Typical Capacitor Values Used:

Mode Freq OSC1 OSC2

XT 4.0 MHz 33 pF 33 pFHS 8.0 MHz

16.0 MHz27 pF22 pF

27 pF22 pF

Capacitor values are for design guidance only. These capacitors were tested with the resonatorslisted below for basic start-up and operation. Thesevalues are not optimized.Different capacitor values may be required to produceacceptable oscillator operation. The user should testthe performance of the oscillator over the expectedVDD and temperature range for the application.

See the notes following Table 2-2 for additionalinformation.

Resonators Used:

4.0 MHz8.0 MHz

16.0 MHzWhen using ceramic resonators with frequenciesabove 3.5 MHz, HS mode is recommended over XTmode. HS mode may be used at any VDD for whichthe controller is rated. If HS is selected, the gain of theoscillator may overdrive the resonator. Therefore, aseries resistor should be placed between the OSC2pin and the resonator. As a good starting point, therecommended value of RS is 330 . 2009 Microchip Technology Inc. DS39632E-page 25

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TABLE 2-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

An internal postscaler allows users to select a clockfrequency other than that of the crystal or resonator.Frequency division is determined by the CPUDIVConfiguration bits. Users may select a clock frequencyof the oscillator frequency, or 1/2, 1/3 or 1/4 of thefrequency.

An external clock may also be used when the micro-controller is in HS Oscillator mode. In this case, theOSC2/CLKO pin is left open (Figure 2-3).

FIGURE 2-3: EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION)

2.2.3 EXTERNAL CLOCK INPUTThe EC, ECIO, ECPLL and ECPIO Oscillator modesrequire an external clock source to be connected to theOSC1 pin. There is no oscillator start-up time requiredafter a Power-on Reset or after an exit from Sleepmode.

In the EC and ECPLL Oscillator modes, the oscillatorfrequency divided by 4 is available on the OSC2 pin.This signal may be used for test purposes or tosynchronize other logic. Figure 2-4 shows the pinconnections for the EC Oscillator mode.

FIGURE 2-4: EXTERNAL CLOCKINPUT OPERATION(EC AND ECPLL CONFIGURATION)

The ECIO and ECPIO Oscillator modes function like theEC and ECPLL modes, except that the OSC2 pinbecomes an additional general purpose I/O pin. The I/Opin becomes bit 6 of PORTA (RA6). Figure 2-5 showsthe pin connections for the ECIO Oscillator mode.

FIGURE 2-5: EXTERNAL CLOCK INPUT OPERATION (ECIO AND ECPIO CONFIGURATION)

The internal postscaler for reducing clock frequency inXT and HS modes is also available in EC and ECIOmodes.

Osc Type Crystal Freq

Typical Capacitor Values Tested:

C1 C2

XT 4 MHz 27 pF 27 pFHS 4 MHz 27 pF 27 pF

8 MHz 22 pF 22 pF20 MHz 15 pF 15 pF

Capacitor values are for design guidance only. These capacitors were tested with the crystals listedbelow for basic start-up and operation. These valuesare not optimized.Different capacitor values may be required to produceacceptable oscillator operation. The user should testthe performance of the oscillator over the expectedVDD and temperature range for the application.

See the notes following this table for additionalinformation.

Crystals Used:

4 MHz8 MHz

20 MHz

Note 1: Higher capacitance increases the stabilityof oscillator but also increases thestart-up time.

2: When operating below 3V VDD, or whenusing certain ceramic resonators at anyvoltage, it may be necessary to use theHS mode or switch to a crystal oscillator.

3: Since each resonator/crystal has its owncharacteristics, the user should consultthe resonator/crystal manufacturer forappropriate values of externalcomponents.

4: Rs may be required to avoid overdrivingcrystals with low drive level specification.

5: Always verify oscillator performance overthe VDD and temperature range that isexpected for the application.

OSC1

OSC2Open

Clock fromExt. System PIC18FXXXX

(HS Mode)

OSC1/CLKI

OSC2/CLKOFOSC/4

Clock fromExt. System PIC18FXXXX

OSC1/CLKI

I/O (OSC2)RA6

Clock fromExt. System PIC18FXXXXDS39632E-page 26 2009 Microchip Technology Inc.

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2.2.4 PLL FREQUENCY MULTIPLIERPIC18F2455/2550/4255/4550 devices include a PhaseLocked Loop (PLL) circuit. This is provided specificallyfor USB applications with lower speed oscillators andcan also be used as a microcontroller clock source.

The PLL is enabled in HSPLL, XTPLL, ECPLL andECPIO Oscillator modes. It is designed to produce afixed 96 MHz reference clock from a fixed 4 MHz input.The output can then be divided and used for both theUSB and the microcontroller core clock. Because thePLL has a fixed frequency input and output, there areeight prescaling options to match the oscillator inputfrequency to the PLL.

There is also a separate postscaler option for derivingthe microcontroller clock from the PLL. This allows theUSB peripheral and microcontroller to use the sameoscillator input and still operate at different clockspeeds. In contrast to the postscaler for XT, HS and ECmodes, the available options are 1/2, 1/3, 1/4 and 1/6of the PLL output.

The HSPLL, ECPLL and ECPIO modes make use ofthe HS mode oscillator for frequencies up to 48 MHz.The prescaler divides the oscillator input by up to 12 toproduce the 4 MHz drive for the PLL. The XTPLL modecan only use an input frequency of 4 MHz which drivesthe PLL directly.

FIGURE 2-6: PLL BLOCK DIAGRAM (HS MODE)

2.2.5 INTERNAL OSCILLATOR BLOCKThe PIC18F2455/2550/4455/4550 devices include aninternal oscillator block which generates two differentclock signals; either can be used as the microcontrollersclock source. If the USB peripheral is not used, theinternal oscillator may eliminate the need for externaloscillator circuits on the OSC1 and/or OSC2 pins.

The main output (INTOSC) is an 8 MHz clock sourcewhich can be used to directly drive the device clock. Italso drives the INTOSC postscaler which can provide arange of clock frequencies from 31 kHz to 4 MHz. TheINTOSC output is enabled when a clock frequencyfrom 125 kHz to 8 MHz is selected.

The other clock source is the internal RC oscillator(INTRC) which provides a nominal 31 kHz output.INTRC is enabled if it is selected as the device clocksource; it is also enabled automatically when any of thefollowing are enabled:

Power-up Timer Fail-Safe Clock Monitor Watchdog Timer Two-Speed Start-up

These features are discussed in greater detail inSection 25.0 Special Features of the CPU.The clock source frequency (INTOSC direct, INTRCdirect or INTOSC postscaler) is selected by configuringthe IRCF bits of the OSCCON register (page 33).

2.2.5.1 Internal Oscillator ModesWhen the internal oscillator is used as the micro-controller clock source, one of the other oscillatormodes (External Clock or External Crystal/Resonator)must be used as the USB clock source. The choice ofthe USB clock source is determined by the particularinternal oscillator mode.

There are four distinct modes available:

1. INTHS mode: The USB clock is provided by theoscillator in HS mode.

2. INTXT mode: The USB clock is provided by theoscillator in XT mode.

3. INTCKO mode: The USB clock is provided by anexternal clock input on OSC1/CLKI; the OSC2/CLKO pin outputs FOSC/4.

4. INTIO mode: The USB clock is provided by anexternal clock input on OSC1/CLKI; the OSC2/CLKO pin functions as a digital I/O (RA6).

Of these four modes, only INTIO mode frees up anadditional pin (OSC2/CLKO/RA6) for port I/O use.

MU

X

VCO

LoopFilter

andPrescaler

OSC2

OSC1

PLL Enable

FINFOUT

SYSCLK

PhaseComparator

HS/EC/ECIO/XT Oscillator Enable

24

(from CONFIG1H Register)

Oscillator 2009 Microchip Technology Inc. DS39632E-page 27

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2.2.5.2 OSCTUNE RegisterThe internal oscillators output has been calibrated atthe factory but can be adjusted in the users applica-tion. This is done by writing to the OSCTUNE register(Register 2-1). The tuning sensitivity is constantthroughout the tuning range.

The INTOSC clock will stabilize within 1 ms. Code exe-cution continues during this shift. There is no indicationthat the shift has occurred.

The OSCTUNE register also contains the INTSRC bit.The INTSRC bit allows users to select which internaloscillator provides the clock source when the 31 kHzfrequency option is selected. This is covered in greaterdetail in Section 2.4.1 Oscillator Control Register.

2.2.5.3 Internal Oscillator Output Frequency and Drift

The internal oscillator block is calibrated at the factoryto produce an INTOSC output frequency of 8.0 MHz.However, this frequency may drift as VDD or tempera-ture changes, which can affect the controller operationin a variety of ways.

The low-frequency INTRC oscillator operates indepen-dently of the INTOSC source. Any changes in INTOSCacross voltage and temperature are not necessarilyreflected by changes in INTRC and vice versa.

REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER

R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as 0-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown

bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)0 = 31 kHz device clock derived directly from INTRC internal oscillator

bit 6-5 Unimplemented: Read as 0bit 4-0 TUN4:TUN0: Frequency Tuning bits

01111 = Maximum frequency 00001 00000 = Center frequency. Oscillator module is running at the calibrated frequency.11111 10000 = Minimum frequencyDS39632E-page 28 2009 Microchip Technology Inc.

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2.2.5.4 Compensating for INTOSC DriftIt is possible to adjust the INTOSC frequency bymodifying the value in the OSCTUNE register. This hasno effect on the INTRC clock source frequency.

Tuning the INTOSC source requires knowing when tomake the adjustment, in which direction it should bemade and in some cases, how large a change isneeded. When using the EUSART, for example, anadjustment may be required when it begins to generateframing errors or receives data with errors while inAsynchronous mode. Framing errors indicate that thedevice clock frequency is too high; to adjust for this,decrement the value in OSCTUNE to reduce the clockfrequency. On the other hand, errors in data may sug-gest that the clock speed is too low; to compensate,increment OSCTUNE to increase the clock frequency.

It is also possible to verify device clock speed againsta reference clock. Two timers may be used: one timeris clocked by the peripheral clock, while the other isclocked by a fixed reference source, such as theTimer1 oscillator. Both timers are cleared but the timerclocked by the reference generates interrupts. Whenan interrupt occurs, the internally clocked timer is readand both timers are cleared. If the internally clockedtimer value is greater than expected, then the internaloscillator block is running too fast. To adjust for this,decrement the OSCTUNE register.

Finally, a CCP module can use free-running Timer1 (orTimer3), clocked by the internal oscillator block and anexternal event with a known period (i.e., AC powerfrequency). The time of the first event is captured in theCCPRxH:CCPRxL registers and is recorded for uselater. When the second event causes a capture, thetime of the first event is subtracted from the time of thesecond event. Since the period of the external event isknown, the time difference between events can becalculated.

If the measured time is much greater than the calcu-lated time, the internal oscillator block is running toofast; to compensate, decrement the OSCTUNE register.If the measured time is much less than the calculatedtime, the internal oscillator block is running too slow; tocompensate, increment the OSCTUNE register. 2009 Microchip Technology Inc. DS39632E-page 29

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2.3 Oscillator Settings for USBWhen these devices are used for USB connectivity,they must have either a 6 MHz or 48 MHz clock forUSB operation, depending on whether Low-Speed orFull-Speed mode is being used. This may require someforethought in selecting an oscillator frequency andprogramming the device. The full range of possible oscillator configurationscompatible with USB operation is shown in Table 2-3.

2.3.1 LOW-SPEED OPERATIONThe USB clock for Low-Speed mode is derived from theprimary oscillator chain and not directly from the PLL. Itis divided by 4 to produce the actual 6 MHz clock.Because of this, the microcontroller can only use aclock frequency of 24 MHz when the USB module is

active and the controller clock source is one of theprimary oscillator modes (XT, HS or EC, with or withoutthe PLL). This restriction does not apply if the microcontrollerclock source is the secondary oscillator or internaloscillator block.

2.3.2 RUNNING DIFFERENT USB AND MICROCONTROLLER CLOCKS

The USB module, in either mode, can run asynchro-nously with respect to the microcontroller core andother peripherals. This means that applications can usethe primary oscillator for the USB clock while the micro-controller runs from a separate clock source at a lowerspeed. If it is necessary to run the entire applicationfrom only one clock source, full-speed operationprovides a greater selection of microcontroller clockfrequencies.

TABLE 2-3: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATIONInput Oscillator

FrequencyPLL Division

(PLLDIV2:PLLDIV0)Clock Mode

(FOSC3:FOSC0)MCU Clock Division(CPUDIV1:CPUDIV0)

Microcontroller Clock Frequency

48 MHz N/A(1) EC, ECIO None (00) 48 MHz2 (01) 24 MHz3 (10) 16 MHz4 (11) 12 MHz

48 MHz 12 (111) EC, ECIO None (00) 48 MHz2 (01) 24 MHz3 (10) 16 MHz4 (11) 12 MHz

ECPLL, ECPIO 2 (00) 48 MHz3 (01) 32 MHz4 (10) 24 MHz6 (11) 16 MHz

40 MHz 10 (110) EC, ECIO None (00) 40 MHz2 (01) 20 MHz3 (10) 13.33 MHz4 (11) 10 MHz

ECPLL, ECPIO 2 (00) 48 MHz 3 (01) 32 MHz4 (10) 24 MHz6 (11) 16 MHz

24 MHz 6 (101) HS, EC, ECIO None (00) 24 MHz2 (01) 12 MHz3 (10) 8 MHz4 (11) 6 MHz

HSPLL, ECPLL, ECPIO 2 (00) 48 MHz3 (01) 32 MHz4 (10) 24 MHz6 (11) 16 MHz

Legend: All clock frequencies, except 24 MHz, are exclusively associated with full-speed USB operation (USB clock of 48 MHz). Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz, USB clock of 6 MHz).

Note 1: Only valid when the USBDIV Configuration bit is cleared.DS39632E-page 30 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/455020 MHz 5 (100) HS, EC, ECIO None (00) 20 MHz2 (01) 10 MHz3 (10) 6.67 MHz4 (11) 5 MHz


16 MHz 4 (011) HS, EC, ECIO None (00) 16 MHz 2 (01) 8 MHz3 (10) 5.33 MHz4 (11) 4 MHz


12 MHz 3 (010) HS, EC, ECIO None (00) 12 MHz2 (01) 6 MHz3 (10) 4 MHz4 (11) 3 MHz


8 MHz 2 (001) HS, EC, ECIO None (00) 8 MHz2 (01) 4 MHz3 (10) 2.67 MHz4 (11) 2 MHz


4 MHz 1 (000) XT, HS, EC, ECIO None (00) 4 MHz2 (01) 2 MHz3 (10) 1.33 MHz4 (11) 1 MHz

HSPLL, ECPLL, XTPLL, ECPIO

2 (00) 48 MHz3 (01) 32 MHz4 (10) 24 MHz6 (11) 16 MHz

TABLE 2-3: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION (CONTINUED)Input Oscillator

FrequencyPLL Division

(PLLDIV2:PLLDIV0)Clock Mode

(FOSC3:FOSC0)MCU Clock Division(CPUDIV1:CPUDIV0)

Microcontroller Clock Frequency

Legend: All clock frequencies, except 24 MHz, are exclusively associated with full-speed USB operation (USB clock of 48 MHz). Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz, USB clock of 6 MHz).

Note 1: Only valid when the USBDIV Configuration bit is cleared. 2009 Microchip Technology Inc. DS39632E-page 31

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2.4 Clock Sources and Oscillator

SwitchingLike previous PIC18 enhanced devices, thePIC18F2455/2550/4455/4550 family includes a featurethat allows the device clock source to be switched fromthe main oscillator to an alternate, low-frequency clocksource. These devices offer two alternate clocksources. When an alternate clock source is enabled,the various power-managed operating modes areavailable.

Essentially, there are three clock sources for thesedevices:

Primary oscillators Secondary oscillators Internal oscillator block

The primary oscillators include the External Crystaland Resonator modes, the External Clock modes andthe internal oscillator block. The particular mode isdefined by the FOSC3:FOSC0 Configuration bits. Thedetails of these modes are covered earlier in thischapter.

The secondary oscillators are those external sourcesnot connected to the OSC1 or OSC2 pins. Thesesources may continue to operate even after thecontroller is placed in a power-managed mode.

PIC18F2455/2550/4455/4550 devices offer the Timer1oscillator as a secondary oscillator. This oscillator, in allpower-managed modes, is often the time base forfunctions such as a Real-Time Clock (RTC). Mostoften, a 32.768 kHz watch crystal is connectedbetween the RC0/T1OSO/T13CKI and RC1/T1OSI/UOE pins. Like the XT and HS Oscillator mode circuits,loading capacitors are also connected from each pin toground. The Timer1 oscillator is discussed in greaterdetail in Section 12.3 Timer1 Oscillator.In addition to being a primary clock source, the internaloscillator block is available as a power-managedmode clock source. The INTRC source is also used asthe clock source for several special features, such asthe WDT and Fail-Safe Clock Monitor.

2.4.1 OSCILLATOR CONTROL REGISTERThe OSCCON register (Register 2-2) controls severalaspects of the device clocks operation, both infull-power operation and in power-managed modes.

The System Clock Select bits, SCS1:SCS0, select theclock source. The available clock sources are theprimary clock (defined by the FOSC3:FOSC0 Configu-ration bits), the secondary clock (Timer1 oscillator) andthe internal oscillator block. The clock source changesimmediately after one or more of the bits is written to,following a brief clock transition interval. The SCS bitsare cleared on all forms of Reset.

The Internal Oscillator Frequency Select bits,IRCF2:IRCF0, select the frequency output of the internaloscillator block to drive the device clock. The choices arethe INTRC source, the INTOSC source (8 MHz) or oneof the frequencies derived from the INTOSC postscaler(31 kHz to 4 MHz). If the internal oscillator block issupplying the device clock, changing the states of thesebits will have an immediate change on the internal oscil-lators output. On device Resets, the default outputfrequency of the internal oscillator block is set at 1 MHz.

When an output frequency of 31 kHz is selected(IRCF2:IRCF0 = 000), users may choose which inter-nal oscillator acts as the source. This is done with theINTSRC bit in the OSCTUNE register (OSCTUNE).Setting this bit selects INTOSC as a 31.25 kHz clocksource by enabling the divide-by-256 output of theINTOSC postscaler. Clearing INTSRC selects INTRC(nominally 31 kHz) as the clock source.

This option allows users to select the tunable and moreprecise INTOSC as a clock source, while maintainingpower savings with a very low clock speed. Regardlessof the setting of INTSRC, INTRC always remains theclock source for features such as the Watchdog Timerand the Fail-Safe Clock Monitor.

The OSTS, IOFS and T1RUN bits indicate which clocksource is currently providing the device clock. The OSTSbit indicates that the Oscillator Start-up Timer (OST) hastimed out and the primary clock is providing the deviceclock in primary clock modes. The IOFS bit indicateswhen the internal oscillator block has stabilized and isproviding the device clock in RC Clock modes. TheT1RUN bit (T1CON) indicates when the Timer1 oscil-lator is providing the device clock in secondary clockmodes. In power-managed modes, only one of thesethree bits will be set at any time. If none of these bits areset, the INTRC is providing the clock or the internaloscillator block has just started and is not yet stable.

The IDLEN bit determines if the device goes into Sleepmode, or one of the Idle modes, when the SLEEPinstruction is executed.

The use of the flag and control bits in the OSCCONregister is discussed in more detail in Section 3.0Power-Managed Modes.

Note 1: The Timer1 oscillator must be enabled toselect the secondary clock source. TheTimer1 oscillator is enabled by setting theT1OSCEN bit in the Timer1 Control regis-ter (T1CON). If the Timer1 oscillator isnot enabled, then any attempt to select asecondary clock source will be ignored.

2: It is recommended that the Timer1oscillator be operating and stable prior toswitching to it as the clock source; other-wise, a very long delay may occur whilethe Timer1 oscillator starts. DS39632E-page 32 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550

2.4.2 OSCILLATOR TRANSITIONSPIC18F2455/2550/4455/4550 devices contain circuitryto prevent clock glitches when switching betweenclock sources. A short pause in the device clock occursduring the clock switch. The length of this pause is the

sum of two cycles of the old clock source and three tofour cycles of the new clock source. This formulaassumes that the new clock source is stable.

Clock transitions are discussed in greater detail inSection 3.1.2 Entering Power-Managed Modes.

REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0

bit 7 bit 0

Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as 0-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown

bit 7 IDLEN: Idle Enable bit1 = Device enters Idle mode on SLEEP instruction0 = Device enters Sleep mode on SLEEP instruction

bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits111 = 8 MHz (INTOSC drives clock directly)110 = 4 MHz 101 = 2 MHz 100 = 1 MHz(3) 011 = 500 kHz 010 = 250 kHz001 = 125 kHz000 = 31 kHz (from either INTOSC/256 or INTRC directly)(2)

bit 3 OSTS: Oscillator Start-up Time-out Status bit(1)

1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready

bit 2 IOFS: INTOSC Frequency Stable bit 1 = INTOSC frequency is stable0 = INTOSC frequency is not stable

bit 1-0 SCS1:SCS0: System Clock Select bits1x = Internal oscillator01 = Timer1 oscillator00 = Primary oscillator

Note 1: Depends on the state of the IESO Configuration bit.2: Source selected by the INTSRC bit (OSCTUNE), see text.3: Default output frequency of INTOSC on Reset. 2009 Microchip Technology Inc. DS39632E-page 33

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2.5 Effects of Power-Managed Modes

on the Various Clock SourcesWhen PRI_IDLE mode is selected, the designatedprimary oscillator continues to run without interruption.For all other power-managed modes, the oscillatorusing the OSC1 pin is disabled. Unless the USBmodule is enabled, the OSC1 pin (and OSC2 pin ifused by the oscillator) will stop oscillating.

In secondary clock modes (SEC_RUN andSEC_IDLE), the Timer1 oscillator is operating andproviding the device clock. The Timer1 oscillator mayalso run in all power-managed modes if required toclock Timer1 or Timer3.

In internal oscillator modes (RC_RUN and RC_IDLE),the internal oscillator block provides the device clocksource. The 31 kHz INTRC output can be used directlyto provide the clock and may be enabled to supportvarious special features regardless of thepower-managed mode (see Section 25.2 WatchdogTimer (WDT), Section 25.3 Two-Speed Start-upand Section 25.4 Fail-Safe Clock Monitor for moreinformation on WDT, Fail-Safe Clock Monitor andTwo-Speed Start-up). The INTOSC output at 8 MHzmay be used directly to clock the device or may bedivided down by the postscaler. The INTOSC output isdisabled if the clock is provided directly from the INTRCoutput.

Regardless of the Run or Idle mode selected, the USBclock source will continue to operate. If the device isoperating from a crystal or resonator-based oscillator,that oscillator will continue to clock the USB module.The core and all other modules will switch to the newclock source.

If the Sleep mode is selected, all clock sources arestopped. Since all the transistor switching currentshave been stopped, Sleep mode achieves the lowestcurrent consumption of the device (only leakagecurrents).

Sleep mode should never be invoked while the USBmodule is operating and connected. The only exceptionis when the device has been issued a Suspend

command over the USB. Once the module has sus-pended operation and shifted to a low-power state, themicrocontroller may be safely put into Sleep mode.

Enabling any on-chip feature that will operate duringSleep will increase the current consumed during Sleep.The INTRC is required to support WDT operation. TheTimer1 oscillator may be operating to support aReal-Time Clock. Other features may be operating thatdo not require a device clock source (i.e., MSSP slave,PSP, INTx pins and others). Peripherals that may addsignificant current consumption are listed inSection 28.2 DC Characteristics: Power-Down andSupply Current.

2.6 Power-up DelaysPower-up delays are controlled by two timers so that noexternal Reset circuitry is required for most applications.The delays ensure that the device is kept in Reset untilthe device power supply is stable under normal circum-stances and the primary clock is operating and stable.For additional information on power-up delays, seeSection 4.5 Device Reset Timers.The first timer is the Power-up Timer (PWRT), whichprovides a fixed delay on power-up (parameter 33,Table 28-12). It is enabled by clearing (= 0) thePWRTEN Configuration bit.

The second timer is the Oscillator Start-up Timer(OST), intended to keep the chip in Reset until thecrystal oscillator is stable (XT and HS modes). TheOST does this by counting 1024 oscillator cyclesbefore allowing the oscillator to clock the device.

When the HSPLL Oscillator mod

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