Physical Planning for the Architectural Exploration of Large-Scale Chip Multiprocessors
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Transcript of Physical Planning for the Architectural Exploration of Large-Scale Chip Multiprocessors
Physical Planning for the Architectural Exploration of
Large-Scale Chip Multiprocessors
Javier de San Pedro, Nikita Nikitin,Jordi Cortadella and Jordi Petit
Universitat Politècnica de Catalunya (Barcelona)
Project funded by Intel Corp.
Outline• Introduction
– Architectural exploration of CMPs
• Physical planning– Integration with architectural exploration– Floorplanning and wire planning technology
• Results and conclusions
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Designing a Chip Multiprocessor
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CMP Off-ChipMemory
DSP
Graphics
Data Mining
Bioinformatics
⁞
• How many cores?• How much L2/L3 on-chip cache?• Interconnect: mesh/ring/bus?• How many memory controllers?
Automated exploration
Models(performance/power)
Cores
On-chip caches
Off-chip memories
Interconnect fabrics
Cache protocol
Workloads
Architectural configuration
Number of cores
Cluster size
L2/L3 size
Hierarchical interconnect
Memory controllers
Exploration tool
Constraints
Area
Throughput
Power
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Huge design space:Billions of configurations
Our exploration flow
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Simulation
AnalyticalModeling*
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Architecturalconfigurations
Promisingconfigurations
*N. Nikitin et al. "Analytical Performance Modeling of Hierarchical Interconnect Fabrics.“NOCS 2012
Configuration example
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MC
MC
MC
MCC2
L2C2
L2C2
L2
L3
Bus
C2L2
C2L2
NIR
C1
L2
- 6x4 mesh, 24 clusters- total 144 cores- 6 cores/cluster - 1 C1, 128K L1, 256K L2 - 5 C2, 64K L1, 96K L2- 146 Mb total shared L3
Throughput = 85.71 IPC
• Min area, but …• Unbalanced aspect ratio• L2 not adjacent to cores• Uneven distribution of ring routers
Motivation for physical planning
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C
L2
C
L2
C
L2
C
L2
r r
r r
r
r
R
L3
NSWE • Block area is used during exploration
Abutability in tiled CMPs
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N
S
EW
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Over-the-cell routing
ISPD 2013 Tiled CMPs
Cache
Core
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500-1000 wires
Router
1000 wires 10 µm
Physical planning
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Simulation
AnalyticalModeling
L3 R
Local IC
L2CC L2C C
R
L3
L2
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PhysicalPlanning
Estimations:• Area• Wirelength• Routability
Floorplanner• Slicing structures & Simulated Annealing*• Lightweight maze router• Constraints:
– Adjacency (Core L2)– Balanced links (rings)– Maximum length for critical nets
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• D.F. Wong and C.L. Liu, “A New Algorithm for Floorplan Design”DAC 1986, pages 101-107.
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24 5
V
H H
V1 2 3
4 5
Wire planner• SAT-based approach for gridded routing• Grid unit: link width ( 500 - 1000 wires)• Customizable for any type of Boolean-encoded
constraints (abutability, 1D/2D routing, …)
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Top view
Cross-section view
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Filtering floorplans
320
330
340
350
360
370
380
390
400
100 101 102 103 104 105 106 107 108
Area
[mm
2]
Throughput [IPC]
Block areaBest floorplan
Best routable floorplan
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320
330
340
350
360
370
380
390
400
100 101 102 103 104 105 106 107 108
Area
[mm
2]
Throughput [IPC]
Block areaBest floorplan
Best routable floorplan
Area limit
After physical planning
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Conclusions• Physical planning has significant impact during
architectural exploration of tiled CMPs
• Future work:– New topologies (mesh of rings)– Multi-module memory floorplanning– Regularity and choppability
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