Physical Design

This is what we want

• Are amenable to fabrication with some given target process

• Logically function as expected in spite of numerous parasitic effects

• Meet ambitious performance goals in spite of layout parasitics

• Keep fabrication costs down by minimizing die size and by maximizing yield.

Common Problems

• Tolerances and misalignments of photomasks,• Wave diffraction and proximity effects,• Uneven profile together with shallow depth of focus,• Reflections from underlying layers,• Tolerances in photoresist exposure,• Etching along undesired dimensions,• Lateral diffusion of dopants, and• Spiking of aluminum.

Layout Rules

• Minimum Width• Minimum Intralayer Spacing• Minimum Interlayer Spacing• Minimum Enclosure• Minimum Extension

Min Width and Min Intralayer Spacing

Min Interlayer Spacing and Min Enclosure

Minimum Extension

Maximum Width

Density Rules

• Have to define a lower and upper density bound• No less than 20%, no more than 80% of 1mmx1mm• This method is used in CMP (Chemical Mechanical Polishing) to

prevent the errosion of two interconnecting surfaces of two materials of different hardness such as copper and Si02.

Electrical Properties

Surface has different materials of different electrical properties. So it’s necessary to define electrical characteristics.

• Conductivity• Sustainable Current Density

Conductivity

• Huge difference in conductivity between metal and silicon layers • If no Silicidation was present, the contrast would be even more

significant• Improved by using metal silicate or CoSi2 on the top of Si material

Sustainable Current Density

• The max amount of current that IC can handle is a matter of concern• Reliability concerns the current the device can handle• When subject to excess current, the metal conductors tend to

disintegrate named as electromigration• VLSI designers design interconnect networks to function as current

load

Connection Between Layers

Two types of connections

• ContactsConnection between metal and Si Layers

• ViaConnection between two superimposed layers of metal

350 mm CMOS 5 Layer

Contacts and Vias

Metal Layers

Typical Roles of Conducting Layers

• First level metal is instrumental can connect to all Si Layers without detour• Intermediate level are mostly used for general extra-cell signal inter

connect.• Higher level metals are thicker, lower sheet resistance.

Cell Based Back-End Design

Floorplanning

• Partitioning into major building blocks (datapaths, controllers, memories, megacells, etc.),• Number and anticipated sizes, shapes, and placement of all such blocks,• Package selection and pin/pad utilization,• Wide busses and electrically critical signals,• Clock domains (frequency, conditional vs. unconditional clocking),• Voltage domains (power dissipation, power density, local current

needs), and• On-chip power and clock distribution schemes.

Two types of PIN Design

• Core LimitedA larger core surrounded by few pads. Core size determines overall die size. Porting target to denser process might reduce core size i.e. Die size. Might not impact cost.

• Pad LimitedSmall core with large number of pads. The pad number determines necessary circumference thus the fixed die size which cannot be reduced later. This is the minimum defined size. Dense or less dense cannot reduce die size because core is small and unaffected, but has impact on cost.

Core and Pad Limited Floorplan

Establish Pin Budget

• Total pin count determines package selection and packaging costs• A good pinout accounts not only for on chip interconnect but also for

board level wiring• Arrange signal from different power level • Keep bus signal together• Provide ample return path for switching current• Make differential signals occupy adjacent pins

Place and Route Basics

• Floorplan predicts the future outcome of each individual block.• These individual blocks can be tested separately thanks to modern

EDA Suites.• We can decompose blocks into small sizes to manage and test with

separate personnel/teams.• Extra cells (sewing kits) are kept which are expected to require future

mods, we can make last minute changes to them without much divergence of the actualy floor plan itself.

Major Revision Necessary if

Inconsistency in • Power Dissipation• Long Path Delay• Area Coverage• Clock Speed

will force us to revise and change the major floorplan

Place and Route : These Are Done

Good routing makes a difference in fabrication yield. At the interconnect level, yield enhancement implies:• Connecting multiple vias in parallel.• Making the preferred orientations of wires on adjacent metal layers

perpendicular to each other to minimize the impact of crosstalk on path delays, both long and short.• Spacing long lines further apart than required by the minimum

separation rule to minimize the chance of shorts and the severity of crosstalk.

Chip Assembly

• Final phase of physical design• Place all top level building blocks• Interconnect those blocks to obtain chip’s core• Prepare the pad frame required to electrically connect the external

world• Connect core and pad frame to complete chip’s design

Packaging

Packaging Process 1

Packaging Process 2

Packaging Process 3

Packaging Rules

• Protect semiconductor dies against mechanical stress and other environmental attacks• Electrical connections with surrounding circuitry with a particular

emphasis on low impedance for power and ground nets.• Facilitate the handling of parts during shipping and board assembly.• Carry away the thermal power while keeping die at an acceptable

temperature.

Wafer Sorting

Wafer Testing

• A set of ultrafine needles firmly held in place by a probe card is lowered into the wafer until all needles establish electrical contact with the bonding pads of ic.• It determines that the connections are all working and the circuit

faults can be found out.• Takes 2 seconds to test each IC response, and defective chips are

inked.• All responses are recorded.

Probe Card

Backgrinding and Singulation

• Standard wafers are between 720 µm and 770 µm thick.• The wafer’s back surface is subjected to grinding by disks with

embedded diamond abrasives.• Final thickness can be as low as 75 µm, although most thin-wafer

production averages 250 µm to stay clear of yield losses during grinding, handling, and later packaging steps.• The wafer then gets sawn apart by two orthogonal series of parallel

cuts, each of which traverses the wafer from one rim to the opposite one.

Encapsulation

• In a step termed die bonding, aka die attach, a good die is placed in the cavity of the package, where it is mechanically fastened by means of solder or epoxy resin compound.• Next follows wire bonding, whereby electrical connections are

established between bond pads on the silicon die and their counterparts on the package leads.• Al and Au wires are used.• Bonding occurs by way of pressure, ultrasonic energy, and/or heat.

Bonding diagram and Bonding Rules

Instructions on how to connect the pads on the die to the available package leads during wire bonding:• are conveyed in a bonding diagram• Do not design dies with aspect ratios outside the interval [1 2 ...2].• Allow for a minimum gap of 0.6 mm between cavity and die on all four sides.• Make 25 µm bond wires no shorter than 1.0 mm and no longer than 3.5 mm.• Avoid downbonds, groundbonds, and double bonds.• Respect a minimum angle of 45 between bond wires and chip edge.• Make all bond areas square with a minimum overglass opening of 75 µm by 75 µm.• Respect a minimum pad pitch of 90 µm.

Advanced Packaging Techniques

High Performance Packages

• Implemented on chips which operate on Ghz Frequency and dissipate 150W

• Wire bonding is impractical in such situations.

• Conductive Polymer is used.

HighDensity Packaging

• Is used to reduce the IC size• High-density packaging uses similar techniques to mount and interconnect

bare dies — and often tiny SMD components as well — on a small substrate before encapsulating everything in a common package. • Even where this is technically feasible, combining many such features on a

single monolithic circuit implies a more complex fabrication process• The alternative is to have each subsystem manufactured with its respective

optimal technology and to have them tested separately before mounting them in a common package to obtain a multi-chip module (MCM)

Folded Flexiprints

• Particularly popular when a multi-chip circuit must fit into a small or irregular volume. Chips are fabricated, packaged, and tested in the normal way before being surface-mounted on a flexible film substrate. • Discrete components, sensors, and the like can also be

accommodated. The flexiprint is then cut and folded before being fit into a medical device

Chip Stacking and Cubing

• Hearing aids, mobile phones, and flash memories such as USB memory sticks take advantage of the third dimension by stacking two, three, or more dies on top of each other.• Cubing allows for still higher densities. Bare dies are stacked on top of

each other before being inter-connected on their outer rims to obtain a cube-like assembly. Burying the vertical interconnections within the chip stack itself is an extra sophistication.• Plasma etching is used.

Thank You