Phase-Locked Loop Design S emiconducto r S imulation L aboratory Phase-locked loops: Building blocks...

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Phase-Locked Loop Design S S emiconduc emiconduc tor tor S S imulation imulation L L aboratory aboratory Phase-locked loops: Building blocks in receivers and other communication electronics Main premise: Lock in to a frequency or phase component of an incoming signal and give a synchronized output Block diagram: Circuit Operation Phase Detector: Creates an output proportional to the phase difference between its input signals, the incoming data and the feedback signal. Loop Filter: A low pass filter; adds another pole to the feedback loop to control lock-in range and frequency. Voltage-Controlled Oscillator: Produces a clock signal whose frequency is proportional to its input voltage. Divide-by-N Counter: Feeds the output clock signal, its frequency divided by N, back to the PD. Closed Loop Gain: Phase-Locked Loops F VCO PD F VCO PD data clock K K K N s K K K s H 1 ) ( Phase Detector & Loop Filter: Schematic and Responses VCO Current Pump and the VCO: Schematic and Responses 50 100 150 200 250 0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 V in (V ) V C O _f(M Hz) Phase detector and the loop filter Transient responses for the phase detector and the loop filter Full VCO VCO, input voltage vs. frequency A VCO current pump VCO current pump, current vs. V in Design Specifications Design Goal Given a reference clock signal at 200 kHz, design a PLL whose output will oscillate in a range between 110 MHz to 130 MHz. •For the block diagram above, this requires a divide-by-N counter with N between 550 and 650. •Therefore we used a 10-bit binary downcounter. The inputs set the number it starts counting down from. The output of the VCO is the “count” signal for the counter. When the counter reaches zero, it is reloaded and sends a pulse to the phase detector. 10-bit Counter Schematics Phase-Locked Loop, Complete Circuit Phase-Locked Loop, Operation: Simulation Results Reference Clock and the Counter Output PD output to loop filter and loop filter output to VCO VCO outputs at the beginning of the simulation and after lock-in

Transcript of Phase-Locked Loop Design S emiconducto r S imulation L aboratory Phase-locked loops: Building blocks...

Page 1: Phase-Locked Loop Design S emiconducto r S imulation L aboratory Phase-locked loops: Building blocks in receivers and other communication electronics Main.

Phase-Locked Loop Design SSemiconducemiconductortorSSimulationimulationLLaboratoryaboratory

• Phase-locked loops: Building blocks in receivers and other communication electronics

• Main premise: Lock in to a frequency or phase component of an incoming signal and give a synchronized output

• Block diagram:

Circuit Operation•Phase Detector: Creates an output proportional to the phase difference between its input signals, the incoming data and the feedback signal.•Loop Filter: A low pass filter; adds another pole to the feedback loop to control lock-in range and frequency.•Voltage-Controlled Oscillator: Produces a clock signal whose frequency is proportional to its input voltage.•Divide-by-N Counter: Feeds the output clock signal, its frequency divided by N, back to the PD.•Closed Loop Gain:

Phase-Locked Loops

FVCOPD

FVCOPD

data

clock

KKKN

s

KKKsH

1)(

Phase Detector & Loop Filter: Schematic and Responses

VCO Current Pump and the VCO: Schematic and Responses

50

100

150

200

250

0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 1.3

Vin (V)

VC

O_f

(M

Hz)

Phase detector and the loop filter

Transient responses for the phase detector and the loop filter

Full VCO

VCO, input voltage vs. frequency

A VCO current pump

VCO current pump, current vs. Vin

Design Specifications

•Design Goal Given a reference clock signal at 200 kHz, design a PLL whose output will oscillate in a range between 110 MHz to 130 MHz.•For the block diagram above, this requires a divide-by-N counter with N between 550 and 650. •Therefore we used a 10-bit binary downcounter. The inputs set the number it starts counting down from. The output of the VCO is the “count” signal for the counter. When the counter reaches zero, it is reloaded and sends a pulse to the phase detector.

10-bit Counter Schematics

Phase-Locked Loop, Complete Circuit

Phase-Locked Loop, Operation: Simulation Results

Reference Clock and the Counter Output PD output to loop filter and loop filter output to VCOVCO outputs at the beginning of the simulation and after lock-in

Page 2: Phase-Locked Loop Design S emiconducto r S imulation L aboratory Phase-locked loops: Building blocks in receivers and other communication electronics Main.

FM Transceiver: Frequency-Modulation Transmitter and ReceiverFM Transceiver: Frequency-Modulation Transmitter and Receiver

LNAMatchingNetwork

AntennaMixer

LocalOscillator

PLL

CrystalFilter

IFA PAOutputSignal

FMDemodulator

A FM transceiver consists both FM transmitter and FM receiver where FM stands for “frequency modulation”. Transmitter and receiver are the basic building blocks in modern wireless communication systems. A transmitter modulates the information signal and transmits the modulated signal in form of electro-magnetic wave. A receiver, on the other hand, receives this modulated signal and demodulates it in which way the original information is recovered. Frequency modulation differs from amplitude modulation by reflecting the changing of the amplitude of the information signal to the frequency domain. The superheterodyne topology is used for high frequency solution.

We are working on the design and hardware implementation of a high-frequency FM transceiver. First, we try to investigate some of the design issues and thus improve the performance of the system. Second, we use this transmitter as the platform to test signal interference effects associated with the topology.

MatchingNetwork

Antenna

PAInputSignal

DCBias

VoltageAdder

VCO

RCNetwork

FM Modulator

Mixer

LocalOscillator

Receiver Chip LayoutReceiver Chip Layout

Transmitter PC Board DesignTransmitter PC Board Design

Design of High-Frequency FM TransceiverDesign of High-Frequency FM Transceiver

• FM Transmitter

The information signal is first added to a DC signal which enables the VCO (voltage controlled oscillator) to have the maximal operation linearity. The VCO acts as the FM modulator. The modulated signal is up-converted by the mixer to wanted carrier frequency. The PA (power amplifier) further increases the signal level which is transmitted by the antenna.

• FM Receiver

The modulated signal sent out by the transmitter is received by the antenna at the receiver end and is amplified by the LNA (low noise amplifier). The mixer down-converts this signal to intermediate frequency (IF), realizing the tuning function. The PLL (phase lock loop) demodulates the FM signal and thus the original information is recovered for processing.

Design NoteDesign Note

A High-Frequency FM Transceiver

• DC Bias: Voltage regulator that has very low output resistance.• VCO: Current Starved Ring Oscillator.• Power Amplifier: Class A cascade common-emitter amplifier with emitter degeneration and resonant load.• Antenna: Loop antenna with 50Ω radiant impedance.• LNA: Cascode amplifier with input matching and output buffer.• Mixer: Gilbert cell.• Local Oscillator: Colpitts oscillator.• PLL: Phase frequency detector, charge pump, loop filter, and VCO.