Phase locked loop
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Jan 24, 2009 Winter School on VLSI Systems Design ECE Department, ECE Department, NIT Durgapur NIT Durgapur Aniruddha Chandra ECE Department, NIT Durgapur, WB, India. <[email protected]> Phase Locked Loop Phase Locked Loop (PLL) (PLL)
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3 hour tutorial on phase locked loop.
Transcript of Phase locked loop
Jan 24, 2009
Winter School on VLSI Systems Design
ECE Department, ECE Department, NIT DurgapurNIT Durgapur
Aniruddha Chandra
ECE Department, NIT Durgapur, WB, India. <[email protected]>
Phase Locked Loop (PLL)Phase Locked Loop (PLL)
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VLSI Systems DesignOutlineOutline
Synchronization
PLL Basics
Analog PLL
Digital PLL
TDTL FPGA Implementation
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VLSI Systems DesignSynchronization ???Synchronization ???
In heavy traffic we are forced to match our speed to that of the car in front of us
and should also try to avoid sudden braking so as not to frighten the driver behind us.
Concept Attribute
Synchronization Frequency/ phase
Urban traffic Vehicle speed
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VLSI Systems DesignSynchronization ???Synchronization ???
In a symphony orchestra, the reference is the conductor, and all musicians attempt to reproduce the beat as set by the conductor’s baton.
Concept Attribute
Synchronization Frequency/ phase
Orchestra Scale of note
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VLSI Systems Design
Synchronization
We take it for granted
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VLSI Systems DesignSynchronizationSynchronization
What happens without it?
Exchange
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VLSI Systems DesignSynchronizationSynchronization
What happens without it?
Exchange
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VLSI Systems DesignSynchronizationSynchronization
What happens without it?
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VLSI Systems DesignSynchronization HierarchySynchronization Hierarchy
Coherent demodulation – phase/ frequency Non-coherent demodulation – frequencyMulti Carrier systems – sub-carrier
Carrier Synchronization
Symbol Synchronization
Frame Synchronization
Network Synchronization
Integrator, Decision device
Multiple access (TDMA), FEC (Block coding)
Transmitter synchronization – Satellite, GPS, CDMA
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VLSI Systems Design
Phase Locked Loop (PLL)
Building block for all synchronization system
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VLSI Systems DesignPLL - BasicsPLL - Basics
What is PLL?
PLL is a circuit synchronizing an output signal (generated by an oscillator) with a reference or input signal in the frequency as well as in phase.
This is the action of a PLL
Oscillator output Reference input
These look like pointless operations!
Track average phase (& frequency)/ period input
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VLSI Systems Design
Oscillator output Reference input
PLL - BasicsPLL - Basics
Oscillator output Reference input
PLL types
Phase and Frequency locked
coherent demodulation
Frequency locked, constant Phase difference
non-coherent demodulation
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VLSI Systems DesignPLL - ApplicationsPLL - Applications
Clock phase adjustment in μP
Time-to-Digital converters (TDC)
Frequency synthesis
Motor speed control
Frequency modulation/ demodulation
Jitter reduction, Skew suppression, Clock recovery
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VLSI Systems Design
1922-27: Oscillator synchronization - Appleton, VanderPol
1932: Publication on the PLL concept - H. de Bellescise
1932: British scientists develop the homodyne/ synchrodyne detection (AFC)
1943: PLL applied in TV - vertical and horizontal scan
1965: Analog PLL devices appeared
1970: Digital PLL introduced - IC 565, CD 4046
1980-90: All-digital PLL (ADPLL) was invented. Software controlled PLL (SPLL) became relity.
Turning the pages of HistoryTurning the pages of History
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VLSI Systems Design
Analog Phase Locked Loop (APLL)
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VLSI Systems DesignAnalog PLL (APLL)Analog PLL (APLL)
The components of a PLL: VCO, PD, and LF.
In synchronized or locked state, the phase error between the oscillator’s output and the reference signal is either zero or an arbitrary constant.
When phase error builds up, the oscillator is tuned by a control mechanism to reduce the phase error.
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VLSI Systems DesignAPLL - AnalysisAPLL - Analysis
tVtv 111 cos
tVtv 222 cos
The reference (or input signal)
The output signal of the VCO
with , where ωo is the centre frequency of
the VCO, Ko is the VCO gain, and vf (t) is the output signal of
loop filter
tvKt f002
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VLSI Systems Design
tte 21
tKtv edd
The phase error at PD
PD output signal , where Kd is the PD gain
vd (t) consists of a dc component and a superimposed ac component
vf (t) is delayed version of vd (t) with ac removed
APLL - AnalysisAPLL - Analysis
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VLSI Systems DesignAPLL – ComponentsAPLL – Components
Phase Detector (PD)
PD compares the phases of the input and output signals and generate an error signal proportional to the phase deviation.
A mixer (analog multiplier/ balanced modulator) generates the sums and differences of the frequencies at its input terminals.
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VLSI Systems DesignAPLL – ComponentsAPLL – Components
Phase Detector (PD)
Superior noise performance
Operates on the entire amplitude of the input and VCO signals rather than quantizing them to 1 bit
Best suited for PLL applications in the microwave frequency range as well as in low noise frequency synthesizers
Loop gain depends on signal amplitude
Non-linear response due to non-idealities in the circuit
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VLSI Systems DesignAPLL – ComponentsAPLL – Components
Voltage Controlled Oscillator (VCO)
VCO produces an oscillation whose frequency can be controlled through some external voltage.
VCO types
Ring oscillator - Odd number of inverters connected in a feedback loop.
Relaxation oscillator - Generates square wave using Schmitt trigger.
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VLSI Systems DesignAPLL – ComponentsAPLL – Components
VCO types (Contd.)
Resonant oscillator - Resonant circuit in the positive feedback path of a voltage to current amplifier.
A simple resonant circuit VCO, where the frequency is controlled by adjusting the reverse bias of the varactor diode C1
Crystal Oscillator
YIG Oscillator - YIG (Yttrium, Iron and Garnet) spheres, due to the ferrite properties, resonate at μ-wave frequencies when immersed in a magnetic field.
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VLSI Systems Design
Active lead-lag filterPassive lead-lag filter
Loop Filter
PLLs are mostly second order and as the VCO is modeled as an integrator, loop filters are of the lead-lag type.
More specifically, the loop filter contains an integrator which is able to track a phase ramp, and this corresponds to tracking a step in frequency.
APLL – ComponentsAPLL – Components
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VLSI Systems Design
Hold Range
The hold range, is defined as the frequency range over which the PLL is able to statically maintain phase tracking
APLL – Performance MetricsAPLL – Performance Metrics
Lock Range
The lock range, is defined as the frequency range within which the PLL locks within one single-beat note between the reference frequency and output frequency.
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VLSI Systems Design
Digital Phase Locked Loop (DPLL)
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VLSI Systems Design
Superiority in performanceAPLLs can’t operate at very low frequencies. The analog LPF struggles while extracting the lower frequency component, as it needs larger time for better frequency resolution.
SpeedSelf-acquisition of APLLs is often slow, while DPLLs can achieve locking within few cycles.
Reliability VCO is sensitive to temperature and power supply variations. Analog multipliers are sensitive to DC drifts.
Reduction in size and cost
Why DPLL?Why DPLL?
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VLSI Systems DesignDPLL DevelopmentDPLL Development
Sinusoidal Digital PLL (1970)
Digital tan-lock loop (1982)
Time-delay digital tan-lock loop
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VLSI Systems DesignDPLL SchematicDPLL Schematic
Digital PD
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VLSI Systems DesignDPLL – ComponentsDPLL – Components
Phase Error Detector (PED)
Classification based on PED type
1. Flip-flop DPLL
2. The Nyquist-rate DPLL
3. The lead-lag DPLL or, binary-quantized DPLL
4. Exclusive-OR DPLL
5. Zero-crossing DPLL
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VLSI Systems Design
Phase detector
Comparator - convert sinusoidal input into a square wave
Q output - duration when Q = 1 is proportional to phase error
Counter clock - frequency 2M × fo
fo = DCO center frequency
2M = number of quantization levels of the phase error over period of 2π
Flip-flop DPLLFlip-flop DPLL
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VLSI Systems Design
Phase detector
Counter - starts counting on the positive-going edge of the flip-flop waveform.
The content of the counter, No, which is proportional to the phase error, is applied to digital filter.
Flip-flop DPLLFlip-flop DPLL
The output of the digital filter K controls the period of the DCO
DCO - programmable divide- by-K counter
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VLSI Systems DesignDPLL – ComponentsDPLL – Components
Digital Controlled Oscillator (DCO)
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VLSI Systems Design
Binary SubtratorDCO Components Programmable counter
Binary subtractor
Zero detector
Digital Controlled Oscillator (DCO)Digital Controlled Oscillator (DCO)
When it reaches zero, the counter generates a pulse. This pulse is used to load the counter with M −K where K is input.
With each clock pulse counter decrements by one.
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VLSI Systems Design
DCO free-running frequency
fo = fc /M
where fc is the frequency of the counter clock.
Digital Controlled Oscillator (DCO)Digital Controlled Oscillator (DCO)
Binary Subtrator
The period between the (k−1)th and the kth pulse
T(k) = (M − K) Tc where Tc = 1/ fc
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VLSI Systems Design
Sinusoidal DPLL
Digital tan-lock loop (DTL)
Time-delay digital tan-lock loop (TDTL)
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VLSI Systems Design
Why DTL?
Sinusoidal DPLL - sensitive to the variations in the input signal power and rather limited lock range
Digital tan-lock loop (DTL)Digital tan-lock loop (DTL)
Components
90o phase shifter, 2 samplers, PED, digital loop filter, DCO
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VLSI Systems Design
Phase error at sampling instant is extracted by the tan−1 function. This phase error, modified by the digital filter, controls the period of DCO.
Digital tan-lock loop (DTL)Digital tan-lock loop (DTL)
Sampler I and II takes in-phase (I) and quadrature (Q) samples simultaneously.
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VLSI Systems Design
Why TDTL?
A digital Hilbert transformer introduces approximations and imposes limitations on the range of input frequencies, especially when implemented on a microprocessor.
Time-delay DTL (TDTL)Time-delay DTL (TDTL)
A constant time-delay may be used to produce a phase-shifted version of the incoming signal to reduce complexity.
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VLSI Systems DesignImproved TDTL - IImproved TDTL - I
The conflicting requirements of fast acquisition and widelocking range necessitate the inclusion of more than one time delay.
Variable delay TDTL (VD-TDTL)
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VLSI Systems DesignImproved TDTL - IIImproved TDTL - II
If a sudden change in input frequency drives the system to go outside the locking range, the system senses this error through the FSM and updates the gain of the digital filter to bring the operating point within the locking region
Adaptive gain TDTL (AG-TDTL)
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VLSI Systems DesignImproved TDTL - IIIImproved TDTL - III
Adaptive gain variable delay (AG-VD) TDTL
Combining the best of two - faster acquisition, wider locking range and more resilience to frequency drifts
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VLSI Systems Design
TDTL FPGA Implementation
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VLSI Systems Design
Xtreme DSP development board
Virtex-II XC2V3000 chip with three million gates
Virtex-II XC2V80 for clocking and I/O management
Spartan-II interface FPGA for communicating with PC using the PCI bus/ USB.
Xtreme DSP Development Kit-II powered by a Virtex-II FPGA chip from Xilinx.
PlatformPlatform
Xilinx System Generator serves as the software development platform. It consists of a Simulink library called the Xilinx Blockset, and software to translate a Simulink model into a hardware realization of the model.
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VLSI Systems DesignTDTL FPGA ImplementationTDTL FPGA Implementation
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VLSI Systems DesignCORDIC Arctangent BlockCORDIC Arctangent Block
The COordinate Rotational DIgital Computer (CORDIC) algorithm is an iterative method of calculating trigonometric and functions.
The CORDIC algorithm is used to implement the 4-quad tan−1(x / y) function of the phase detector, converging to angles between ± π within eleven system clock cycles.
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VLSI Systems DesignDCO BlockDCO Block
The disadvantage of using divide-by-k counter is poor frequency resolution.
The DCO is implemented using a Direct Digital Synthesis (DDS) block
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VLSI Systems Design
References
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VLSI Systems DesignRead more about thisRead more about this
S. R. Al-Araji, Z. M. Hussain, and M. A. Al-Qutayri, Digital Phase Lock Loops: Architectures and Applications, Springer, Dordrecht, Netherlands, 2006.
W. F. Egan, Phase-Lock Basics, Wiley InterScience, John Wiley & Sons, New York, 1998.
R. E. Best, Phase-Locked Loops: Design, Simulation, and Applications, McGraw-Hill, New York, 2003, 5th edition.
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VLSI Systems Design
M. Kihara, S. Ono, and P. Eskelinenesign, Digital Clocks for Synchronization and Communications, Artech House, Boston, London, 2003.
H. M. Berlin, Design of Phase-Locked Loop Circuits with Experiments, SAMS Publishers/ Longman Higher Education, 1978.
A. Blanchard, Phase-Locked Loops: Application to Coherent Receiver Design, Krieger Publishers, 1992.
F. M. Gardner, Phaselock Techniques, John Wiley & Sons, New York, 2005, 3rd edition.
Read Read eveneven more about this more about this
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VLSI Systems Design
Thank You!
Questions???
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