PHASE LOCK LOOPs

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This ppt contains description of a PLL by razavi.

Transcript of PHASE LOCK LOOPs

  • 1. PRESENTED BY:-PRESENTED TO:- Aman Jain (EC 08) Ravitesh Mishra Gourav Gupta (EC 38)A.P,BCE Mandideep Mohit Swarnkar ( EC 53) Narendra Singh Rajput (EC 57) Piyush Pal (EC66)28/02/2013Time taken: 24 minsAMAN JAIN Number of Slides : 19 1

2. Presentation Outline What is Phase Locked Loop (PLL) Parts of a PLL Locked Condition Dynamics of Simple PLL Transient Respone to PLL Application of PLL28/02/2013AMAN JAIN 2 3. What is Phase Locked Loop (PLL) PLL is an Electronic Module (Circuit) that locks the phase of the output to the input. A PLL is a negative feedback system where an oscillator-generated signal is phase and frequency locked to a reference signal.28/02/2013AMAN JAIN3 4. Parts of a PLL Phase Detector Filter Voltage Controlled Oscillator28/02/2013 MOHIT SWARNKAR4 5. Parts of a PLL Phase Detector Acts as comparator Produces a voltage proportional to the phase difference between input and output signal Voltage becomes a control signal28/02/2013MOHIT SWARNKAR 5 6. Implementation of PD Phase Detector is an XOR gate.28/02/2013MOHIT SWARNKAR 6 7. 28/02/2013 MOHIT SWARNKAR 7 8. Parts of a PLL Filter Determines dynamic characteristics of PLL Specify Capture Range (bandwidth) Specify Tracking Range Receives signal from Phase Detector and filters accordingly28/02/2013 NARENDRA SINGH RAJPUT8 9. Parts of a PLL Voltage Controlled Oscillator Set tuning range Set noise margin Creates low noise clock oscillation Wout = Wo+Kvco Vcont28/02/2013NARENDRA SINGH RAJPUT 9 10. Locked Condition Locked Conditiond/dt(in-out)=0This implies thatwin = wout28/02/2013 NARENDRA SINGH RAJPUT 10 11. Vi and Vout has at the same frequency W1 The phase detector must produce V1 Hence, VCO is dynamically changing and PD is creating VControl to adjust for the phase difference. The PLL is in the Locked state28/02/2013NARENDRA SINGH RAJPUT 11 12. Dynamics of Simple PLL PLL is a feedback systemPD is a gain amplifierLPF be first order filterVCO is a unit step module The transfer function of the feedback system is given as:28/02/2013 GOURAV KUMAR GUPTA 12 13. 28/02/2013 GOURAV KUMAR GUPTA 13 14. Transient Response to PLL The unit step response to second order system can be Overdamped Critically damped Underdamped Problems with this PLLSettling time Vs. ripple of VcontorStability of the systemLacks performance in ICs28/02/2013GOURAV KUMAR GUPTA 14 15. 28/02/2013 GOURAV KUMAR GUPTA 15 16. Application of PLL Frequency Multiplications The feedback loop has frequency division. Frequency division is implemented using a counter.28/02/2013 PIYUSH PAL16 17. Jitter Reduction Clock Skew Reduction Buffers are used to distribute the clock Embed the buffer within the loop28/02/2013PIYUSH PAL 17 18. Other applications include: Demodulation of both FM and AM signals Recovery of small signals that otherwise would be lost in noise (lock-in amplifier) Recovery of clock timing information from a data stream such as from a disk drive Clock multipliers in microprocessors that allow internal processor elements to run faster than external connections, while maintaining precise timing relationships DTMF decoders, modems, and other tone decoders, for remote control and telecommunications28/02/2013PIYUSH PAL18 19. THANK YOU28/02/2013 19