PRESENTED BY:- PRESENTED TO:- Aman Jain (EC 08) Ravitesh Mishra

Gourav Gupta (EC 38) A.P,BCE Mandideep

Mohit Swarnkar ( EC 53)

Narendra Singh Rajput (EC 57)

Piyush Pal (EC66)

Time taken: 24 mins AMAN JAIN Number of Slides : 19 128/02/2013

Presentation Outline

What is Phase Locked Loop (PLL) Parts of a PLL Locked Condition Dynamics of Simple PLL Transient Respone to PLL Application of PLL

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What is Phase Locked Loop (PLL)

PLL is an Electronic Module (Circuit) that locks the phase of the output to the input.

A PLL is a negative feedback system where an oscillator-generated signal is phase and frequency locked to a reference signal.

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Parts of a PLL

Phase Detector Filter Voltage Controlled Oscillator

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Parts of a PLL

Phase Detector Acts as comparator Produces a voltage proportional to the phase difference between input and output signal Voltage becomes a control signal

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Implementation of PD

Phase Detector is an XOR gate.

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Parts of a PLL

Filter Determines dynamic characteristics of PLL

Specify Capture Range (bandwidth) Specify Tracking Range

Receives signal from Phase Detector and filters accordingly

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Parts of a PLL

Voltage Controlled Oscillator Set tuning range Set noise margin Creates low noise clock oscillation

Wout = Wo+Kvco Vcont

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Locked Condition

Locked Condition

d/dt(φin-φout)=0

This implies that

win = wout

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Vi and Vout has at the same

frequency W1

The phase detector must

produce V1 Hence, VCO is dynamically

changing and PD is creating

VControl to adjust for the phase

difference. The PLL is in the Locked state

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Dynamics of Simple PLL

PLL is a feedback system

PD is a gain amplifier

LPF be first order filter

VCO is a unit step module The transfer function of the feedback system is given as:

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Transient Response to PLL

The unit step response to second order system can be

Overdamped

Critically damped

Underdamped

Problems with this PLL

Settling time Vs. ripple of Vcontor

Stability of the system

Lacks performance in ICs

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Application of PLL

Frequency Multiplications

The feedback loop has frequency division.

Frequency division is implemented using a counter.

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Jitter Reduction Clock Skew Reduction

Buffers are used to distribute the clock

Embed the buffer within the loop

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Other applications include:

Demodulation of both FM and AM signals Recovery of small signals that otherwise would be lost in noise (lock-in amplifier) Recovery of clock timing information from a data stream such as from a disk drive Clock multipliers in microprocessors that allow internal processor elements to run faster than external connections, while

maintaining precise timing relationships DTMF decoders, modems, and other tone decoders, for remote control and telecommunications

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1928/02/2013

THANK YOU