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Phase 2 Tracker R&D

Background:Initial work was in the context of the long barrel on local tracklet-based designs. • designs of support structures and PS modules based on 3D integrated

circuits. Including thermal testing and simulation.• Design of off-detector FPGA track formation logic which

accommodates 6.4 microsecond L1 accept• simulation of tracklet and track formation• Verilog design of the readout chip.• VICTR 3D chip prototyping and testing• Interposer development and testing• Active edge sensor R&DDecision to drop long barrel and restrict tracker geometry means that we have had to rethink our program.

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• After the meeting at Snowmass we expect that you will submit a short proposal to be evaluated and approved by CMS and US CMS. The proposal that you will submit to US CMS should provide a brief summary of:

• R&D Topic • People involved, percentage of time and job category (e.g.

engineer, technician, etc.• Breakdown of costs between materials, travel, fully loaded

salary (sal= ary + fringes + overhead) • Major accomplishments in FY13 (You can make a reasonable

extrapolation= to the end of FY13) • List of goals and deliverables for FY14

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Why this R&D is important to CMS

The track trigger and new tracker is the centerpiece of the CMS phase 2 upgrade. It is technically very difficult and success is not assured. We have unique experience, technologies and insight we can contribute.

Many ideas are different than current “baseline” designs. I hope this can provide a healthy discussion. I believe that there are significant flaws in the “baseline” designs presented at Hamburg, which are essentially copies of the current tracker.CMS has now established a set of global meetings on module design and track finding.

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Institutes

• Brown University– Chip testing – TSV chip, Double sided probing, – PCB or silicon interposer tests– Active edge testing – CV, VI, beam tests– Radiation tests

• Cornell– Track trigger design – simulation, chip design– Chip testing – VIP chip, pixel chip features, future test chips– Simulation– Active edge arrays – Test structure evaluation– Interconnect – PCB or silicon interposer

• Fermilab– Track trigger design– Chip testing– Chip design– Active edge arrays– Interconnect– Mechanics

• UC Davis– Mechanics – module support?– Interconnect – bump bonding, prototyping

• UC Santa Barbra– Chip design?

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Technical Challenge –PS Module design

• Spacing between layers will vary with radius and between barrel and disk modules

• We would like to continue to work on a design based on either TSVs or a PC board interposer that solves many of these problems

• Collaborating with CERN on development of a commercial TSV vendor in the US– Received wafers this week– Chip Testing at Cornell

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• Current PS module design needs considerable development to be thermally, mechanically and functionally acceptable

• It is essentially a pixel detector, so one sensor has to be bump bonded to readout chips– Cooling should have minimum

thermal impedance– Interconnections are needed

between chips to insure full coverage

– Z must cross between chips or incur dead regions

– Information from the bottom sensor has to be transmitted to the top (or vice-versa)

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Module

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Dummy ROICFlexfoldover

Carbon foamDummy sensors

Kaptonspacers

Carbon foam/flex based design

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Technical challenge-Track Finding

• The baseline tracker design is predicated on utilization of associative memories for track finding. The success of this technique is uncertain – depends on system design, data paths and throughput

• We plan to continue work on alternate ideas for off-detector track finding and collaborate on AM work– Examine ways to provide local tracking in a disk-barrel

design• Look at geometrical and design limitations of tracklet

designs• Explore alternate strategies for finding level 1 tracks

– Complete initial work on tracklet processor FPGA-based hardware, including track fitter which can be utilized in AM based designs

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L1 Tracking with TrackletsIn the LB context a very detailed emulation of a tracklet based track finding algorithm has been developed.

Processing done in 24 (15°) sector Extensive use of FPGA DSP capabilities

Firmware implementation (on GLIB) test platform underway at Cornell.Algorithm performance similar to a full floating point c2 calculation:

Floating point FPGA emulation

Work underway to understand how to extend algorithm to the BE geometry. Main challenge is in the larger separation between layers that give larger rate

of fake stubs.

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Technical Challenge-PS Readout Chip

• This chip puts an unprecedented level of intelligence in front end electronics – there are substantial challenges in integration with simulation, optimization, power efficiency

• Collaborating with CERN on chip design and simulation– Provide Monte Carlo simulation for detailed verification

• Data throughput, buffers, power consumption• Design is constrained by DC-DC converter power delivery

– Confirm functionality at the logic gate level (ongoing)• Compare CERN and FNAL designs• Look at issues like z ganging, inter-chip communication …

– Contribute to IC design logic blocks (pipeline stages…)– Continue chip testing

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Technical Challenge-Interconnect

• Explore PCB-based interposer design using flex circuit– Discussions with companies

on technologies and prototypes

– Understand requirements (via size, line width, layers) for successful layout

– Understand CTE issues• Explore TSV-based design which

does not have TSV issues, but requires to PCB interconnect

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Mechanics

• Need to discuss with tracker group how we can contribute beyond the long barrel rod design. – Carbon fiber part fabrication– Cooling tests utilizing CO2 facility– Overall rod supports– Carbon foam components

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Tiling Large area devices

A significant issue for the original long barrel design was the yield for a large (10x10) pixel module. This drove our current study of active tiles – which decouples yield and enables large area pixelated devices - This work is under way and the layers will be bonded this summer

- Will demonstrate the basic process including top wafer thinning and interconnect to “upside down” chip

- Cornell recently completed top wafer processing- Brown tested sensors

- However the layup is complex and the stack has to be background and etched to separate tiles.

There is a much easier wayR. Lipton

Handle wafer

sensor

trenches

Buriedoxide

readoutIC and pads200 micron

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• z

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• Bond ROIC to sensor wafer• Thin ROIC to 10 microns• Etch connections to ROIC Pads• Etch edges• Use ALD (NRL, UCSC)process to activate

edges

Plan: test the idea by trench processing sensor test structures From HPK or Micron, measuringLeakage current

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Feasibility - Time Scales

• PS module design + interconnectTest TSV structure

– 6 months – mechanical + thermal study– PCB prototypes – 9 months– Bonded stacks – 1.5 year

• Track Finding– 1 year – test stands at Cornell– 9 months study of tracklets in barrel disk

• Readout chip– Verilog design – 6 months– Prototypes – 2 years

• Mechanics– Module and support mockups and testing

• Active Edge– 9 months study dRIE on test structures– 1.5 years – full demonstration

• Radiation length test stand in Fermilab TB?R. Lipton