PEX 8619BA-AIC4U4D RDKPEX 8619BA-AIC4U4D RDK Hardware Reference Manual Version 1.1 November 2009...

PEX 8619BA-AIC4U4D RDK Hardware Reference Manual

Version 1.1

November 2009

Website: HHUwww.plxtech.comUH

Technical Support: Uwww.plxtech.com/supportU

Copyright © 2009 by PLX Technology, Inc. All Rights Reserved – Version 1.1 November 19, 2009

http://www.plxtech.com/

© 2009 PLX Technology, Inc. All rights reserved.

PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.

PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc.

Other brands and names are the property of their respective owners.

Order Number: PEX 8619AIC-RDK-HRM-1.1

November 19, 2009

PREFACE

NOTICE This document contains PLX Confidential and Proprietary information. The contents of this document may not be copied nor duplicated in any form, in whole or in part, without prior written consent from PLX Technology, Inc.

PLX provides the information and data included in this document for your benefit, but it is not possible to entirely verify and test all the information, in all circumstances, particularly information relating to non-PLX manufactured products. PLX makes neither warranty nor representation relating to the quality, content, or adequacy of this information. The information in this document is subject to change without notice. Although every effort has been made to ensure the accuracy of this manual, PLX shall not be liable for any errors, incidental, or consequential damages in connection with the furnishing, performance, or use of this manual or examples herein. PLX assumes no responsibility for damage or loss resulting from the use of this manual, for loss or claims by third parties, which may arise through the use of the RDK, or for any damage or loss caused by deletion of data as a result of malfunction or repair.

ABOUT THIS MANUAL This document describes the PLX PEX 8619BA-AIC4U4D, a Rapid Development Kit, from a hardware perspective. The contents of this document provide an accurate description of all aspects of this RDK board including a description of the major features and components, and details regarding the layout of the printed circuit board such as PCB mechanical outline, PCB stack-up, and component placement. This manual also includes complete schematics and bill of materials.

This Hardware Reference Manual is specific to the PEX 8619BA-AIC4U4D. In the event of a discrepancy between this Hardware Reference Manual and the PEX 8619 Data Book, please be sure to follow the instructions and guidelines as stated in the PEX 8619 Data Book when designing your systems.

REVISION HISTORY

Date Version Comments

April 2009 1.0 Hardware Reference Manual initial release.

November 2009 1.1 Updated Schematics and other miscellaneous edits.

REFERENCES • PLX Technology, Inc, www.plxtech.com

o PEX 8619 Data Book, Version 1.0

o PEX 8619 Quick Start Hardware Design Guide, Version 1.0

• PCI Special Interest Group (PCI-SIG), www.pcisig.com

o PCI Express Base Specification, Version 2.0

o PCI Express CEM Specification, Version 2.0

o PCI Express External Cabling Specification, Version 1.0

• Agilent Technologies, www.agilent.com

o Agilent Soft Touch Midbus Probe User’s Guide. April 2007

PEX 8619BA-AIC4U4D Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved iv

http://www.plxtech.com/http://www.pcisig.com/http://www.agilent.com/

CONTENTS NOTICE ..................................................................................................................................................... iv ABOUT THIS MANUAL ................................................................................................................................. iv

REVISION HISTORY ................................................................................................................................ iv REFERENCES ........................................................................................................................................ iv

1. System Architecture .......................................................................................................................... 1 2. Hardware Architecture ...................................................................................................................... 2

2.1 PCI Express Port Configurations .............................................................................................. 2 2.1.1 PEX 8619BA-AIC4U4D Port Configurations .......................................................................... 3 2.1.2 Additional PEX 8619BA-AIC4U4D Port Configurations Using x4 to x1x1x1x1 Breakout

Board(s) ................................................................................................................................. 9 2.1.3 Configuration Modules ......................................................................................................... 10 2.1.4 x4 to x1x1x1x1 Breakout Board ........................................................................................... 10

2.2 Direct Memory Access (DMA) Operation ................................................................................ 10 2.3 PCI Express Cable Support .................................................................................................... 11 2.4 Non-Transparent Operation .................................................................................................... 11 2.5 PCI Express Hot-Plug Circuitry ............................................................................................... 11 2.6 Reference Clock Circuitry ....................................................................................................... 11 2.7 Lane Status Indicator LEDs .................................................................................................... 12 2.8 Switches and Jumpers ............................................................................................................ 13

2.8.1 SW2 – Port Configuration .................................................................................................... 14 2.8.2 SW3 – Upstream Port Select ............................................................................................... 14 2.8.3 SW1 – Functional Strapping Selection ................................................................................ 14 2.8.4 SW4 – Non-Transparent Port Select ................................................................................... 15 2.8.5 SW6 – On-Board Voltage Generation Enable ..................................................................... 15 2.8.6 SW10 – Hot-Plug Control .................................................................................................... 15 2.8.7 SW8 – Hot-Plug Slot Address .............................................................................................. 15 2.8.8 JP11 – 3.3 Vaux Jumper ..................................................................................................... 15

2.9 Power Circuitry ........................................................................................................................ 16 2.10 Reset Circuit ............................................................................................................................ 16 2.11 Debug Mode Interface ............................................................................................................. 16 2.12 Serial EEPROM Interface ....................................................................................................... 18 2.13 JTAG Interface ........................................................................................................................ 18 2.14 I2C Interface ............................................................................................................................ 18 2.15 FATAL_ERR#, INTA#, PEX_NT_RESET# ............................................................................. 18

3. Board Layout Information ................................................................................................................ 19 3.1 Trace Routing Design Rules ................................................................................................... 19

3.1.1 Trace Width/Spacing Rules ................................................................................................. 19 3.1.2 Trace Length Matching Rules .............................................................................................. 19 3.1.3 Trace Length Restrictions .................................................................................................... 19

3.2 PCB Stack-up .......................................................................................................................... 19 4. Bill of Materials / Schematics .......................................................................................................... 20

PEX 8619BA-AIC4U4D Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved v

PEX 8619BA-AIC4U4D Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved vi

FIGURES Figure 1. Component Placement for PEX 8619BA-AIC4U4D ................................................................... 1 Figure 2. PCI Express Lane Numbering ................................................................................................... 2 Figure 3. PEX 8619BA-AIC4U4D – x4x4x4x4 Configuration .................................................................... 4 Figure 4. PEX 8619BA-AIC4U4D – x8x4x4 Configuration ........................................................................ 5 Figure 5. PEX 8619BA-AIC4U4D – x8x8 Configuration ........................................................................... 6 Figure 6. PEX 8619BA-AIC4U4D – x4x4x4-CABLEx4 Configuration ....................................................... 7 Figure 7. PEX 8619BA-AIC4U4D – x8x4-CABLEx4 Configuration ........................................................... 8 Figure 8. x8x4x1x1x1x1 Configuration.................................................................................................... 10 Figure 9. PEX 8619BA-AIC4U4D Reference Clock Block Diagram ....................................................... 12 Figure 10. PEX 8619BA-AIC4U4D Lane Status LEDs ........................................................................... 12 Figure 11. Hardware Strap Configuration Switches ................................................................................ 13 Figure 12. I2C Interface Footprints .......................................................................................................... 18 Figure 13. PEX 8619BA-AIC4U4D Stack-up .......................................................................................... 19

TABLES Table 1. PEX 8619BA-AIC4U4D Configurations Supported ..................................................................... 3 Table 2. PEX 8619BA-AIC4U4D Hardware Configurations ...................................................................... 3 Table 3. Additional PEX 8619AA-AIC4U4D Port Configurations .............................................................. 9 Table 4. PEX 8619AA-AIC4U4D Additional Hardware Configurations ..................................................... 9 Table 5. Signal Mapping of Debug Signals ............................................................................................. 16

1. System Architecture The PEX 8619BA-AIC4U4D is a PLX Rapid Development Kit intended primarily for use by PLX customers for silicon evaluation and design reference of the PEX 8619. The form factor is based on the PCI Express Card Electromechanical specification. The board is designed to work by plugging into a PCI Express compliant motherboard via a x8 PCIe card edge connector. Four Configuration Modules are used at two locations to provide the hardwire routing flexibility needed to support the required port configurations that are used on this board. The PEX 8619BA-AIC4U4D board supports non-transparent operation through a PCIe cable. Debug mode is available through two MICTOR connectors and one 2x10 pin header. Figure 1 below shows board layout and placement of major components for the PEX 8619BA-AIC4U4D board.

Power Connector

JTAG

PC

Ie C

AB

LEx4

J3

J2

J1

J4

P1

Con

figur

atio

n M

odul

e Configuration Module

MICTOR

MICTOR

PEX 8619

J1

J2

J3

P1

LANE 0

LANE 1

LANE 2

LANE 3

LANE 4

LANE 5

LANE 6

LANE 7

J4

Serial Hot Plug Ckt.

MAN PERST#

SYSERR

I2C

THERMDIODE

EEPROM

7.3 inch

7.25 inch

OPE

NO

PEN

OP

ENO

PENO

PEN

1 2 3 41 2 3 4

1 2 3 4 5 6 7 81 2 3 4 5 6

1 2

OPE

NO

PEN

1 2 3 41 2

Figure 1. Component Placement for PEX 8619BA-AIC4U4D

PEX 8619BA-AIC4U4D Hardware Reference Manual – Version 1.1 Copyright © 2009 by PLX Technology, Inc. All rights reserved 1

2. Hardware Architecture

2.1 PCI Express Port Configurations The PEX 8619BA-AIC4U4D supports the PEX 8619 device: a 16-lane, 16-port, non-blocking PCI Express switch, which can support both transparent and non-transparent modes of operation. Section 2.1.1 below describes the port configurations that the PEX 8619BA-AIC4U4D supports, and how these configurations are set-up.

In addition to these configurations, Section 2.1.2 below describes how additional port configurations can be set-up through the use of x4 to x1x1x1x1 breakout boards. These boards may be purchased separately (part name Breakout Board 1111).

The PEX 8619 device lane numbering is shown in Figure 2 below.

Figure 2. PCI Express Lane Numbering

Lanes 8 through 15 pass through an Agilent soft touch midbus probe footprint in order to monitor PCIe traffic. Refer to the Agilent Soft Touch Midbus Probe User’s Guide for further details of the headers. Lanes 0 through 3 are wired directly to card edge connector P1. Lanes 4 through 7 are routed to P1 or J3 by the Configuration Module on the right. Lanes 8 through 11 are routed to J1, J2, or J4 by the Configuration Module on the left. Lanes 12 through 15 are wired directly to J1. The board routing is such that connections to connectors J1 through J4 rely on lane reversal. Only connector P1 does not use lane reversal.


2.1.1 PEX 8619BA-AIC4U4D Port Configurations The PEX 8619BA-AIC4U4D is designed to support the port configurations shown in Table 1 below.

Table 1. PEX 8619BA-AIC4U4D Configurations Supported

Config P1 J1 J2 J3 J4

x4x4x4x4 Default Configuration X4 – Port 0 X4 – Port 3 X4 – Port 1 X4 – Port 2

x8x4x4 X8 – Port 0 X4 – Port 3 X4 – Port 1

x8x8 X8 – Port 0 X8 – Port 1

x4x4x4-Cablex4 X4 – Port 0 X4 – Port 3 X4 – Port 2 X4 – Port 1

x8x4–Cablex4 X8 – Port 0 X4 – Port 3 X4 – Port 1

Table 2, below, describes how the PEX 8619BA-AIC4U4D is hardwire configured to support these five configuration modes, and points to the appropriate Figure showing how the routing occurs.

Table 2. PEX 8619BA-AIC4U4D Hardware Configurations

Config Left Config Module Used Right Config Module Used

SW2 Settings Routing Figure

x4x4x4x4 Default Configuration -0107 -0108

LHLL Figure 3

x8x4x4 -0107 -0107 LHHH Figure 4

x8x8 -0110 -0107 HLLL Figure 5

x4x4x4-Cablex4 -0111 -0108 LHLL Figure 6

x8x4-Cablex4 -0111 -0107 LHHH Figure 7


Figure 3. PEX 8619BA-AIC4U4D – x4x4x4x4 Configuration


Figure 4. PEX 8619BA-AIC4U4D – x8x4x4 Configuration


Power Connector

JTAG

PC

Ie C

ABLE

x4

J3

J2

J1 – Port 1

J4

P1 – Port 0

PEX 8619

J1

J2

J3

P1

LANE 0

LANE 1

LANE 2

LANE 3

LANE 4

LANE 5

LANE 6

LANE 7

J4

Module -0107M

odul

e -0

110

OP

ENO

PEN

OP

EN

1 2 3 41 2 3 4

1 2 3 4 5 6 7 81 2 3 4 5 6

1 2

OP

ENO

PEN

SW

2

CLOSED = LOWCLOSED = LOWCLOSED = LOWOPEN = HIGH

Figure 5. PEX 8619BA-AIC4U4D – x8x8 Configuration


Figure 6. PEX 8619BA-AIC4U4D – x4x4x4-CABLEx4 Configuration


Figure 7. PEX 8619BA-AIC4U4D – x8x4-CABLEx4 Configuration


2.1.2 Additional PEX 8619BA-AIC4U4D Port Configurations Using x4 to x1x1x1x1 Breakout Board(s) Through the use of a x4 to x1x1x1x1 Breakout Board (purchased separately, part name Breakout Board 1111), the PEX 8619AA-AIC4U4D can support the additional port configurations shown in Table 3 below.

Table 3. Additional PEX 8619AA-AIC4U4D Port Configurations

Config P1 J1 J2 J3 J4

x8x4x1x1x1x1 x8 – Port 0 x1x1x1x1 –

Ports 15, 13, 11, 3

x4 – Port 1

Table 4 below describes how the PEX 8619AA-AIC4U4D is hardwire configured to support these three additional configuration modes, and points to the appropriate Figure showing how the routing occurs.

Table 4. PEX 8619AA-AIC4U4D Additional Hardware Configurations

Config Left Config Module Used Right Config Module Used

Number of Breakout Boards

SW2 Settings

Routing Figure

x8x4x1x1x1x1 -0107 -0107 1 LHHL Figure 8


Breakout x4 to x1x1x1x1

x1

x1

x1

x1

Power Connector

JTAG

J3

J2 – Port 1

J1 – Ports 15, 13, 11, 3

J4

P1 – Port 0

PEX 8619

J1

J2

J3

P1

LAN

E 0

LAN

E 1

LAN

E 2

LAN

E 3

LAN

E 4

LAN

E 5

LAN

E 6

LAN

E 7

J4

Module -0107

PC

Ie C

AB

LEx4

Mod

ule

-010

7

OP

EN

OP

EN

OP

EN

1 2 3 41 2 3 4

1 2 3 4 5 6 7 81 2 3 4 5 6

1 2

OP

EN

OP

EN

SW

2

CLOSED = LOW

OPEN = HIGHCLOSED = LOW

OPEN = HIGH

PEX8619 RDK

PEX8619

End Point

End Point

End Point

Bre

akou

t Boa

rd

End Point

End Point

Figure 8. x8x4x1x1x1x1 Configuration

2.1.3 Configuration Modules Two Configuration Modules are used on the board. The configuration modules consist of a 10x20 ball board-to-board high-speed connector, with one half of the connector mounted on the PEX 8619BA-AIC4U4D, and the other half mounted on a small 4-layer PCB that performs the re-mapping. There are no other components. Four different configuration modules are required. A 3-pin interface on the modules communicates their function to the board. The default configuration of the PEX 8619BA-AIC4U4D Rapid Development Kit provides one -0107 and one -0108 configuration module. Additional modules can be purchased separately.

2.1.4 x4 to x1x1x1x1 Breakout Board The x4 to x1x1x1x1 Breakout Board is a board that can be purchased separately, part name Breakout Board 1111. This board takes four lanes from its male card edge connector and routes each lane to its own female slot connector. PCIe REFCLK from the male card edge connector goes to a 1:4 fan-out buffer, which is driven to each of the female slot connectors. PERST#, 3.3VAUX, and WAKE# are passed from the card edge connector to each of the female slot connectors.

2.2 Direct Memory Access (DMA) Operation The PEX 8619 device provides DMA functionality with its internal DMA engine. The DMA engine supports four independent DMA channels and it is implemented as a separate function on the upstream port; making it completely independent from the transparent switch function. The DMA function implements an endpoint


configuration header (Type 0) and requires a software driver. The software driver provides access to the DMA internal registers in order to configure, start and monitor DMA transfers. The DMA software driver for the PEX 8619 is included in the Software Development Kit (SDK) available from PLX. Please contact technical support for additional information on the SDK.

2.3 PCI Express Cable Support The PEX 8619BA-AIC4U4D is meant to demonstrate PCI Express cable usage. The cable connection, J4, is hardware configurable so that it can act as a downstream port. The board adheres to the downstream subsystem requirements as outlined in the PCI Express External Cabling Specification Rev 1.0 for a x4 cable, with the following exceptions: none of the optional features are implemented, and CREFCLK is not dual 50 ohm terminated to ground. This means that only the lanes, and CPRSNT#, are implemented. Other side-band signals, such as CREFCLK and CPERST#, are not. The PCI Express cable connection can be used to demonstrate non-transparent operation to an NT host PC, see Section 2.4 for further details.

2.4 Non-Transparent Operation The PEX 8619BA-AIC4U4D board is capable of routing Lanes 8 through 11 to a x4 PCI Express cable connector, J4. This, in conjunction with a cable adapter board, permits connection to a second computer to demonstrate non-transparent operation. There is a specific power-up sequence that must be followed. The host PC must be powered-up before the NT host PC. If the host PC is running spread-spectrum clocking, then SSC isolation must be enabled. The NT host PC cannot be running spread-spectrum clocking. If it is, then a second PEX 8619BA-AIC4U4D with SSC isolation enabled must be used in place of the cable adapter board in the NT host PC to provide clock isolation. The PEX_NT_RESET signal from the PEX 8619 device is brought out to a test point via.

Note: Please refer to the PEX8619 Errata document for updates on the SSC isolation function.

2.5 PCI Express Hot-Plug Circuitry The PEX 8619 device supports Hot-Plug through a serial Hot-Plug interface brought out through I2C port 1. Only slot connector J1 supports Hot-Plug. The PEX 8619BA-AIC4U4D supports Hot-Plug to connector J1 via an IO expander IC. The lower 3 bits of the I2C address are pulled low through resistors to give a 7-bit I2C address to the IO expander of 38h. The two power rails to this slot (3.3VDC and 12VDC) are current limited to 5 amps. Hot-Plug control of this slot can be disabled by setting switch SW10-1 to CLOSED (LOW), so that this slot is always on. The MRL# signal is simulated by switch SW10-2. Switch block SW8 sends the Hot-Plug port address to the PEX 8619 device. The INTERLOCK signal from the PEX 8619 device is brought out to a test point via.

2.6 Reference Clock Circuitry The PEX 8619BA-AIC4U4D has circuitry to support SSC isolation. Refer to the PEX 8619BA Quick Start Hardware Design Guide for details on how spread-spectrum clock isolation is implemented in the PEX 8619 device.

The RefClk from the host PC is brought onto the board via card edge connector P1. This clock is assumed to be spread-spectrum. This clock drives a 1:2 clock fan-out buffer. One of these fan-out clocks goes to the PEX 8619 device’s PEX REFCLK input. The other fan-out clock goes to a 2:1 mux. The other input to this mux is from an onboard constant frequency clock generator. The output from this mux drives a 1:4 clock fan-out buffer, such as SpectraLinear’s CY28400-2 device. The outputs from this fan-out buffer drive the downstream connectors. From the 1:4 fan-out buffer, one of these clocks is routed to connector J1 and can be enabled/disabled by the serial Hot-Plug circuit. If the Hot-Plug control is disabled, this clock is always enabled. Two of the clocks are routed to connectors J2 and J3 and are always enabled. The fourth clock is routed to a 3-pin header associated with using the midbus soft-touch probe. A second onboard constant frequency clock generator drives the PEX REFCLK CFC input to the PEX 8619 device. Refer to Figure 11 below.


http://www.plxtech.com/8618http://www.plxtech.com/8618

Figure 9. PEX 8619BA-AIC4U4D Reference Clock Block Diagram The clock into the PEX 8619 device’s PEX REFCLK input drives all SerDes when SSC ISOLATION is disabled. In this case the downstream slots must also be driven by this clock. When SSC ISOLATION is disabled, the on-board circuitry turns off the CFC clock into the 2:1 mux, and sets the 2:1 mux to pass the RefClk from P1 to the downstream connectors by way of the 1:4 fan-out buffer.

When using SSC ISOLATION, the clock into the PEX 8619 device’s PEX REFCLK input only drives the SerDes for Port 0. In this case Port 0 CAN ONLY BE x4 or x8, and Port 0 must be an upstream port or an NT port. The clock into the PEX 8619 device’s PEX REFCLK CFC input drives the remaining SerDes. The downstream slots must also be driven by this constant frequency clock. When SSC ISOLATION is enabled, the on-board circuitry turns off the SSC from the 1:2 fan-out buffer into the 2:1 mux, and sets the 2:1 mux to pass the CFC from the on-board generator to the downstream connectors by way of the 1:4 fan-out buffer.

2.7 Lane Status Indicator LEDs The status of each PCIe lane can be monitored by a bank of green LEDs driven by the PEX 8619 device’s lane status balls. This bank of indicators are grouped in the upper right corner of the RDK board. Blinking indicates Gen 1 speeds, solid indicates Gen 2 speeds. Refer to Figure 12 below.

Figure 10. PEX 8619BA-AIC4U4D Lane Status LEDs


2.8 Switches and Jumpers The PEX 8619 has a number of strap pins which provide the capability to perform various types of hardware initialization without the use of software. Some strap pins are brought out to DIP switches, including the PORT_CFG strap pins. When the DIP switch is CLOSED, the value is LOW. When the switch is OPEN, the value is HIGH. Other strap pins that are not used in typical situations are strapped using pull-up/pull-down resistors. Strap pins I2C_ADDR[2:0] are pulled low, and STRAP_TESTMODE[3:0] are pulled high, through resistors.

Figure 11. Hardware Strap Configuration Switches


2.8.1 SW2 – Port Configuration

PORTCFG[3:0] Port Configuration Default RDK

LHLL x4x4x4x4 Yes LHHH x8x4x4 - HLLL x8x8 - LHHL x8x4x1x1x1x1 -

All Others Reserved -

2.8.2 SW3 – Upstream Port Select

Default is Port 0. Upstream port and NT port cannot be the same port.

2.8.3 SW1 – Functional Strapping Selection

FAST-BRINGUP# Factory Test Only. Keep HIGH(OPEN)

RSVD17# Factory Test Only. Keep HIGH(OPEN) PLL-BYPASS# Factory Test Only. Keep HIGH(OPEN)

SSC-ISO-EN# Default is HIGH(OPEN). LOW(CLOSED) Enables spread-spectrum clocking isolation. Refer to Section 2.6 for details.

DEBUG-EN Default is LOW(CLOSED). HIGH(OPEN) isolates the debug signals from on-board circuitry (Lane Status LEDs, etc.) so they only go to the debug headers. Refer to Section 2.11 for details.

SERDES-EN# Default is HIGH(OPEN). LOW(CLOSED) Enables SerDes debug mode. If Enabled, DEBUG-EN needs to be HIGH(OPEN).

PROBE-EN# Default is HIGH(OPEN). LOW(CLOSED) Enables Probe debug mode. If Enabled, DEBUG-EN needs to be HIGH(OPEN). DEBUG-SEL0 Factory Test Only. Keep HIGH(OPEN)


2.8.4 SW4 – Non-Transparent Port Select

Default is NT Port 1, with Non-Transparent disabled. Upstream port and NT port cannot be the same port. Location 6 on DIP Switch SW4 is unused.

2.8.5 SW6 – On-Board Voltage Generation Enable

Default is all HIGH(OPEN). When LOW(CLOSED), these switches turn off the on-board voltage generation for the PEX 8619 device in order to use external voltage supplies to the PEX 8619 device for voltage margining and current measurement tests.

2.8.6 SW10 – Hot-Plug Control

SHP EN Default is HIGH(OPEN). When HIGH(OPEN) the PEX 8619 controls the Hot-Plug slot. When LOW(CLOSED) the Hot-Plug slot is always turned on. MRL# Default is LOW(CLOSED). This switch mimics the Manual Retention Lever signal.

2.8.7 SW8 – Hot-Plug Slot Address

OP

EN

1 2 3 4

Default is all LOW(CLOSED). These switches transmit the Hot-Plug slot address back to the PEX 8619 device.

2.8.8 JP11 – 3.3 Vaux Jumper Default is NOT installed. The PEX 8619BA-AIC4U4D is meant to support WAKE functionality. Therefore, 3.3 Vaux is routed from card edge connector P1 to the downstream slot connectors. However, some slots that the PEX 8619BA-AIC4U4D is plugged into may not support 3.3 Vaux, and some add-in cards require 3.3 Vaux. In this case this jumper is installed to route 3.3 VDC from the card edge connector P1 to 3.3 Vaux of the downstream slot connectors.


2.9 Power Circuitry The PEX 8619BA-AIC4U4D is an add-in board. Power to the on-board circuitry is derived from PCIe card edge connector P1. Power to the PCIe slot connectors J1, J2, and J3 is from hard disk drive connector P2. A 4-pin, straight mount, HDD power connector is used.

Dedicated power rails supply the 1.0VDC and 2.5VDC voltages to the PEX 8619 device only. This permits accurate current draw measurements when operating in various port configurations and traffic levels. Test points are available to attach external power supplies to provide the 1.0VDC (TP1 for 1.0VDC, TP2 for GND) and 2.5VDC (TP3 for 2.5VDC, TP4 for GND). This permits current draw measurements and voltage margining of the PEX 8619 device voltages. When using external supplies, onboard voltage generators need to be disabled by switch SW6. Bi-color red/green LED indicators are used to indicate when 1.0VDC is within 5%, and 2.5VDC is within 10%.

Power to PCIe slot J1 can be controlled by the Hot-Plug circuit.

2.10 Reset Circuit The PEX 8619BA-AIC4U4D accepts a PERST# from the host PC via card edge connector P1. This signal is OR’d with a manual reset circuit. The manual reset circuit consists of a pushbutton (SW7, upper left corner) that feeds into a reset timer. The reset timer monitors its power rail and reset input. If the reset input is low or the supply rail is out of range, the reset output is held. Once both conditions no longer exist, the reset output will de-assert after a programmable reset timeout period (capacitor adjustable, default value 128 msec). The OR’d reset signal goes to the PEX 8619 device’s PEX_PERST# input pin, and the downstream slots’ PERST# connector pins. PERST# to Slot J1 can be controlled by the PEX 8619 device’s Hot-Plug interface.

2.11 Debug Mode Interface The PEX 8619BA-AIC4U4D supports the use of probe mode and SerDes debug mode through two MICTOR connectors and one 2x10 pin header. The MICTORs are high-speed connectors that deliver probe mode signals from the PEX 8619 device. The 2x10 pin header delivers selection signals to the PEX 8619 device. Probe mode signals are multiplexed onto other package balls that, in normal operation, deliver low speed signals for things like lane status. Table 5 provides a description of the signal mapping of the debug signals to the debug mode headers.

Note: Inputs are marked in blue, outputs are marked in red.

Table 5. Signal Mapping of Debug Signals Ball Name Probe Mode SerDes Debug Mode Connection

STRAP_NT_UPSTRM_PORTSEL2 stn_sel SW4-pin3 STRAP_DEBUG_SEL0 mod_sel3 In_sel3 JP7-pin19, JP8-pin7, SW1-pin8

STRAP_UPCFG_TIMER_EN# mod_sel2 rcvr_dat18 JP7-pin17, JP8-pin9 STRAP_SMBUS_EN# mod_sel1 In2_add1 JP7-pin15, JP8-pin11

STRAP_SPARE0# mod_sel0 In2_add0 JP7-pin11, JP8-pin13 I2C_ADDR2 port_sel3 In_sel0 JP7-pin3, JP8-pin21, R125-pin1

GPIO30 port_sel2 In_sel2 JP7-pin5, JP8-pin19 GPIO29 port_sel1 In_sel1 JP7-pin7, JP8-pin17

STRAP_NT_UPSTRM_PORTSEL3 port_sel0 JP7-pin9, JP8-pin15, SW4-pin4 GPIO3 outA_sel3 rx_status0 JP7-pin14, JP8-pin14 GPIO2 outA_sel2 JP7-pin16, JP8-pin12 GPIO1 outA_sel1 JP7-pin18, JP8-pin10 GPIO0 outA_sel0 JP7-pin20, JP8-pin8

I2C_ADDR1 outB_sel3 JP7-pin4, JP8-pin22, R123-pin1 I2C_ADDR0 outB_sel2 JP7-pin6, JP8-pin20, R84-pin1

GPIO5 outB_sel1 rx_status2 JP7-pin10, JP8-pin18 GPIO4 outB_sel0 rx_status1 JP7-pin12, JP8-pin16

STRAP_SPARE1# ext_trig_in rcvr_polarity JP7-pin2, JP8-pin24 PEX_LANE_GOOD15# prb_outA17 rcvr_dat17 JP9-pin38


Ball Name Probe Mode SerDes Debug Mode Connection PEX_LANE_GOOD14# prb_outA16 rcvr_dat16 JP9-pin36 PEX_LANE_GOOD13# prb_outA15 rcvr_dat15 JP9-pin34 PEX_LANE_GOOD12# prb_outA14 rcvr_dat14 JP9-pin32 PEX_LANE_GOOD7# prb_outA13 rcvr_dat13 JP9-pin22 PEX_LANE_GOOD6# prb_outA12 rcvr_dat12 JP9-pin20 PEX_LANE_GOOD5# prb_outA11 rcvr_dat11 JP9-pin18 PEX_LANE_GOOD4# prb_outA10 rcvr_dat10 JP9-pin16

GPIO15 prb_outA9 rcvr_dat9 JP8-pin38 GPIO14 prb_outA8 rcvr_dat8 JP8-pin36 GPIO13 prb_outA7 rcvr_dat7 JP8-pin34 GPIO12 prb_outA6 rcvr_dat6 JP8-pin32 GPIO11 prb_outA5 rcvr_dat5 JP8-pin30 GPIO10 prb_outA4 rcvr_dat4 JP8-pin28 GPIO9 prb_outA3 rcvr_dat3 JP8-pin26 GPIO8 prb_outA2 rcvr_dat2 JP8-pin31 GPIO7 prb_outA1 rcvr_dat1 JP8-pin29 GPIO6 prb_outA0 rcvr_dat0 JP8-pin27

GPIO25 prb_outB17 xmit_dat17 JP9-pin25 GPIO24 prb_outB16 xmit_dat16 JP9-pin23 GPIO23 prb_outB15 xmit_dat15 JP9-pin21 GPIO22 prb_outB14 xmit_dat14 JP9-pin19 GPIO21 prb_outB13 xmit_dat13 JP9-pin17 GPIO20 prb_outB12 xmit_dat12 JP9-pin15 GPIO19 prb_outB11 xmit_dat11 JP9-pin13 GPIO18 prb_outB10 xmit_dat10 JP9-pin11 GPIO17 prb_outB9 xmit_dat9 JP9-pin9 GPIO16 prb_outB8 xmit_dat8 JP9-pin7

PEX_LANE_GOOD11# prb_outB7 xmit_dat7 JP9-pin30 PEX_LANE_GOOD10# prb_outB6 xmit_dat6 JP9-pin28 PEX_LANE_GOOD9# prb_outB5 xmit_dat5 JP9-pin26 PEX_LANE_GOOD8# prb_outB4 xmit_dat4 JP9-pin24 PEX_LANE_GOOD3# prb_outB3 xmit_dat3 JP9-pin14 PEX_LANE_GOOD2# prb_outB2 xmit_dat2 JP9-pin12 PEX_LANE_GOOD1# prb_outB1 xmit_dat01 JP9-pin10 PEX_LANE_GOOD0# prb_outB0 xmit_dat0 JP9-pin8

N/C on ball T1 sclk/2 rclk/2 JP8-pin5 STRAP_NT_P2P_EN# trig_out trig_out JP8-pin37

STRAP_SPARE5# rcvr_dat19 JP8-pin23 GPIO27 xmit_dat19 JP8-pin35 GPIO26 xmit_dat18 JP8-pin33

Due to signal integrity concerns, the probe mode interface is placed near, and directly attached to, the PEX 8619 device. A CPLD provides isolation between the PEX 8619 device and the onboard circuitry that these signals would drive when the PEX 8619 device is in normal operation. When in debug mode, the CPLD blocks these signals from being propagated by setting switch SW1-pin5 (DEBUG-EN) to OPEN (HIGH). Please contact PLX when using the Debug Mode Interface.


2.12 Serial EEPROM Interface The PEX 8619BA-AIC4U4D provides a socketed Serial EEPROM. The contents of the serial EEPROM can be used to initialize the PEX 8619 device after power-on reset. PLX’s Software Development Kit (SDK) can be used to read from or write to the EEPROM.

2.13 JTAG Interface The PEX 8619BA-AIC4U4D has a dedicated JTAG header (JP2) to the PEX 8619 device. The header provides connections for TDI, TDO, TMS, TCK, TRST# and GND. This connector is right angle and accessible through the bulkhead bracket.

2.14 I2C Interface The PEX 8619 device provides a two-wire I2C compatible slave mode interface with three bit addressing. Through this out-of-band channel, the users can read, write, and configure the PEX 8619 device internal registers, run internal output probe mode, monitor error counters, and monitor status. There is no “standard” I2C header pin arrangement; therefore, I2C header type and pin assignments are somewhat arbitrary. A 2x2 pin header is used with a silkscreen outline to represent how an Aardvark controller would connect. See Figure 14 below. The upper 4 bits of the 7-bit I2C address have a default value of 0111. The lower 3 bits of the 7-bit I2C address are determined by external pull-up/pull-down resistors. The default I2C address provided by the 8619BA-AIC4U4D is 38h. PLX’s Software Development Kit (SDK) can be used to access the PEX 8619 device through the I2C interface.

Pin

3 =

SD

AP

in 2

= G

ND

Pin

4 =

NC

Pin

1 =

SC

L

Figure 12. I2C Interface Footprints

2.15 FATAL_ERR#, INTA#, PEX_NT_RESET# The PEX 8619 device has a number of chip-specific side band signals that are intended for various uses. The FATAL_ERR# output (legacy SERR# equivalent) is used to indicate that the PEX 8619 device detected a fatal unrecoverable error. The INTA# output is used to be compatible with PCI. The PEX_NT_RESET# output is used to indicate an in-band Reset from an NT host. These three signals are brought out to test point vias, so that a customer can access these pins. The FATAL_ERR# signal also drives a red LED indicator. The INTA# signal also drives a yellow LED indicator.


3. Board Layout Information

3.1 Trace Routing Design Rules

3.1.1 Trace Width/Spacing Rules There should be at least a 20-mil gap from the outer edge of one pair to the outer edge of another pair. PCI Express pairs are routed on the outer layers as much as possible, other signal traces are routed on outer and inner layers. The differential pairs are routed as loosely coupled pairs, 6-mil width, with 42.5 ohm single ended impedance, 85 ohm differential impedance.

3.1.2 Trace Length Matching Rules The two traces of a differential pair are length matched within 5-mil. Because the pairs are loosely coupled, only the total length of the two halves need to be closely matched. We don’t need to match each segment on a given layer for pairs that route on multiple layers. Differential pairs that form a common link are matched pair-to-pair within 3-inches.

3.1.3 Trace Length Restrictions Differential pairs being routed from the PEX 8619 device to the slot connectors should not exceed 8-inches in length.

3.2 PCB Stack-up The PEX 8619 is an 8 layer, 62-mil thick PCB. Refer to Figure 15 below.

Figure 13. PEX 8619BA-AIC4U4D Stack-up

This stack up includes 2 outer routing layers for much of the differential signaling, 2 inner layer signal planes for low speed or static single-ended signals and additional differential signaling, 3 ground planes adjacent to these to provide controlled impedance of the differential signals, and a split power plane to deliver the required voltages. Plane capacitance decoupling of the powers occurs between layers 4 and 5.


4. Bill of Materials / Schematics Item

# Qty Man. Man. Part # Description Package Type Reference Distributor Distributor

Part # Part

SURFACE MOUNT COMPONENTS

1 63 Kemet C0402C104K8PACTU CAP .10UF 10V CERAMIC

X5R 0402 SMT, 0402

C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11,

C12, C13, C14, C15, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C61, C62, C63, C64, C85, C86, C87, C88, C89, C90, C91, C92, C93, C94,

C95, C96, C97, C104, C110, C111, C115, C116, C121, C127, C132, C135, C141, C143, C144, C145,

C146

Digi-Key 399-3027-1-ND 0.1uF

2 8 AVX TAJC226K020R CAP TANTALUM 22UF 20V 10% SMD EIA size C C33, C34, C35, C36, C37,

C38, C39, C40 Digikey 478-1711-1-

ND 22uF

3 10 Kemet C0603C105K8PACTU CAP CERAMIC 1.0UF 10V

X5R 0603 SMT, 0603 C41, C42, C43, C44, C57,

C58, C59, C60, C120, C142

Digi-Key 399-3118-1-ND 1uF

4 28 Panasonic ECJ-ZEB1E102K CAP 1000PF 25V

CERAMIC X7R 0201 SMT, 0201

C45, C46, C47, C48, C49, C51, C52, C53, C54, C55, C56, C65, C66, C67, C69, C70, C71, C72, C73, C74, C75, C76, C77, C78, C79,

C80, C81, C83

Digi-Key PCC2130CT-ND 1000pF

5 4 Panasonic ECJ-3YB1C106M

CAP 10UF 16V CERAMIC X5R 1206 LOVOLT

FOOTPRINT

SMT, 1206, LoVolt C100, C108, C128, C140 Digi-Key

PCC2227CT-ND 10uF

6 2 Kemet C0603C105K8PACTU CAP CERAMIC 1.0UF 10V

X5R 0603, 2 VIA SMT, 0603, 2via C101, C109 Digi-Key 399-3118-1-

ND 1uF

7 2 Kemet C1206C226K9PACTU

CAP 22UF 6.3V CER X5R SMD 1206 LOVOLT

FOOTPRINT

SMT, 1206, LoVolt C102, C103 Digikey

399-3229-1-ND 22uF

8 2 Panasonic ECJ-1VB1H473K CAP .047UF 50V

CERAMIC X7R 0603 SMT, 0603 C105, C114 Digi-Key PCC2286CT-

ND 0.047uF

9 2 Panasonic ECJ-0EB1E102K CAP 1000PF 25V

CERAMIC 0402 SMD SMT, 0402 C122, C147 DigiKey PCC102BQC

T-ND 1000pF

10 12 Panasonic ECJ-0EB1C103K CAP 10000PF 16V

CERAMIC 0402 SMD SMT, 0402 C123, C124, C125, C126, C129, C130, C133, C134, C136, C137, C138, C139

DigiKey PCC103BQCT-ND 0.01uF

11 4 Kemet C0603C180J5GACTU CAP CERAMIC 18PF 50V

NP0 0603 SMT, 0603 C148, C149, C150, C151 Digi-Key 399-1052-1-

ND 18pF


Item # Qty Man. Man. Part # Description Package Type Reference

Distributor Distributor Part Part #

12 29 Lumex SML-LXT0805GW-TR LED THIN 565NM GRN

DIFF 0805 SMD SMT, 0805

DS1, DS2, DS3, DS4, DS5, DS6, DS7, DS8,

DS9, DS10, DS11, DS12, DS13, DS14, DS15, DS16, DS17, DS18, DS19, DS20, DS22, DS23, DS24, DS25, DS26, DS27, DS28, DS29,

DS35

Digi-Key 67-1553-1-ND Green

13 2 Lumex SML-LXT0805YW-TR LED THIN 585NM YEL

DIFF 0805 SMD SMT, 0805 DS30, DS36 Digi-Key 67-1554-1-ND Yellow

14 2 Lumex SML-

LXT0805SRW-TR

LED THIN660NM SUPRED DIFF0805SMD SMT, 0805 DS31, DS34 Digi-Key 67-1555-1-ND Red

15 2 CML Innovative Technologies CMD15-

22SRUGC/TR8 LED, RED/GREEN HI BRT

S TYPE SMD, If=20mA DS32, DS33 Digi-Key L6221115CT-

ND LED_BI

16 2 Amp 767054-1 CONN, 38-pin MICTOR, RECPT, STRAIGHT MICTOR38 JP8, JP9 MICTOR 38

RECEPT

17 1 Molex 87767-0123 PCI Express x16 straddle-mount connector SMT, 164-pin J1 PCI_EXP_X16_STRADDLE_MNT_CONN

18 1 Molex 75586-0011 Connector, Right-angle receptacle, PCIe x4 Cable SMT, PCIe x4

Cable J4 Mouser 538-75586-

0011 PCIe x4 Cable

19 2 FCI 84517-101LF Header, BGA, 10x20, recept, Pb Free 84517 J5,J6 84517-101

20 2 International Rectifier IRF7470 MOSFET, N-CHAN, 10A,

Rds=13 mohm SO8 Q1, Q2 IRF7470

21 4 ON Semiconductor MMBT3904LT1 NPN, GPSS, MMBT3904,

SOT23 Q3, Q4, Q5, Q6 MMBT3904LT

1

22 7 CTS Resistor Products 742-083-512-J RESNET, MF, 5.1 KOHM

NIL 5%, ISOLATED 742-CTS-RN-8 RN1, RN2, RN3, RN4,

RN5, RN7, RN8 Digi-Key 742C083512J

CT-ND 5.1K

23 4 Panasonic ERJ-3EKF1431V RES 1.43K OHM 1/10W 1% 0603 SMD SMT, 0603 R1, R2, R3, R4 Digi-Key P1.43KHCT-

ND 1.43K

24 21 Yageo 9C06031A0R00JLHFT RES 0.0 OHM 1/10W 5%

0603 SMD SMT, 0603

R5, R6, R8, R9, R10, R14, R15, R77, R97, R98, R99, R106, R108, R177, R179, R135, R140, R142, R159,

R164, R167

Digi-Key 311-0.0GCT-ND 0

25 4 Panasonic ERJ-3GEYJ102V RES 1.0K OHM 1/10W 5%

0603 SMD SMT, 0603 R7, R16, R17, R18 Digi-Key P1.0KGCT-

ND 1K


0603 SMD SMT, 0603

R11, R12, R13, R21, R22, R23, R24, R25, R48, R60, R66, R67, R75, R76, R84,

R85, R86, R103, R104, R105, R107, R109, R110, R118, R123, R125, R127, R128, R131, R138, R139, R144, R145, R158, R161, R163, R168, R170, R178,

R180, R22, R23, R24, R25, R84, R123, R125

Digi-Key P5.1KGCT-ND 5.1K



Distributor Distributor Part Part # 27 1 Panasonic ERJ-3GEYJ152V

RES, Shunt Select Footprint, 0603 SMT, 0603-2 R19 Digi-Key

P1.5KGCT-ND 1.5K

28 3 Panasonic ERJ-3GEYJ103V RES 10K OHM 1/10W 5%

0603 SMD SMT, 0603 R20, R30, R31 Digi-Key P10KGCT-ND 10K

29 4 Panasonic ERJ-3EKF2261V RES 2.26K OHM 1/10W 1% 0603 SMD SMT, 0603 R26, R27, R28, R29 Digi-Key P2.26KHCT-

ND 2.26K

30 35 Panasonic ERJ-3GEYJ391V RES 390 OHM 1/10W 5%

0603 SMD SMT, 0603

R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R49, R50, R51, R52, R54, R55, R56, R57, R58, R59, R61, R62, R63, R64, R71, R72, R82, R83, R120

Digi-Key P390GCT-ND 390

31 3 Panasonic ERJ-3GEYJ151V RES 150 OHM 1/10W 5%

0603 SMD SMT, 0603 R53, R94, R95 Digi-Key P150GCT-ND 150


0603 SMD SMT, 0603 R65 Digi-Key P33KGCT-ND 33K


0603 SMD SMT, 0603 R68 Digi-Key P27KGCT-ND 27K

34 1 Panasonic ERJ-3EKF4001V RES 4.00K OHM 1/10W 1% 0603 SMD SMT, 0603 R69 Digi-Key P4.00KHCT-

ND 4.00K

35 2 Panasonic ERJ-3EKF1001V RES 1.00K OHM 1/10W 1% 0603 SMD SMT, 0603 R70, R79 Digi-Key P1.00KHCT-

ND 1.00K


ND 6.81K


ND 14.3K


ND 1.50K


ND 12.1K


ND 4.53K


0603 SMD SMT, 0603 R87 DigiKey P1.3KGCT-

ND 1.3K


ND 28.0K


ND 4.99K

44 2 Panasonic ERJ-3GEYJ330V RES, CF, 33 OHM, 1/16W,

5%, 0603 SMD SMT, 0603 R90, R93 Digi-Key P33GCT-ND 33


ND 3.48K


ND 2.00K



Distributor Distributor Part Part # 47 2 TTelectronics LR2512-01-R020-F Res. 2W, 0.02 ohm 1% SMT, 2512 R100, R102 Mouser

66-LR2512-01-R040-F 0.02


0603 SMD SMT, 0603 R111 Digi-Key P1.5KGCT-

ND 1.5K

49 3 Yageo 9C08052A0R00JLHFT RES 0.0 OHM 1/8W 5%

0805 SMD SMT, 0805 R114, R149, DS21 Digi-Key 311-0.0ACT-

ND 0

50 16 Panasonic ERJ-1GEF49R9C RES 49.9 OHM 1/20W 1%

0201 SMD SMT, 0201

R115, R116, R119, R121, R136, R137, R146, R147, R152, R153, R156, R157, R166, R169, R174, R175

Digi-Key P49.9ABCT-ND 49.9


0603 SMD SMT, 0603 R117, R122 Digi-Key P2.7KGCT-

ND 2.7K

52 2 Panasonic ERJ-2RKF4750X RES 475 OHM 1/16W 1%

0402 SMD SMT, 0402 R129, R182 Digi-Key P475LCT-ND 475

53 12 Panasonic ERJ-1GEF33R2C RES 33.2 OHM 1/20W 1%

0201 SMD SMT, 0201 R130, R133, R141, R143, R150, R151, R154, R155, R160, R162, R172, R173

Digi-Key P33.2ABCT-ND 33.2

54 2 Panasonic ERJ-3EKF4750V RES 475 OHM 1/16W 1% 0603 SMD SMT, 0603 R148, R171 Digi-Key P475HCT-ND 475

55 4 Panasonic ERJ-2RKF33R2X RES 33.2 OHM 1/16W 1%

0402 SMD SMT, 0402 R185, R186, R189, R190 Digi-Key P33.2LCT-ND 33.2

56 2 Omron B3S-1002 SWITCH TACT 6MM SMD MOM 230GF SW7, SW9 Digikey SW416-ND B3S-1002

57 1 PLX Technology PEX8619-BA50BCG IC, PCI Express Switch, Gen 2, 16 Lane, DMA U1 PEX 8619

58 1 Maxim MAX6658 IC, Temperature Sensor, SMBus-Compatible, SO8 SO8 U3 MAX6658

59 1 Lattice LCMXO256C-3TN100C IC, CPLD TQFP100 U4 LCMXO256C-

3TN100C

60 2 Belfuse S7AH-08E1A00 IC, Non-iso DC/DC converter, 12V-to-1V @ 8A SMT, 7-pin

Belfuse U5, U10 S7AH-

08E1A00

61 1 Maxim MAX8556ETE IC, V-REG, 4 A, ADJ, Enable, POK Thin QFN16 U6 MAX8556

62 1 Intersil ISL6132IR IC, MULTI-VOLTAGE SUPERVISOR L24.4x4 U7 ISL6132

63 1 Maxim MAX6412UK29-T

IC, Reset controller, 2.9V threshold, Adj. reset

timeout SOT23-5 U8 MAX6412

64 1 Fairchild NC7SZ08P5X IC, AND Gate, Tpd=15nsec, 24mA SC70-5 U9 NC7SZ08

65 1 TI TPS2311IPW IC, DUAL HOT SWAP CONTROLLER TSSOP20 U11 TPS2311

66 1 Maxim MAX7311AUG IC, 2-WIRE, 16-BIT IO EXPANDER TSSOP24 U12 MAX7311AU

G



Distributor Distributor Part Part # 67 2 SpectraLinear CY28400OXC-2 IC, 1:4 100MHz Differential Clock Fanout SSOP28 U16, U18 CY28400-2

68 1 Maxim MAX4906

IC, Bus Switch, Dual SPDT, Ron=4 ohm typ, BW=1.0 GHz, Con=4pF

typ

uDFN10 U17 MAX4906

69 2 Fairchild NC7SZ04P5X IC, NOT GATE SC70-5 U19, U22 NC7SZ04P5X

70 2 On Semiconductor NB3N3002D IC, Crystal-to-HCSL Clock

Generator, OE TSSOP16 U23, U24 NB3N3002

THROUGH-HOLE COMPONENTS 100 4 Vishay 94SP187X0016EBP CAP, Oscon, 180uF, 16V E case C98, C99, C106, C107 180uF

101 1 Tyco Electronics Amp 5103310-1 CONN HEADER LOPRO

R/A 10POS 15AU 0.1" 2x5 RA JP2 Digi-Key A33179-ND JTAG Header

102 2 3M 929710-10-02 CONN HEADER .100 DUAL STR 4POS 0.1" 2x2 JP3,JP4 Digi-Key 929710-10-

02-ND HEADER 2X2

103 1 3M 929400-01-36

HEADER, Lattice Programming, 1x8

VERTICAL, .1in THRU-HOLE

0.1" 1x8 JP6 Digi-Key 929400-01-36-ND Lattice JTAG

104 1 3M 929710-10-10 CONN HEADER LOPRO STR 20POS 15AU 0.1" 2x10 JP7 Digikey 929710-10-

10-ND

PRB MODE INPUT

HEADER

105 1 3M 929400-01-36 HEADER, 1x2

VERTICAL, .1in THRU-HOLE

SIP-2 JP11 DigiKey 929400-01-36-ND JUMPER

106 2 Molex 87715-3302 PCI Express x16 Through-hole connector TH, 164-pin J2,J3 PCI_EXP_X16_FEMALE_C

ONN

107 1 Molex 74540-0400 Guide house, for 4x link

PCIe external cable connector

TH, PCIe x4 Cable J4 Mouser

538-74540-0400

108 1 Molex 15-24-4449 Header, HD 4-pin, straight P2 Arrow IDE4_HEADER

109 1 Grayhill 76SB08T SWITCH 8POS DIP EXT ROCK UNSEALD DIP16 SW1 Digi-Key GH7177-ND SW DIP-8

110 3 Grayhill 76SB04T SWITCH 4POS DIP EXT ROCK UNSEALD DIP8 SW2, SW3, SW8 Digi-Key GH7170-ND SW DIP-4

111 1 Grayhill 76SB06T SWITCH DIP EXT RCKR UNSEALD 6POS DIP12 SW4 Digi-Key GH7174-ND SW DIP-6

112 2 Grayhill 76SB02T SWITCH DIP EXT ROCKER 2POS TH DIP4 SW6, SW10 Digi-Key GH7115-ND SW DIP-2

113 1 Mill-Max 210-93-308-41-001000 Socket, EEPROM, DIP8,

Thru-hole DIP8 U2 Digi-Key ED60000-ND AT25128A

114 2 Citizen HC49US25.000MABJ-UB CRYSTAL 25.000 MHZ

HC49/US 2-pin thru-hole Y1, Y2 25MHz

115 4 Components Corporation TP-101-10-T Test Point Post TP1, TP2, TP3, TP4 TP-101-10-T



Item # Qty Man. Man. Part # Description Package Type Reference Distributor

Distributor Part # Part

MANUALLY INSERTED COMPONENTS 200 1 Atmel AT25128A-10PI-2.7

IC SRL EE 128K 2.7V 8DIP DIP-8 U2 Digi-Key

AT25128A-10PI-2.7-ND AT25128A

201 1 PLX Technology 91-0107-000-A CONFIGURATION MODULE, A3-to-B3 J5 0107

202 1 PLX Technology 91-0108-000-A CONFIGURATION MODULE, A3-to-A2 J6 0108

203 1 Amp 881545-2 SHUNT LP W/HANDLE 2 POS 30AU JP11 Digi-Key A26242-ND

MISCELLANEOUS COMPONENTS 300 1 Keystone Electronics 9203 Modified PCI bracket Mouser 534-9203

301 1 Building Fasteners PMSSS 440

0025 PH Phillips Panhead screw, 4-

40 thread, 0.25" Digi-Key H703-ND

302 1 PLX Technology 90-0101-000-A PCIe 16 LANE SWITCH RDK PCB, GEN2, Rev 000 PARTS SHOULD NOT BE ASSEMBLED

1 Agilent E5387-68701 Header, Midbus LAI Probe Shroud PCIe MIDBUS JP1 Midbus LAI

1 Yageo 9C06031A0R00JLHFT RES 0.0 OHM 1/10W 5%

0603 SMD SMT, 0603 R165 Digi-Key 311-0.0GCT-

ND 0

4 Panasonic ERJ-2RKF33R2X RES 33.2 OHM 1/16W 1%

0402 SMD SMT, 0402 R183, R184, R187, R188 Digi-Key P33.2LCT-ND 33.2

2 Maxim DS4100H+ IC, HCSL Oscillator, 100 MHz LCCC10 U20,U21 DS4100H

2 Kemet C0402C104K8PACTU CAP .10UF 10V CERAMIC

X5R 0402 SMT, 0402 C112, C113 Digi-Key 399-3027-1-

ND 0.1uF

1 Samtec TMS-103-02-S-S HEADER, RefClk, 3-pin, 0.05" TMS-103-02-S-S JP10 TMS-103-02-

S-S SECOND SOURCE / ALTERNATIVE PARTS

2 On Semiconductor NB3N5573D IC, Crystal-to-HCSL Clock

Generator, OE, Dual TSSOP16 U23, U24 NB3N5573

1 Maxim MAX8557ETE IC, V-REG, 4 A, ADJ, Enable, POR Thin QFN16 U6 MAX8557

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

91-0126-000-A 000

PEX8619 RDK - Functional Block Diagram

PLX Technology, Inc.870 W. Maude AvenueSunnyvale, CA 94085www.plxtech.com

C

1 10Monday, January 19, 2009

Title


Date: Sheet of

91-0126-000-A 000



C


Title


Date: Sheet of

91-0126-000-A 000



C


1 Functional Block Diagram2 Board Layout Information3 SWITCH_PCIe_Interface4 PCIe Connectors5 SWITCH_Power_Strapping6 Switches_Indicators_CPLD7 Power8 Hot Plug9 Probe Mode Interface10 PCIe Clocks

Sheet # Title

Schematic Table of Contents

PEX 8619

EEPROMJTAGI2CSTRAPPINGSWITCHES

CONFIG MODULE - J5

CONFIG MODULE - J6

CARD EDGE CONNECTOR - P1

LANES 0-3

LANES 4-7LANES 8-11

LANES 12-15

J1 - X4 OR X8 - HOT PLUG CAPABLE

J2 - X4 ONLY

J3 - X4 ONLY

J4 - X4 ONLY

P1 - X4 OR X8

1:2FANOUT

REFCLK

CONSTANTFREQUENCYCLOCK SOURCE

CFCCLK

2:1MUX

CONSTANTFREQUENCYCLOCK SOURCE

1:4FANOUT

TO HOT-PLUG SLOT J1

TO SLOT J2

TO SLOT J3

TO PROBE HEADER JP10

CLOCK CIRCUIT

12V TO1.0V

3.3V TO2.5V

1.0VDD

2.5VDD

3.3 V BOARD POWER

12 V BOARD POWER

HOT PLUGCONTROLCIRCUIT

5V TO3.3V

P2

3.3V TO SLOTS

12V TO SLOTSEXTERNALSUPPLY

SERIALHOT PLUGINTERFACE

January 19, 2009 First board build000

Revision History

Rev. # Date Reason for Revision

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of

91-0126-000-A 000

PEX8619 RDK - Board Layout Information


C

2 10Tuesday, January 20, 2009

Title


Date: Sheet of

91-0126-000-A 000



C


Title


Date: Sheet of

91-0126-000-A 000



C


PREPREG, Er=4.0, 4.5 mi/�

L6, SIGNAL 3

L1, SIGNAL 1

L2, GND

L3, SIGNAL 2

L4, GND

L5, POWER

PREPREG, Er=4.0, 3.5 mils


LAMINATE, Er=4.0, 5.0 mils


L8, SIGNAL 4



L7, GND

BoardThickness = 63 mils

LAYER STACKUP

OUTERTRACES

INNERTRACES

WIDTH = 6.0 milsCu = 1.50 ozDIFF Trace Zo = 85 ohm

WIDTH = 6.0 milsCu = 0.50 ozDIFF Trace Zo = 85 ohm

NL = No Load

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

C_PEX_TX0_pC_PEX_TX0_n
















PEX_RX0_pPEX_RX0_n

PEX_RX1_pPEX_RX1_n

PEX_RX2_pPEX_RX2_n

PEX_RX3_pPEX_RX3_n

PEX_RX4_pPEX_RX4_n

PEX_RX5_pPEX_RX5_n

PEX_RX7_pPEX_RX7_n

PEX_RX8_pPEX_RX8_n

PEX_RX9_pPEX_RX9_n

PEX_RX10_pPEX_RX10_n


PEX_RX6_pPEX_RX6_n

PEX_TX8_pPEX_TX8_n

PEX_TX9_pPEX_TX9_n

PEX_TX10_pPEX_TX10_n





PEX_TX15_pPEX_TX15_n PEX_RX15_p

PEX_RX15_n






PEX_RX9_pPEX_RX9_n

PEX_RX8_pPEX_RX8_n

PEX_TX4_pPEX_TX4_n

PEX_TX5_pPEX_TX5_n

PEX_TX6_pPEX_TX6_n

PEX_TX7_pPEX_TX7_n

PEX_RX10_p

PEX_RX11_p

PEX_RX10_n

PEX_RX11_n

PEX_TX8_p

PEX_TX8_n

PEX_TX9_p

PEX_TX9_n

PEX_TX10_p

PEX_RX8_p

PEX_TX10_n

PEX_RX8_n

PEX_TX11_p

PEX_RX9_p

PEX_TX11_n

PEX_RX9_n

PEX_RX6_p

PEX_RX7_p

PEX_RX6_n

PEX_RX7_n

PEX_TX4_p

PEX_TX4_n

PEX_TX5_p

PEX_TX5_n

PEX_TX6_p

PEX_RX4_p

PEX_TX6_n

PEX_RX4_n

PEX_TX7_p

PEX_RX5_p

PEX_TX7_n

PEX_RX5_n

PEX_TX0_p {4}PEX_TX0_n {4}




PEX_RX0_p {4}PEX_RX0_n {4}





PEX_RX15_n {4}PEX_RX15_p {4}







PEX_REFCLK_CFCp{10}PEX_REFCLK_CFCn{10}

PEX_REFCLKp{10}PEX_REFCLKn{10}

J2_PEX_RX8_p{4}J4_PEX_RX8_p{4}J1_PEX_RX8_p{4}

J2_PEX_TX8_p {4}

J2_PEX_RX8_n{4}

J4_PEX_TX8_p {4}

J4_PEX_RX8_n{4}

J2_PEX_TX8_n {4}J1_PEX_TX8_n {4}

J1_PEX_RX8_n{4}

J4_PEX_TX8_n {4}

J2_PEX_RX9_p{4}

J2_PEX_TX9_p {4}

J4_PEX_RX9_p{4}

J1_PEX_TX9_p {4}J4_PEX_TX9_p {4}

J1_PEX_RX9_p{4}

J2_PEX_TX9_n {4}

J2_PEX_RX9_n{4}

J1_PEX_TX9_n {4}J4_PEX_TX9_n {4}

J4_PEX_RX9_n{4}

J2_PEX_TX10_p {4}

J1_PEX_RX9_n{4}

J1_PEX_TX10_p {4}J4_PEX_TX10_p {4}

J2_PEX_RX10_p{4}

J2_PEX_TX10_n {4}

J4_PEX_RX10_p{4}

J1_PEX_TX10_n {4}

J1_PEX_RX10_p{4}

J4_PEX_TX10_n {4}

J2_PEX_TX11_p {4}

J2_PEX_RX10_n{4}

J1_PEX_TX11_p {4}

J4_PEX_RX10_n{4}

J4_PEX_TX11_p {4}

J2_PEX_TX11_n {4}

J1_PEX_RX10_n{4}

J1_PEX_TX11_n {4}

J2_PEX_RX11_p{4}

J4_PEX_TX11_n {4}

J1_PEX_TX8_p {4}

J4_PEX_RX11_p{4}J1_PEX_RX11_p{4}

J2_PEX_RX11_n{4}J4_PEX_RX11_n{4}J1_PEX_RX11_n{4}

P1_PEX_RX4_p{4}J3_PEX_RX4_p{4}

P1_PEX_TX4_p {4}

P1_PEX_RX4_n{4}J3_PEX_RX4_n{4}

P1_PEX_TX4_n {4}J3_PEX_TX4_n {4}



J3_PEX_TX4_p {4}




P1_PEX_TX5_p {4}J3_PEX_TX5_p {4}







MOD2_PRSNT#{6}MOD2_CONFIG0{6}MOD2_CONFIG1{6}

MOD1_PRSNT#{6}MOD1_CONFIG0{6}MOD1_CONFIG1{6}

Title


Date: Sheet of

91-0126-000-A 000

PEX8619 RDK - PCIe INTERFACE


C


Title


Date: Sheet of

91-0126-000-A 000



C


Title


Date: Sheet of

91-0126-000-A 000



C


C140.1uF C140.1uF

C150.1uF C150.1uF

C200.1uF C200.1uF

C210.1uF C210.1uF

C270.1uF C270.1uF

R21.43K1%

R21.43K1%

C260.1uF C260.1uF

TPV1TPV1

C320.1uF C320.1uF

C40.1uF C40.1uF

C50.1uF C50.1uF

C110.1uF C110.1uF

C100.1uF C100.1uF

C160.1uF C160.1uF

C170.1uF C170.1uF

C10.1uF C10.1uF

TPV2TPV2

C220.1uF C220.1uF

TPV3TPV3

C230.1uF C230.1uF

C280.1uF C280.1uF

C290.1uF C290.1uF

TPV4TPV4

JP1

NL

JP1

NL

TX0+1TX0-3 RX0+ 4

RX0- 6

GND 2

GND 8RX1+ 10RX1- 12GND 14

RX2+ 16RX2- 18GND 20

RX3+ 22RX3- 24GND 26

RX4+ 28RX4- 30GND 32

RX5+ 34RX5- 36GND 38

RX6+ 40RX6- 42GND 44

RX7+ 46RX7- 48

GND5TX1+7TX1-9GND11TX2+13TX2-15GND17TX3+19TX3-21GND23TX4+25TX4-27GND29TX5+31TX5-33GND35TX6+37TX6-39GND41TX7+43TX7-45GND47

R31.43K1%

R31.43K1%

C60.1uF C60.1uF

C70.1uF C70.1uF

C120.1uF C120.1uF

C130.1uF C130.1uF

C190.1uF C190.1uF

R11.43K1%

R11.43K1%

TPV5TPV5

PEX 8619

U1A

PEX 8619

PEX 8619

U1A

PEX 8619

PEX_PETp0 U8

PEX_PETp1 U9

PEX_PETp2 U11

PEX_PETp3 U12

PEX_PETp4 L18

PEX_PETp5 K18

PEX_PETp6 H18

PEX_PETp7 G18

PEX_PETp8 B11

PEX_PETp9 B10

PEX_PETp10 B8

PEX_PETp11 B7

PEX_PETp12 H1

PEX_PETp13 J1

PEX_PETp14 L1

PEX_PETp15 M1

PEX_PETn0 V8

PEX_PETn1 V9

PEX_PETn2 V11

PEX_PETn3 V12

PEX_PETn4 L17

PEX_PETn5 K17

PEX_PETn6 H17

PEX_PETn7 G17

PEX_PETn8 A11

PEX_PETn9 A10

PEX_PETn10 A8

PEX_PETn11 A7

PEX_PETn12 H2

PEX_PETn13 J2

PEX_PETn14 L2

PEX_PETn15 M2

PEX_PERp0 P8

PEX_PERp1 P9

PEX_PERp2 P11

PEX_PERp3 P12

PEX_PERp4 L15

PEX_PERp5 K15

PEX_PERp6 H15

PEX_PERp7 G15

PEX_PERp8 E11

PEX_PERp9 E10

PEX_PERp10 E8

PEX_PERp11 E7

PEX_PERp12 H4

PEX_PERp13 J4

PEX_PERp14 L4

PEX_PERp15 M4

PEX_PERn0 R8

PEX_PERn1 R9

PEX_PERn2 R11

PEX_PERn3 R12

PEX_PERn4 L14

PEX_PERn5 K14

PEX_PERn6 H14

PEX_PERn7 G14

PEX_PERn8 D11

PEX_PERn9 D10

PEX_PERn10 D8

PEX_PERn11 D7

PEX_PERn12 H5

PEX_PERn13 J5

PEX_PERn14 L5

PEX_PERn15 M5

PEX_REFCLKpU10PEX_REFCLKnV10

REXT_A0R10

REXT_B0N11

REXT_A1J15

REXT_B1H13

N/CJ17N/CJ18

PEX_REFCLK_CFCnA9PEX_REFCLK_CFCpB9

REXT_A2D9

REXT_B2F8

N/CK1N/CK2

REXT_A3K4

REXT_B3L6

N/CP10

N/CJ14

N/CE9

N/CK5

J6B84517-101J6B84517-101

GN

D0

A20

GN

D1

A9

GN

D2

A8

GN

D3

A5

GN

D4

A4

GN

D5

A1

GN

D6

A17

GN

D7

A16

GN

D8

A13

GN

D9

A12

GN

D10

B20

GN

D11

B9

GN

D12

B8

GN

D13

B5

GN

D14

B4

GN

D15

B1

GN

D16

B17

GN

D17

B16

GN

D18

B13

GN

D19

B12

GN

D20

C20

GN

D21

C9

GN

D22

C8

GN

D23

C5

GN

D24

C4

GN

D25

C1

GN

D26

C17

GN

D27

C16

GN

D28

C13

GN

D29

C12

GN

D30

D20

GN

D31

D9

GN

D32

D8

GN

D33

D5

GN

D34

D4

GN

D35

D1

GN

D36

D17

GN

D37

D16

GN

D38

D13

GN

D39

D12

GN

D40

G20

GN

D41

G9

GN

D42

G8

GN

D43

G5

GN

D44

G4

GN

D45

G1

GN

D46

G17

GN

D47

G16

GN

D48

G13

GN

D49

G12

GN

D50

H20

GN

D51

H9

GN

D52

H8

GN

D53

H5

GN

D54

H4

GN

D55

H1

GN

D56

H17

GN

D57

H16

GN

D58

H13

GN

D59

H12

GN

D60

I20

GN

D61

I9G

ND

62I8

GN

D63

I5G

ND

64I4

GN

D65

I1G

ND

66I1

7G

ND

67I1

6G

ND

68I1

3G

ND

69I1

2G

ND

70J2

0G

ND

71J9

GN

D72

J8G

ND

73J5

GN

D74

J4G

ND

75J1

GN

D76

J17

GN

D77

J16

GN

D78

J13

GN

D79

J12

NC

0E

3N

C1

E4

NC

2E

5N

C3

E6

NC

4E

7N

C5

E8

NC

6E

9N

C7

E10

NC

8E

11N

C9

E12

NC

10E

13N

C11

E14

NC

12E

15N

C13

E16

NC

14E

17N

C15

E18

NC

16E

19N

C17

E20

NC

18F2

NC

19F3

NC

20F4

NC

21F5

NC

22F6

NC

23F7

NC

24F8

NC

25F9

NC

26F1

0N

C27

F11

NC

28F1

2N

C29

F13

NC

30F1

4N

C31

F15

NC

32F1

6N

C33

F17

NC

34F1

8N

C35

F19

NC

36F2

0

C180.1uF C180.1uF

TXRX

J6A

84517-101

TXRX

J6A

84517-101

TX0_S_pA19 TX0_D0_p B19TX0_D1_p A18TX0_D2_p B18

TX0_D0_n D19TX0_D1_n C18TX0_D2_n D18

TX0_S_nC19

TX1_S_pA15

TX1_S_nC15

TX1_D0_p B15TX1_D1_p A14TX1_D2_p B14








RX4_S2_nJ2RX4_S1_nI2RX4_S0_nJ3

RX4_S2_pH2RX4_S1_pG2RX4_S0_pH3

TX2_S_pA11

TX2_S_nC11

TX3_S_pA7

TX3_S_nC7

TX4_S_pA3

TX4_S_nC3









PRESENT#F1CFGID0E1CFGID1E2

RX0_D_p G19

RX0_D_n I19

RX1_D_p G15

RX1_D_n I15

RX2_D_p G11

RX2_D_n I11

RX3_D_p G7

RX3_D_n I7

RX4_D_p G3

RX4_D_n I3

J5B84517-101J5B84517-101

GN

D0

A20

GN

D1

A9

GN

D2

A8

GN

D3

A5

GN

D4

A4

GN

D5

A1

GN

D6

A17

GN

D7

A16

GN

D8

A13

GN

D9

A12

GN

D10

B20

GN

D11

B9

GN

D12

B8

GN

D13

B5

GN

D14

B4

GN

D15

B1

GN

D16

B17

GN

D17

B16

GN

D18

B13

GN

D19

B12

GN

D20

C20

GN

D21

C9

GN

D22

C8

GN

D23

C5

GN

D24

C4

GN

D25

C1

GN

D26

C17

GN

D27

C16

GN

D28

C13

GN

D29

C12

GN

D30

D20

GN

D31

D9

GN

D32

D8

GN

D33

D5

GN

D34

D4

GN

D35

D1

GN

D36

D17

GN

D37

D16

GN

D38

D13

GN

D39

D12

GN

D40

G20

GN

D41

G9

GN

D42

G8

GN

D43

G5

GN

D44

G4

GN

D45

G1

GN

D46

G17

GN

D47

G16

GN

D48

G13

GN

D49

G12

GN

D50

H20

GN

D51

H9

GN

D52

H8

GN

D53

H5

GN

D54

H4

GN

D55

H1

GN

D56

H17

GN

D57

H16

GN

D58

H13

GN

D59

H12

GN

D60

I20

GN

D61

I9G

ND

62I8

GN

D63

I5G

ND

64I4

GN

D65

I1G

ND

66I1

7G

ND

67I1

6G

ND

68I1

3G

ND

69I1

2G

ND

70J2

0G

ND

71J9

GN

D72

J8G

ND

73J5

GN

D74

J4G

ND

75J1

GN

D76

J17

GN

D77

J16

GN

D78

J13

GN

D79

J12

NC

0E

3N

C1

E4

NC

2E

5N

C3

E6

NC

4E

7N

C5

E8

NC

6E

9N

C7

E10

NC

8E

11N

C9

E12

NC

10E

13N

C11

E14

NC

12E

15N

C13

E16

NC

14E

17N

C15

E18

NC

16E

19N

C17

E20

NC

18F2

NC

19F3

NC

20F4

NC

21F5

NC

22F6

NC

23F7

NC

24F8

NC

25F9

NC

26F1

0N

C27

F11

NC

28F1

2N

C29

F13

NC

30F1

4N

C31

F15

NC

32F1

6N

C33

F17

NC

34F1

8N

C35

F19

NC

36F2

0

C250.1uF C250.1uF

TPV6TPV6

C240.1uF C240.1uFTPV7TPV7

C300.1uF C300.1uF

C310.1uF C310.1uF

TXRX

J5A

84517-101

TXRX

J5A

84517-101

TX0_S_pA19 TX0_D0_p B19TX0_D1_p A18TX0_D2_p B18


TX0_S_nC19

TX1_S_pA15

TX1_S_nC15











TX2_S_pA11

TX2_S_nC11

TX3_S_pA7

TX3_S_nC7

TX4_S_pA3

TX4_S_nC3









PRESENT#F1CFGID0E1CFGID1E2

RX0_D_p G19

RX0_D_n I19

RX1_D_p G15

RX1_D_n I15

RX2_D_p G11

RX2_D_n I11

RX3_D_p G7

RX3_D_n I7

RX4_D_p G3

RX4_D_n I3

C30.1uF C30.1uF

TPV8TPV8

C20.1uF C20.1uF

C80.1uF C80.1uF

R41.43K1%

R41.43K1%

C90.1uF C90.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CPRSNT#

WAKE#

3.3Vaux

3.3V_SERIAL_HOT_PLUG 12V_SERIAL_HOT_PLUG

3.3V_BOARD

3.3V_DWNSTREAM

3.3V_BOARD

12V_DWNSTREAM

3.3V_BOARD 12V_BOARD

3.3V_DWNSTREAM

3.3V_BOARD

12V_DWNSTREAM

3.3V_BOARD

3.3V_BOARD

J4_PEX_TX11_n{3}

J2_PEX_TX8_p{3}

PEX_TX0_p {3}

J4_PEX_TX10_p{3}

J2_PEX_TX8_n{3}

J4_PEX_TX10_n{3}

PEX_TX0_n {3}

J2_PEX_RX11_p {3}

PEX_RX0_p{3}

J4_PEX_TX9_p{3}

PEX_TX1_p {3}

J4_PEX_TX9_n{3}

PEX_RX0_n{3}

J2_PEX_RX11_n {3}

PEX_TX1_n {3}

J2_REFCLKp {10}J2_REFCLKn {10}

J4_PEX_TX8_p{3}

PEX_TX15_p{3}PEX_TX15_n{3}



J2_PEX_RX10_p {3}

PEX_RX1_p{3}

J4_PEX_RX8_n {3}

PEX_TX2_p {3}

J4_PEX_TX8_n{3}

J2_PEX_RX10_n {3}

PEX_RX1_n{3}

PEX_TX2_n {3}

J4_PEX_RX8_p {3}

J2_PEX_RX9_p {3}



PEX_RX14_p {3}

PEX_RX2_p{3}

PEX_RX14_n {3}


J4_PEX_RX9_n {3}

PEX_TX3_p {3}

J2_PEX_RX9_n {3}

PEX_RX2_n{3}

J4_PEX_RX9_p {3}

J2_PEX_RX8_p {3}

PEX_TX3_n {3}

J4_PEX_RX10_n {3}

PEX_RX3_p{3}

J2_PEX_TX11_p{3}

J2_PEX_RX8_n {3}

P1_PERST# {7}

J4_PEX_RX10_p {3}

PEX_RX3_n{3}

J2_PEX_TX11_n{3}

J4_PEX_RX11_n {3}

P1_REFCLK_n {10}

J2_PEX_TX10_p{3}

J4_PEX_RX11_p {3}

J2_PEX_TX10_n{3}

P1_REFCLK_p {10}

J4_PEX_TX11_p{3}

J2_PEX_TX9_p{3}J2_PEX_TX9_n{3}

P1_PEX_TX5_p {3}P1_PEX_TX5_n {3}




P1_PEX_RX4_p{3}P1_PEX_RX4_n{3}




J3_PEX_RX6_n {3}

J3_PEX_RX5_p {3}J3_PEX_RX5_n {3}

J3_PEX_RX4_p {3}

J3_PEX_TX7_p{3}

J3_PEX_RX4_n {3}

J3_PEX_TX7_n{3}






J3_PEX_RX6_p {3}











SHP_PRSNT#{8}

SHP_PERST# {6}

PERST#_PCIe_SWITCH{5,6,7}

CPRSNT{6}

Title


Date: Sheet of

91-0126-000-A 000

PEX8619 RDK - PCIe Connectors


C


Title


Date: Sheet of

91-0126-000-A 000



C


Title


Date: Sheet of

91-0126-000-A 000



C


IF 3.3VAUX IS NOT AVAILABLE FROM EDGECONNECTOR P1, BUT CARDS PLUGGED INTOTHE DOWNSTREAM SLOTS REQUIRE IT, THENINSTALL JUMPER JP11.

R9 0R9 0

Q3MMBT3904LT1Q3MMBT3904LT1

1

32

R6 0R6 0

TPV9TPV9

TPV11TPV11

+ C33

22uF

+ C33

22uF

R5 0R5 0

R125.1KR125.1K

R135.1KR135.1K

R10 0R10 0

TPV10TPV10

P1

PCI Express x8 edge connector

P1

PCI Express x8 edge connector

+12VB1+12VB2+12VB3GNDB4SMCLKB5SMDATB6GNDB7+3.3VB8TRST#B93.3VauxB10WAKE#B11

RSVDB12GNDB13PETp0B14PETn0B15GNDB16PRSNT2#B17GNDB18PETp1B19PETn1B20GNDB21GNDB22PETp2B23PETn2B24GNDB25GNDB26PETp3B27PETn3B28GNDB29RSVDB30PRSNT2#B31GNDB32

PRSNT1# A1+12V A2+12V A3GND A4TCK A5TDI A6

TDO A7TMS A8

+3.3V A9+3.3V A10

PERST# A11

GND A12REFCLK+ A13REFCLK- A14

GND A15PERp0 A16PERn0 A17

GND A18RSVD A19GND A20

PERp1 A21PERn1 A22

GND A23GND A24

PERp2 A25PERn2 A26

GND A27GND A28

PERp3 A29PERn3 A30

GND A31RSVD A32RSVD A33GND A34

PERp4 A35PERn4 A36

GND A37GND A38

PERp5 A39PERn5 A40

GND A41GND A42

PERp6 A43PERn6 A44

GND A45GND A46

PERp7 A47PERn7 A48

GND A49

PETp4B33PETn4B34GNDB35GNDB36PETp5B37PETn5B38GNDB39GNDB40PETp6B41PETn6B42GNDB43GNDB44PETp7B45PETn7B46GNDB47

GNDB49PRSNT2#B48

J4

PCIe x4 Cable

J4

PCIe x4 Cable

GND B1GNDA1PERp0 B2PERn0 B3

GND B4PERp1 B5PERn1 B6



GND B13PWR B14PWR B15

PWR_RTN B16PWR_RTN B17

CWAKE# B18CPERST# B19

PETp0A2PETn0A3GNDA4PETp1A5PETn1A6GNDA7PETp2A8PETn2A9GNDA10PETp3A11PETn3A12GNDA13CREFCLKpA14CREFCLKnA15GNDA16SB_RTNA17CPRSNT#A18CPWRONA19

R115.1KR115.1K

J3

PCI_EXP_X16_FEMALE_CONN

J3


PRSNT1# A1+12V A2+12V A3GND A4

TCLK A5TDI A6

TDO A7TMS A8

+3.3V A9+3.3V A10

PERST# A11

+12VB1+12VB2+12VB3GNDB4SMCLKB5SMDATB6GNDB7+3.3VB8TRST#B93.3VAUXB10WAKE#B11

RSVDB12

PETp0B14PETn0B15GNDB16PRSNT2#B17GNDB18PETp1B19PETn1B20GNDB21GNDB22PETp2B23PETn2B24GNDB25GNDB26PETp3B27PETn3B28GNDB29RSVDB30




PERp1 A21PERn1 A22

GND A23GND A24

PERp2 A25PERn2 A26

GND A27GND A28

PERp3 A29PERn3 A30

GNDB13


PERp4 A35PERn4 A36

GND A37GND A38

PERp5 A39PERn5 A40

GND A41GND A42

PERp6 A43PERn6 A44

GND A45GND A46

PERp7 A47PERn7 A48


PERp8 A52PERn8 A53

GND A54GND A55

PERp9 A56PERn9 A57

GND A58GND A59

PERp10 A60

PRSNT2#B31GNDB32PETp4B33PETn4B34GNDB35GNDB36PETp5B37PETn5B38GNDB39GNDB40PETp6B41PETn6B42GNDB43GNDB44PETp7B45PETn7B46GNDB47PRSNT2#B48GNDB49PETp8B50PETn8B51GNDB52GNDB53PETp9B54PETn9B55GNDB56GNDB57PETp10B58PETn10B59GNDB60

PERn10 A61GND A62GND A63

PERp11 A64PERn11 A65

GND A66GND A67


GND A70GND A71


GND A74GND A75


GND A78GND A79


GND A82

GNDB61PETp11B62PETn11B63GNDB64GNDB65PETp12B66PETn12B67GNDB68GNDB69PETp13B70PETn13B71GNDB72GNDB73PETp14B74PETn14B75GNDB76GNDB77PETp15B78PETn15B79GNDB80PRSNT2#B81RSVDB82

JP11JUMPERJP11

JUMPER

12

R14 0R14 0

R71KR71K

R117 2.7KR117 2.7K

+

C39

22uF

+

C39

22uF

+C37

22uF

+C37

22uF

+ C40

22uF

+ C40

22uF

R8 0R8 0

R77 0R77 0

+ C34

22uF

+ C34

22uF

+ C35

22uF

+ C35

22uFJ1

PCI_EXP_X16_STRADDLE_MNT_CONN

J1

PCI_EXP_X16_STRADDLE_MNT_CONN


TCLK A5TDI A6

TDO A7TMS A8

+3.3V A9+3.3V A10

PERST# A11


RSVDB12





PERp1 A21PERn1 A22

GND A23GND A24

PERp2 A25PERn2 A26

GND A27GND A28

PERp3 A29PERn3 A30

GNDB13


PERp4 A35PERn4 A36

GND A37GND A38

PERp5 A39PERn5 A40

GND A41GND A42

PERp6 A43PERn6 A44

GND A45GND A46

PERp7 A47PERn7 A48


PERp8 A52PERn8 A53

GND A54GND A55

PERp9 A56PERn9 A57

GND A58GND A59

PERp10 A60




GND A66GND A67


GND A70GND A71


GND A74GND A75


GND A78GND A79


GND A82


+C36

22uF

+C36

22uF

J2


J2



TCLK A5TDI A6

TDO A7TMS A8

+3.3V A9+3.3V A10

PERST# A11


RSVDB12





PERp1 A21PERn1 A22

GND A23GND A24

PERp2 A25PERn2 A26

GND A27GND A28

PERp3 A29PERn3 A30

GNDB13


PERp4 A35PERn4 A36

GND A37GND A38

PERp5 A39PERn5 A40

GND A41GND A42

PERp6 A43PERn6 A44

GND A45GND A46

PERp7 A47PERn7 A48


PERp8 A52PERn8 A53

GND A54GND A55

PERp9 A56PERn9 A57

GND A58GND A59

PERp10 A60




GND A66GND A67


GND A70GND A71


GND A74GND A75


GND A78GND A79


GND A82


R15 0R15 0

R1185.1KR1185.1K

+C38

22uF

+C38

22uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

I2C_SCL0I2C_SDA0

3.3V_BOARD 3.3V_BOARD

3.3V_BOARD

1.0V_PCIe_SWITCH

3.3V_BOARD

3.3V_BOARD

3.3V_BOARD

2.5V_PCIe_SWITCH

3.3V_BOARD

3.3V_BOARD

3.3V_BOARD

PERST#_PCIe_SWITCH{4,6,7}

STRAP_PORTCFG0{6}STRAP_PORTCFG1{6}STRAP_PORTCFG2{6}STRAP_PORTCFG3{6}

STRAP_UPSTRM_PORTSEL0{6}STRAP_UPSTRM_PORTSEL1{6}STRAP_UPSTRM_PORTSEL2{6}STRAP_UPSTRM_PORTSEL3{6}

STRAP_NT_ENABLE#{6}

STRAP_NT_UPSTRM_PORTSEL3{6,9}

STRAP_NT_UPSTRM_PORTSEL0{6}STRAP_NT_UPSTRM_PORTSEL1{6}STRAP_NT_UPSTRM_PORTSEL2{6}

I2C_SCL1{8}I2C_SDA1{8}

PEX_LANE_GOOD0# {6,9}PEX_LANE_GOOD1# {6,9}PEX_LANE_GOOD2# {6,9}PEX_LANE_GOOD3# {6,9}PEX_LANE_GOOD4# {6,9}PEX_LANE_GOOD5# {6,9}PEX_LANE_GOOD6# {6,9}PEX_LANE_GOOD7# {6,9}PEX_LANE_GOOD8# {6,9}PEX_LANE_GOOD9# {6,9}PEX_LANE_GOOD10# {6,9}PEX_LANE_GOOD11# {6,9}PEX_LANE_GOOD12# {6,9}PEX_LANE_GOOD13# {6,9}PEX_LANE_GOOD14# {6,9}PEX_LANE_GOOD15# {6,9}

PEX 8619BA-AIC4U4D RDKPEX 8619BA-AIC4U4D RDK Hardware Reference Manual Version 1.1 November 2009...

Documents

Transcript of PEX 8619BA-AIC4U4D RDKPEX 8619BA-AIC4U4D RDK Hardware Reference Manual Version 1.1 November 2009...