CHAPTER 3

PERFORMANCE OF A TWO INPUT

NAND GATE USING SUBTHRESHOLD

LEAKAGE CONTROL TECHNIQUES

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In this chapter, performance characteristics of a two input NAND gate using

existing subthreshold leakage control techniques such as stack technique, MTCMOS

technique, sleepy keeper technique, and SCCMOS technique are compared with the

conventional CMOS logic technique in 45nm CMOS technology. Performance

characteristics such as static power dissipation, dynamic power dissipation, and

propagation delay of a two input NAND gate are analyzed. Reduction in static power

dissipation by reduction factors of 1.13x, 1.27x, 1.40x, and 1.44x are observed by using

stack technique, MTCMOS technique, sleepy keeper technique, and SCCMOS

technique respectively in comparison with conventional CMOS logic technique for a

two input NAND gate. SCCMOS technique lowers the subthreshold leakage power

dissipation most effectively. Hence, this technique effectively reduces the overall static

power dissipation in digital logic circuits in deep submicron CMOS technologies. All

simulations are performed at a temperature of 270C, and a supply voltage of 0.40V in

45nm CMOS technology. Microwind ver. 3.1 EDA tool is used in designing and

simulating the layout of a two input NAND gate in various technologies using BSIM4

MOS parameter model. Finally conclusion is provided in the end of this chapter.

3.1 INTRODUCTION

Power dissipation in digital logic circuits can be broadly divided into two

categories: dynamic power dissipation and static or leakage power dissipation. Dynamic

power dissipation is mainly caused by the current flow due to charging and discharging

of parasitic capacitances in the logic circuit. Static power dissipation occurs during the

static input states of the device. With the down scaling in technology, contribution by

static power dissipation increases in the overall power dissipation (Elgharbawy et al.

2005). In deep submicron CMOS technologies, the role of subthreshold leakage power

dissipation becomes dominant among other leakage power components

(Deepaksubramanyan et al. 2007) because of down scaling in technology. Under such

condition, the static power dissipation is approximately equal to the subthreshold

leakage power dissipation and is expressed as

(3.1)

A general formula for the total power dissipation in a digital logic circuit in deep

submicron CMOS technologies can be expressed as

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(3.2)

(3.3)

3.2 CIRCUIT DESIGN USING VARIOUS TECHNIQUES

In this section, circuit diagrams of a two input NAND gate are designed using

conventional CMOS technique and existing subthreshold leakage control techniques

such as stack technique, MTCMOS technique, and SCCMOS technique.

3.2.1 CONVENTIONAL CMOS TECHNIQUE

A conventional CMOS circuit (Kang et al. 2003) consists of a pull up network

and a pull down network. A pull up network consists of pMOS transistors while a pull

down network consists of nMOS transistors. In this technique, all pMOS transistors

must have either an input from the power supply voltage (VDD) or from another pMOS

transistor. Similarly, all nMOS transistors must have either an input from ground or

from another nMOS transistor. Fig. 3.1 shows the circuit diagram of a two input NAND

gate using this technique.

Fig. 3.1 Circuit diagram of a two input NAND gate using conventional CMOS

technique

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3.2.2 STACK TECHNIQUE

In stack technique (Johnson et al. 2002), a MOS transistor of width W is

replaced with two series connected MOS transistors, each of width W/2. Fig. 3.2 shows

the circuit diagram of a two input NAND gate using this technique. In this figure, each

MOS transistor (width W) of a CMOS two input NAND gate is replaced with two series

connected MOS transistors (each of width W/2). When two half size stacked MOS

transistors are turned off together, induce reverse bias between them results in the

reduction of the subthreshold leakage power (Chen et al. 1988). However, increase in

the number of transistors increases the overall propagation delay of the circuit.

Fig. 3.2 Circuit diagram of a two input NAND gate using stack technique

3.2.3 MTCMOS TECHNIQUE

In MTCMOS technique (Mutoh et al. 1995), a high-threshold voltage pMOS

transistor (sleep pMOS transistor) is inserted between the power supply voltage (VDD)

and the logic circuit; and a high-threshold voltage nMOS transistor (sleep nMOS

transistor) is placed between the logic circuit and ground. Fig. 3.3 shows the circuit

diagram of a two input NAND gate using this technique. During active mode of

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operation, the high threshold voltage MOS transistors (sleep transistors) are turned on;

while during sleep mode, these high VTH transistors are turned off.

Fig. 3.3 Circuit diagram of a two input NAND gate using MTCMOS technique

3.2.4 SLEEPY KEEPER TECHNIQUE

In sleepy keeper technique (Kim et al. 2006), an additional high threshold

voltage nMOS transistor is connected in parallel with the sleep pMOS transistor (high

VTH sleep pMOS transistor) and an additional high threshold voltage pMOS transistor is

connected in parallel with the sleep nMOS transistor (high VTH sleep nMOS transistor).

Fig. 3.4 shows the circuit diagram of a two input NAND gate using this technique. In

sleep mode, the sleep transistors are in cutoff state. So, when sleep signal is activated,

then the high threshold voltage nMOS transistor connected in parallel with the sleep

pMOS transistor is the only source of power supply to the pullup network and the high

threshold voltage pMOS transistor connected in parallel with the sleep nMOS transistor

provides the path to connect the pulldown network with ground.

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Fig. 3.4 Circuit diagram of a two input NAND gate using sleepy keeper technique

3.2.5 SCCMOS TECHNIQUE

In SCCMOS technique (Kawaguchi et al. 2000), a pMOS transistor (sleep

pMOS transistor) having the same threshold voltage as that of pMOS transistors of the

logic circuit is inserted between the logic circuit and the power supply voltage (VDD);

and an nMOS transistor (sleep nMOS transistor) having the same threshold voltage as

that of nMOS transistors of the logic circuit is inserted between the logic circuit and

ground. Fig. 3.5 shows the circuit diagram of a two input NAND gate using this

technique. During active mode of operation, sleep transistors are turned on by

connecting GND at VGS1 and VDD at VGS2; while during sleep mode, these sleep

transistors are turned off by providing positive and negative gate voltages at VGS1 and

VGS2 respectively.

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Fig. 3.5 Circuit diagram of a two input NAND gate using SCCMOS technique

3.3 SIMULATION RESULTS AND OBSERVATIONS

Performance characteristics such as static power dissipation, dynamic power

dissipation, and propagation delay for a two input NAND gate using subthreshold

leakage control techniques such as stack technique, MTCMOS technique, sleepy keeper

technique, and SCCMOS technique are compared with the conventional CMOS

technique. All simulations are performed at a temperature of 270C and a supply voltage

of 0.40V in 45nm CMOS technology. Microwind ver 3.1 EDA tool is used for the

layout design and simulation of a two input NAND gate using advanced BSIM4 MOS

parameter model.

Figs. 3.6 – 3.10 show the layout of a two input NAND gate using conventional

CMOS technique, stack technique, MTCMOS technique, sleepy keeper technique, and

SCCMOS technique respectively. MOS transistor parameters such as channel length,

channel width, and aspect ratio used to design a two input NAND gate using various

techniques are mentioned in Tables 3.1 – 3.5. Aspect ratio of a MOS transistor is the

ratio of its channel width and its channel length. The threshold voltage of a MOS

transistor increases with the increase in its channel length. So, the channel lengths of

high threshold voltage transistors and sleep transistors are chosen greater than the

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normal threshold voltage transistors (low VTH transistors) in MTCMOS and sleepy

keeper techniques. Table 3.6 shows all possible static input combinations for measuring

static power dissipation in a two input NAND gate. Fig. 3.11 shows the waveform to

measure the dynamic power dissipation of the logic gate using conventional CMOS and

stack techniques. Similarly, Fig. 3.12 shows the waveform to measure the dynamic

power dissipation of a two input NAND gate using MTCMOS and sleepy keeper

techniques and Fig.3.13 shows the waveform to measure the dynamic power dissipation

using SCCMOS technique.

Fig. 3.6 Layout of a two input NAND gate using conventional CMOS technique

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Fig. 3.7 Layout of a two input NAND gate using stack technique

Fig. 3.8 Layout of a two input NAND gate using MTCMOS technique

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Fig. 3.9 Layout of a two input NAND gate using sleepy keeper technique

Fig. 3.10 Layout of a two input NAND gate using SCCMOS technique

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Table 3.1: Physical aspects of MOS transistors using conventional CMOS technique

Parameters nMOS transistor pMOS transistor

Channel width (μm) 0.15 0.30

Channel length (μm) 0.05 0.05

Aspect ratio 3.00 6.00

Table 3.2: Physical aspects of MOS transistors using stack technique

Parameters nMOS transistor pMOS transistor

Channel width (μm) 0.08 0.15

Channel length (μm) 0.05 0.05

Aspect ratio 1.50 3.00

Table 3.3: Physical aspects of MOS transistors using MTCMOS technique

Table 3.4: Physical aspects of MOS transistors using sleepy keeper technique

Parameters nMOS

transistor

(low VTH)

pMOS

transistor

(low VTH)

Sleep nMOS

transistor

(high VTH)

Sleep pMOS

transistor

(high VTH)

Channel width (μm) 0.15 0.30 0.21 0.42

Channel length (μm) 0.05 0.05 0.07 0.07

Aspect ratio 3.00 6.00 3.00 6.00

Parameters nMOS

transistor

(low VTH)

pMOS

transistor

(low VTH)

Sleep nMOS

transistor

(high VTH)

Sleep pMOS

transistor

(high VTH)

Channel width (μm) 0.15 0.30 0.21 0.42

Channel length (μm) 0.05 0.05 0.07 0.07

Aspect ratio 3.00 6.00 3.00 6.00

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Table 3.5: Physical aspects of MOS transistors using SCCMOS technique

Table 3.6: Static input combinations for measuring static power dissipation

Fig. 3.11 Waveform to measure the dynamic power dissipation using conventional

CMOS and stack techniques

Fig. 3.12 Waveform to measure the dynamic power dissipation using MTCMOS and

sleepy keeper techniques

Parameters nMOS

transistor

(low VTH)

pMOS

transistor

(low VTH)

Sleep nMOS

transistor

(low VTH)

Sleep pMOS

transistor

(low VTH)

Channel width (μm) 0.15 0.30 0.15 0.30

Channel length (μm) 0.05 0.05 0.05 0.05

Aspect ratio 3.00 6.00 3.00 6.00

Static input A Static input B Output Y

0 0 1

0 1 1

1 0 1

1 1 0

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Fig.3.13 Waveform to measure the dynamic power dissipation using SCCMOS

technique

Static power dissipation is obtained by combining all possible static input

combinations. The overall static power dissipation is calculated as the average of power

dissipation in all possible static input combinations. This power dissipation for a two

input NAND gate using various techniques is measured for 50ns time interval.

Dynamic power dissipation in a logic circuit is mainly due to the switching

power dissipation. From Figs. 3.11-3.13, it is observed that the input signal frequency

(A and B) is equal to the switching frequency of the output waveform. So, the output

switching frequency is equal to the input signal frequency. The supply voltage, VDD is

equal to 0.40V. Dynamic power dissipation is obtained by applying two clock signals,

A and B, of same frequency of 200MHz. The amplitude of each clock signal is fixed at

0.40V. This power dissipation for a two input NAND gate using various techniques is

obtained for 50 ns time interval. In SCCMOS technique, dynamic power is obtained by

connecting VGS1 to GND and VGS2 to VDD. Similarly, in MTCMOS and sleepy keeper

techniques, sleep signal and sleep signal are connected to GND and VDD, for obtaining

the dynamic power dissipation. In this way, dynamic power dissipation can be obtained

with the simulated waveforms for a logic circuit by using various conventional and

reported techniques.

Propagation delay of the logic gate by using various techniques is measured

from the trigger input edge reaching 50 % of VDD to the circuit output edge reaching

50 % of VDD.

Table 3.7 shows the performance characteristics of a two input NAND gate

using conventional CMOS, stack, MTCMOS, sleepy keeper, and SCCMOS techniques

in 45nm CMOS technology. Table 3.8 shows the static power dissipation reduction

factors for a two input NAND gate using stack, MTCMOS, sleepy keeper, and

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SCCMOS techniques in comparison with the conventional CMOS technique. Fig. 3.14

shows the static power dissipation comparison of a two input NAND gate by using

various techniques. Fig. 3.15 shows the static power dissipation reduction factors for a

two input NAND gate using existing subthreshold leakage reduction techniques, such as

stack, MTCMOS, sleepy keeper, and SCCMOS techniques in comparison with the

conventional CMOS logic technique.

Reduction in static power dissipation by reduction factors of 1.13x, 1.27x,

1.40x, and 1.44x are observed by using stack technique, MTCMOS technique, sleepy

keeper technique, and SCCMOS technique respectively in comparison with

conventional CMOS logic technique for a two input NAND gate. It is found that

SCCMOS is the most effective technique to reduce the static power dissipation in

comparison with other existing subthreshold leakage control techniques. It is also

important to note that in this technique the dynamic power and delay remains almost

same as that of conventional CMOS logic technique.

Table 3.7: Performance characteristics of a two input NAND gate using various circuit

techniques

Techniques Static power

(in μW)

Dynamic power

(in μW)

Delay

(in sec.)

CMOS 0.052 0.102 12.8 x 10-12

Stack 0.046 0.098 19.6 x 10-12

MTCMOS 0.041 0.109 14.8 x 10-12

Sleepy keeper 0.037 0.114 16.0 x 10-12

SCCMOS 0.036 0.104 13.0 x 10-12

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Table 3.8: Static power dissipation reduction factors for a two input NAND gate using

stack, MTCMOS, sleepy keeper, and SCCMOS techniques in comparison with the

conventional CMOS logic technique

Techniques Static power dissipation reduction factors in

comparison with conventional CMOS technique

Stack 1.13x

MTCMOS 1.27x

Sleepy keeper 1.40x

SCCMOS 1.44x

Fig. 3.14 Static power dissipation comparison of a two input NAND gate using various

techniques

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Fig. 3.15 Static power dissipation reduction factors for a two input NAND gate using

subthreshold leakage reduction techniques in comparison with CMOS technique

3.4 CONCLUSION

In this chapter, performance characteristics such as static power dissipation,

dynamic power dissipation, and propagation delay of a two input NAND gate are

analyzed using various techniques. Performance characteristics of a two input NAND

gate using subthreshold leakage control techniques such as stack technique, MTCMOS

technique, sleepy keeper technique, and SCCMOS technique are compared with the

conventional CMOS logic technique in 45nm CMOS technology. Among these existing

techniques, SCCMOS technique effectively reduces the subthreshold leakage power

dissipation while the dynamic power and delay remain low. So, in deep submicron and

nanoscale technologies, this technique can be utilized for designing digital circuits with

effective reduction in the static power dissipation, which is mainly due to the

subthreshold leakage power dissipation.