International Journal on Electrical Engineering and Informatics - Volume 1, �umber 1, 2009

Performance Evaluation and Control Technique of Large Ratio DC-DC Converter

Agus Purwadi, Kus Adi Nugroho, Firman Sasongko, Kadek Fendy Sutrisna and Pekik Argo Dahono

School of Electrical Engineering and Informatics, Institut Teknologi Bandung

Jl. Ganesha 10, Bandung. 40132. INDONESIA agusp@konversi.ee.itb.ac.id

Abstract: The performance of large ratio dc-dc converter will be discussed in this paper.

The performance will be observed by its ripple and losses. The performance will be compared with multiphase and multilevel dc-dc converter. The specific control technique for large ratio dc-dc converter also will be discussed in this paper. Experiment results are included to verify the analysis method. Keywords: Ripple, losses, control. 1. Introduction

RENEWABLE energy power generations such as photovoltaic, fuel cell, and others dc output voltage power generation, are very promising due to the environmental consideration and limited fossil fuel. This renewable energy, especially solar energy is very potential in Indonesia. This is very useful to electrify remote area in Indonesia.

However, the output voltage of the photovoltaic cell is very low, around 6V-24V. Therefore, the output voltage cannot be directly to be used. The output voltage must be stepped up and inverted to produce appropriate ac voltage.

In case of step down, there are some applications that need a very low dc voltage from grid, such as microprocessor, electroplating, etc. To gather the very low voltage, grid line must be rectified and stepped down. Of course, the other option is to utilize transformer. But the physical size and cost is considerations to avoid transformer. Because of that, step down and step up processes are expected in dc voltage.

There are problems to step up and step down dc voltage to very high and very low dc voltage. In non-isolated dc-dc converter type, high ratio between input and output converter will create problem due to limitation of the switching device. High ratio between input and output will make the switching device operate in very small or very high duty ratio while as we know there are some limitations in the non-ideal switching device. To solve this problem, a new topology of dc-dc converter is proposed[2]. This topology let us obtain the high ratio of the input and output from the potential difference of the each converter. Thus we will not face the extreme duty cycle problem in the switching device anymore since we can operate each converter in the moderate duty cycle.

In this paper, performance of large ratio dc-dc converter will be observed from the ripple and losses aspects. Control technique of large ratio dc-dc converter also will be discussed. The control technique is utilizing double loop control.

2. Large Ratio Dc-Dc Converter Suppose that we want to obtain large ratio buck dc-dc converter as mentioned before, then we

consider the parallel-input, series output configuration (Fig. 1) of buck converter. Fig. 2(a) shows the two buck converters which will be connected in the configuration as shown in Fig. 3.

The load side is represented by a current source, while input side is represented by voltage source. Since input side of buck converter is connected in parallel, then

1 2d d dE E E= = (1) Where Ed1, Ed2, and Ed are input voltage of first buck converter, second buck converter, and the new topology converter, respectively.

Connecting the input side of the two buck converters in parallel manner will result a circuit as

shown in Fig. 2(b). Now the two converters have been connected into single converter with two outputs. Then we had to connect the two outputs in serial manner, since the both output currents are flow in the opposite direction, then we have to reverse one of the output current so it can be connected in serial manner. The reversal of the one of the output current can be done in the control domain of the buck converter. Fig. 2(c) shows the resulted topology after the reversal of another output

oi

1ov

2ov

ov

1oi

2oi

1iv

2iv

ivii 1ii

2ii

Fig. 1. Parallel – Input, Series – Output configuration.

current. Since two current sources which are connected in series are degenerated into a single current source, then Fig. 2(d) shows the resulted topology. The complete new topology large ratio dc-dc converter is shown in Fig. 2(e) where the transistors and diodes used as switching device. With this topology we can obtain large ratio between output and input side, without need to operate each switching device in the extreme duty cycle, as in the conventional buck converter.

Configuration as shown on Fig. 3 is the proposed large ratio dc-dc converter in the opposite direction of power flow, in the other word it is boost dc-dc converter, which also will be discussed later.

Lets us move to the control strategy of the proposed new topology large ratio buck dc-dc converter. As mentioned above the large ratio conversion in the output from the output can be done without operate the switching device in the extreme duty cycle. It can be done since by using the proposed new topology we can control each converter independently. To show the independently control, let us see Fig. 2(e) once again.

The voltage between node a and node n is the output of the first buck converter, so it can be expressed as

1

1

0 when offwhen onan

d

Sv

E S

=

(2)

If the duration of S1 off and on is called Toff1, and Ton1, respectively, and a period of a consecutive Toff and Ton is called Ts, then the average value of van in a period of switching is expressed as:

1 10.A� s off d onv T T E T= + (3)

Thus

11

onA� d d

s

Tv E E DT

= = (4)

Where vAN is the average value of van, and D1 = Ton1/Ts = vAN/Ed is the duty cycle of the switches in the first buck converter. Using similar way, then we can obtain the average value of vbn

22

onB� d d

s

Tv E E DT

= = (5)

Where vBN is the average value of vbn, and D2 = Ton2/Ts = vBN/Ed is duty cycle of the switches in the second buck converter. The load is connected across node a and b, so the load voltage can be expressed as

1dE 1S2S 1oI 2dE 3S

4S 2oI+−

dE

1S2S1oI

+−

3S4S 2oI

dE

1S2S1oI 3S

4S 2oI

dE

1S2S

oI

3S4S

( )a

( )b

( )c

( )d

( )e

1S

2S

3S

4S

dEC

La

b

n

Li

Ci oiabv ovLoad

Fig. 2. Detail of the derivation of large ratio dc-dc converter.

load A� B�v v v= − (6)

1 2load d dv E D E D= − (7)

( )1 2load dv E D D= − (8)

From (8) is clearly shown that we can obtain small value of vload if the (D1-D2) term is made

small. Thus to obtain the small value of (D1-D2), we do not have to set D1 and D2 in small value too, rather we can choose moderate value of D1 and D2 as long as the subtraction result is small. So we will get large ratio between output and input of this proposed converter, while the switching devices are operated in the moderate duty cycle. Thus we will have infinite combinations of D1 and D2 value which can be chosen to give small value of (D1-D2). But the combination of D1 and D2 around 0.5 will give the most optimum results, since with this value we will get minimum ripple in the input and output of the proposed converter compared to the other combinations of D1 and D2 values.

In the operation as boost converter, the topology derived using the same approach is shown in Fig. 3. Let us assume that voltage in the load is called vC, then according to Fig. 3,

3 2C d L S Sv E v v v= + + + (9)

dE

1S

3S 4S

2S

L

C

a

b

nFig. 3. Large ratio boost dc-dc converter

oL

oL

oC

1S

3S

dE2

dE

2dE

ov

oioL

sC

sC

oC

1S

2S

Fig. 4. (a) Two-phase, and (b) Three-level, dc-dc converter.

Where vL, vS3, vS2 are voltage across inductor, S3, and S2, respectively. vS2 itself can be expressed as

2

1

1

0 when off when onS

C

Sv

v S

=

(10)

Thus the average value of vS2 over one switching period is

2 , 1S av cv k v= (11)

Where vS2,av is the average value of vS2 and k1 is the duty cycle of the switch S1. Using the same way, the average value of voltage across S3 can be expressed:

3 , 2S av cv k v= (12)

Where vS3,av is the average value of vS3 and k2 is duty cycle of switch S2. Since the average voltage across an inductor over one switching period is zero, then (9) can be expressed as

1 2C d C Cv E k v k v= + + (13)

1 2

11 ( )c dv E

k k=

− +(14)

Clearly shown in (14), if we want to obtain very big output voltage compare to its input

voltage, then we should set the D or (k1+k2) term as near as unity. Thus we need not to set each k1 and k2 in the value near unity, as long the (k1+k2) is near unity. This is another interesting point of the proposed large ratio boost converter topology, we can obtain very high output voltage without need to operate the switches in extreme duty cycle. Examples for the application of this converter is to step up output voltage of renewable energy power generator, in order to transfer the electricity, such as photovoltaic cell, fuel cell, and others dc voltage power generator.

3. Performance of Large Ratio Dc-Dc Converter The performances of large ratio dc-dc converter will be compared to existed dc-dc

converters. They are multiphase and multilevel dc-dc converters. Large ratio dc-dc converters utilize four switches, therefore, this dc-dc converter will be compared with two-phases dc-dc converter and three-level dc-dc converter, as shown in Fig. 4. To simplify the analysis of large ratio dc-dc converter performances, buck converter will be considered in this analysis. This analysis is also valid for boost converter.

A. Ripple Analysis

At the input side of dc-dc converter, there is usually LC filter to minimize the input current ripple of converter. If dc-dc converter is utilized as power supply, then at the output side there should be another LC filter. Ripple analysis is needed to know the ripple existed at the input and output side of proposed large ratio dc-dc converter. This information is needed to determine the size of filter LC needed for the specified ripple. Commonly, ripple analysis is done with Fourier series concept. With this concept, accurate result will be obtained with all harmonics. However, this concept takes times.

Therefore, ripple analysis will be done with time domain approach. With this approach, accurate result also can be obtained without taking into account the harmonics[3]. Output Ripple Analysis

To analyze the output ripple, some assumptions will be taken into account. Voltage source is a non-ripple ideal voltage source, transistor switches and diodes are ideal switches. Capacitor filter is ideal capacitor without resistance. This analysis will be limited in continues conduction mode.

Output waveform details are shown in Fig. 6(b). abv is output voltage. Li% and ov% are the ripple current in inductor and voltage in capacitor respectively.

To analyze output ripple current, then the start point is stating the voltage a-b point as

Lab o

div L vdt

= + (15)

Current and voltage in Eq. (25) can be separated to average and ripple component as follows,

ab ab abv v v= + % (16)

L L Li i i= + % (17)

o o ov v v= + % (18) Bar sign shows the average component, and tilde sign shows ripple component. And Eq.

(25) will result

L Lab ab o o

di div v L L v vdt dt

+ = + + +%

% % (19)

Separating average from ripple component will result,

Lab o

div L vdt

= + (20)

Lab o

div L vdt

= +%

% % (21)

The capacitor ripple voltage in Eq.(31) is far less than other part, therefore can be simplified to,

Lab

div Ldt

≈%

% (22)

Hence, output ripple current is stated as

( )1L ab abi v v dt

L= −∫% (23)

and the rms value of output ripple current can be calculated with the equation, 0

0

2,

1 .st T

L rms Lt

I i dtT

+

= ∫% % (24)

Then, we can obtain

,(1 )4 3

dL rms

s

EIL f

α α−=% (25)

Where α is converter ratio, 1 1D Dα = + , and sf is switching frequency of dc-dc converter.

The following part will discuss voltage ripple analysis of large ratio dc-dc converter.

Current through the capacitor is stated by

C L Oi i i= − (26) And as explained before, the equation become,

C C L L O Oi i i i i i+ = + − −% % % (27) With

C L Oi i i= −% % % (28)

C L Oi i i= − (29) The capacitor ripple voltage in Eq.(38) is far less than other part, therefore can be simplified

to,

C Li i≈% % (30) Hence, capacitor voltage ripple can be calculated as

1 1o C Lv i dt i dt

C C= =∫ ∫% %% (31)

and the rms value of capacitor ripple voltage can be calculated with the equation, 0

0

2,

1 .st T

o rms ot

V v dtT

+

= ∫% % (32)

Then we can obtain,

( )2, 2

1 (1 ) 1 2 248 5

do rms

s

EVLC f

α α α α= − + −% (33)

Input Ripple Analysis To analyze the input ripple, some assumptions as stated before also will be taken into account. Fig. 5 shows large ratio dc-dc converter with LC filter in input side for input ripple analysis. Input side waveform details are shown in Fig. 6 (a). iD is current through S1 switch, iLs is inductor current, vCs is input capacitor voltage. From Fig. 6 (a), average input current di is

0

5.2

0

2 IdtiT

it

td

sd α== ∫ (34)

and rms value for input current is,

2.5

0

2 2

2

2 t

d ds t

o

I i dtT

Iα

=

=

∫ (35)

Then, the value of input current ripple is, 2

D oi I α α= −% (36)

Based on the Eq.(46), it can be seen that input current ripple is independent with switching frequency. The capacitor current ripple is

Cs Ls Di i i= −% % % (37) Because the current ripple in source inductor is far less then input current ripple, then

( )Cs D D Di i i i= − = − −% % (38)

From Eq.(48), then the capacitor voltage ripple can be calculated with

1S

2S

3S

4S

dEsC

La

b

n

Lsi

Csioi

Csv R

sL

Di

Fig. 5. Large ratio buck dc-dc converter with Ls and Cs.

Li%

%ov

1controlv

2controlv

triv

1refv

2refv

sT

2onT

2onT

2offT

4offT

4offT

0t 1t 2t 2.5t 3t 4t 5t

ABV

4offT

4offT

2onT

2onT

2offTST

triv

1refv

2refv

0

1controlv

2controlv

0

0

0

0I

di

Cv

A

B

Li

0t 1t 2t 5.2t 3t 4t 5t

0oi

0

Fig. 6. Ripple waveform details (a) input, and (b) output side.

1Cs Cs

s

v i dtC

= ∫ %% (39)

And the rms value is

0

0

222

sTt

Cs Css t

V v dtT

+

= ∫% % (40)

Hence, ( )1

4 3o

Css s

IVC f

α α−= =% (41)

To analyze input side inductor current ripple, input side voltage equation can be written as,

Lsd s Cs

diE L vdt

= + (42)

If ~

Li i i= + , then

cL

ss vdtidLE += (43)

cL

s vdtidL +=0 (44)

The source ripple current equation is

dtvL

i cs

L ∫−= ~1~ (45)

Hence,

( )

( )

( )

( ) ( ) ( )

( )

22

20 1

22

21 1 1 2

22

2 112 6

saat

2 112 6

2 1 saat 2

212

o

oL

O�s s

T

t t t t t

T

Ii TLC t t t t t t t

T

αα α

α

αα α

α

αα α

+ −

− − ≤ ≤

+ −

= + − − − − ≤ ≤

−

%

( ) ( ) ( )22 2 2 2.5

16

1 saat 2O�Tt t t t t t tα α

+

− − − − − ≤ ≤

(46)

Rms value of input inductor current ripple can be calculated with equation,

0

0

222 s

Tt

Ls Lss t

I i dtT

+

= ∫% % (47)

Hence,

( ) 2

2

1 1 2 248 5

oLs

s s s

II

L C fα α α α− + −

=% (48)

B. Losses Analysis The losses of DC-DC converter created by switching devices are divided into two losses.

First is switching loss, and second is conduction loss. Switching and conduction losses can be seen in Fig. 7. These waveforms are occurred in

inductive circuit with high duty cycle of switching. The circuit is inductive because it contains inductor as current source to make sure current flows to the load every time.

Area 1 is the loss when the current flow is rising, area 2 is the loss when the current flows in the reverse direction through the diode, and area 3 is charge in diode (qrr). These areas are causing high power dissipation in the transistor (switching device).

Switching loss occurs in transistors during the transition from the OFF to ON state (turn-on) and the ON to OFF state (turn-off). The equation of switching losses is given[4]:

_12S O� d o r s d o rr s d s rrp E I t f E I t f E f q= + + (49)

for turn-on losses, and

_12S OFF d s o cfp E f I t= (50)

for turn-off losses, where Ed = Supply voltage Fs = Switching frequency Io = Output current tr = Switching device current rise time trr = Diode reverse recovery time qrr = Diode reverse recovery charge tcf = Switching device turn-off recovery time

In most intended operating currents, it is more appropriate to assume that the transistor

current rise time and turn-off crossover time and the diode reverse recovery time and charge are made up of a constant component plus a component that is linierly dependent upon current[4], that is

r r tr ot T C I= + (51)

cf cf cf ot T C I= + (52)

rr rr rr ot T C I= + (53)

rr rr qr oq Q C I= + (54)

The switching loss, therefore, can be written as

_ _S S O� S OFFp p p= + (55)

( )20 1

1 22S d s o op E f C C I C I= + + (56)

where

0 2 rrC Q= (57)

1 2 2r cf rr qrC T T T C= + + + (58)

2 2tr cf rrC C C C= + + (59)

Conduction loss occures due to voltage drops across transistors and diodes during conduction. These voltages which are functions of the current that flows through them cn be approximated as the following linear functions:

T T T Sv V R I= + (60) for transistors, and

D D D Sv V R I= + (61) for diodes. Conduction losses are the product of the ON state voltage of the switching device and the

current flowing through it. The equation of conduction losses is then

2T T S T S rmsp V I R I= + (62)

for transistor, and 2

D D S D S rmsp V I R I= + (63) for diode, where

RT / RD = Switching device’s resistance. VT / VD = ON state voltage. Is = Current flow through switching device

To achieve the losses equation, then we must calculate the average and rms value of current

flowing through each switches. Average values are,

11 1

1

onSS o o

sS

TI I D IT

= = (64)

( )12 1

1

1offSS o o

sS

TI I D I

T= = − (65)

CI

( )CE satV

CEV

rt rrt cft

1

CI

3

2

+−

CEV

CI

DICV

Fig. 7. Model of switching waveforms during turn-on and turn-off.

33 2

3

onSS o o

sS

TI I D IT

= = (66)

( )34 2

3

1offSS o o

sS

TI I D I

T= = − (67)

Where TonS1 and TonS3 are ON time for S1 and S3; ToffS1 are ToffS3 are OFF time S1 and S3; TsS1 and TsS3 are switching period for S1 and S3; D1 and D2 are duty cycle for each S1 and S3.

The rms values are

12

1, 11 0

1 onST

S rms o osS

I I dt D IT

= =∫ (68)

( )2, 11S rms oI D I= − (69)

3, 2S rms oI D I= (70)

( )4, 21S rms oI D I= − (71)

From Eq.(74)-(81), we can obtain total switching loss,

( ) ( )( )20 1 2

1 2 1 12s d s o oP E f C C I C Iα α= + + + + (72)

and total conduction loss,

( ) ( ) ( ) ( )2 21 1 1 1c T o T o D o D oP V I R I V I R Iα α α α= + + + + − + − (73)

Hence, the total losses is

S s cP P P= + (74)

( ) ( )( )( ) ( ) ( ) ( )

20 1 2

2 2

1 2 1 12

1 1 1 1

d s o oS

T o T o D o D o

E f C C I C IP

V I R I V I R I

α α

α α α α

+ + + + + = + + + + − + −

(75)

C. Comparison

The equations for those performances in two-phase and three-level dc-dc converter are shown in Table 1 and Table 2. To simplify the comparison, the results obtained in Table 1 and 2, are drawn. Fig. 8 shows source current ripple, and Fig.9 shows it in extreme duty cycle. Fig. 10 shows output current ripple, and Fig. 11 shows it in extreme duty cycle.

Fig.12 shows the total loss comparison between three dc-dc converters. It can be seen that large ratio dc-dc converter results the largest loss for all duty cycle. In large ratio dc-dc converter, current flows through two switches. Therefore, large ratio dc-dc converter has bad performance in loss aspect.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.5

1

1.5

2

2.5x 10-5

Rasio TeganganR

iak

Aru

sS

umbe

r(A

)

konverter dua fasakonverter tiga levelkonverter rasio tinggi

Fig. 8. Source current ripple comparison.

0 0.01 0.02 0.03 0.04 0.05 0.060

0.5

1

1.5

2

2.5

3

3.5x 10-7

Rasio Tegangan

Ria

kA

rus

Sum

ber(

A)

konverter rasio tinggikonverter dua fasakonverter tiga level

Fig. 9. Source current ripple comparison for extreme voltage ratio.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

Rasio Tegangan

Ria

kA

rus

Kel

uara

n(A

)

konverter rasio tinggikonverter dua fasakonverter tiga level

Fig. 10. Output current ripple comparison.

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.050

0.005

0.01

0.015

0.02

0.025

0.03

Rasio Tegangan

Ria

kA

rus

Kel

uara

n(A

)

konverter tiga levelkonverter dua fasakonverter rasio tinggi

Fig. 11. Output current ripple for extreme voltage ratio.

0 1 2 3 4 5 6 7 8 9 100

10

20

30

40

50

60

Arus Keluaran (A)

Rug

i-rug

itot

al(W

)

rasiotinggiduafasatigalevel

Large ratioTwo-phaseThree-level

Output current (A)

Fig. 12. Total losses comparison.

4. Control Technique for Large Ratio Dc-Dc Converter Current controller has been used in many converter applications[6]-[8]. Current control has

the advantage in current protection especially when short circuit occurred. In addition, the use of current controller enables parallel operation of two or more similar converters. Thus the power capacity can be increased. Commonly, in dc-dc converter applications, the current control is used in double-loop controller. In this scheme, voltage controller is in the outer loop while current controller is in the inner loop. The output of voltage controller will be the input for current controller.

In the proposed controller, hysteresis current controller is used while PI controller is used as voltage controller as can be seen in Fig. 13. The error signal between output and reference voltage will be the input for hysteresis current controller. The output signal from hysteresis current controller will determine switching signals. Since two separated switching signals are required, additional logic circuit is needed to produce these signals from hysteresis output signal.

Whenever output voltage is lower than reference voltage, the required inductor current will be increased. Hence, the duty cycle will be increased. In contrast, the duty cycle will be decreased whenever output voltage is higher than reference voltage in which the inductor current will be lessened. In order to maintain well operation, the current controller has to be faster in response than the voltage controller. The proposed control technique block diagram is

shown in Fig. 14.

Fig. 14 Block diagram of control system in high ratio boost converter.

The simplicity and stability of hysteresis controller is applied in the proposed control technique. Basically, hysteresis current controller is the controller in which the allowed error signal is limited to the given hysteresis band. If the inductor current exceeds the upper band limit, then the switch is off and the current is decreasing. Then if the inductor current exceeds the lower band limit, the switch turn on provided the rising in current. The process keeps on going so as to keep the inductor current follows the hysteresis band path (Fig. 15).

The instantaneous inductor current can be written as the sum of average component and ripple component as follow:

Fig. 15 Current controller with hysteresis band in boost converter.

∑

Fig. 13 Control technique for high ratio boost converter.

LLL iii += (76)

where LL iandi are average and ripple component of inductor current respectively. Fig. 15

depicts that the average inductor current is equal to the reference while the maximum inductor current ripple is ±δ, where δ is hysteresis half band and can be expressed as:

δ±± refLL iii max (77)

In boost converter the inductor current can be written as follow:

( ) 01

L S O Li v v dt iL

= − +∫ (78)

where iL0 is the initial inductor current. When the switch is on then vo in (78) is zero, hence the inductor current is as follow:

( ) ; for 0SL L O�

vi t i t T

Lδ= + − < < (79)

From Eq. (77) and (79), we get TO� switch as follow 2

O�S

LTvδ= (80)

Inductor current when the switch is off can be written as

( ) ; for 0S OL L OFF

v vi t i t T

Lδ

−= + + < < (81)

Note that in (81) the output voltage is bigger than input voltage; therefore the inductor current will decrease. From equations (77) and (81), we get TOFF of the switch as

2OFF

O S

LTv v

δ=−

(82)

As boost converter, then the requirement is

1 2 <1k k+ (83) To minimize current ripple caused by switching process, then

1 2k k= (84) For balancing the switching patterns and fulfilling the Eq. (83) – (84), so

( ) ( )1 24

2 2 OS S S O� OFF

S O S

v LT T T T T

v v vδ

= = = + =−

(85)

From Eq (85), the operation frequency can be written as

1 21 1 ; with

4o

S Ss

vf f vLα α

δ α− = = =

(86)

For extreme input-output ratio, the switching frequency can be approximated to 1

4Sf Lδ≈ (87)

The switching signals in both switches are differed and separated. In order to keep the balance and one after another operation of switching signals, logic circuit is required to be added to hysteresis current controller. Thus, it can be obtained that

1 2O� O�T T= (88)

( )( )

1 1

2 2

2 ; 0, 1, 2, ...

2 ; 0, 1, 2, ...S

S

t t n T n

t t n T n

= + =

= + = (89)

( )( )

1 2

2 1

2 1 ; 0, 1, 2, ...

2 1 ; 0, 1, 2, ...S

S

t t n T n

t t n T n

= + + =

= + + = (90)

Where TSx and tx are switching period and state at the time t respectively. From equations (89) and (90) it can be seen that the switching signals are never collided.

Because of the hysteresis control system used is non-linear; the simplification can be done to ease the analysis. In designing the voltage controller we can assume that the current controller is well-operated provided the reference is equal to the inductor current. The output voltage of boost converter can be expressed as follow:

( )

1 ; untuk 0

1 ; untuk 0

O O O�

O L O OFF

v i dt t TC

v i i dt t TC

= − < <

= − < <

∫

∫(91)

With the assumed well-operated current controller, the block diagram in Fig. 14 can be simplified to the one in Figure 16. From the figure, Gc*(s) is ‘1’ when the

switch is on and ‘0’ when the switch is off. The consequence of this condition made the proposed voltage controller is non-linear. To simplify the analysis, the linearization process can be used.

Eq. (91) can be written as

( )1OL O

dvC k i i

dt= − − (92)

where k is the various duty factor and can be express as %k k k= + (93)

with the sign ‘~’ indicate the ripple component with the properties as follow: % ( )%

1 ; 0

;

O�

O� S

k k t T

k k T t T

= − < <

= − < < (94)

We can express the Eq. (92) in respect to the voltage ratio for boost converter as

( )* ; *O SL O

O

dv vC i i

dt vα α= − = (95)

Splitting the Eq. (95) to the average and ripple component we can get

)()*)(*()(ooLL

oo iiiidt

vvdC +−++=+ αα (96)

Because of average component in the left side of the equation is zero, and assuming that the multiplication of ripple components is negligible, we can express Eq. (96) as

)().*().*( oLLo iii

dtdvC −+= αα (97)

The Eq. (97) is valid for small signal analysis. Using the above equation, the response of output voltage because of small duty cycle or load deviation can be analyzed. For each response, we get

)(.*)(*)(

sGsCI

ssv

v

Lo

αα += (98)

)(.*1

)()(

sGsCsIsv

vo

o

α+−= (99)

From Eq. (97), the block diagram can be redrawn as can be seen in Figure 16.

The proposed voltage controller is the commonly used proportional-integral (PI). This PI controller can eliminate steady-state error. We can get the desired transient and steady-state response using the optimally adjusted control system parameter. Applying proportional and integral constant to Gv*(s) in Figure 16 we can get output voltage response in respect to reference and load current as follow:

ip

Lo

KKsCsIs

ssV

**)(*)(

2 ααα ++−= (100)

ipo

o

KKsCss

sIsV

**)()(

2 αα ++−= (101)

Using switching frequency of 2kHz and hysteresis band of 400mA, from (87) we get the

inductance Ls as large as 0.625mH. In order to make the voltage controller response slower than the current controller, we can take the minimum criteria in which current controller response is ten times greater than voltage controller response. Hence, using system parameter C = 220µF, it is obtained that Kp = 0.2 and Ki = 2000 in which the good transient response can be obtained. Bode diagram of output voltage response in respect to the duty cycle and load current changes can be seen in Fig. 17.

(a)

(b)

Figure 16 (a) voltage controller block diagram and (b) simplified voltage controller block diagram

5. Experimental Results In order to verify the proposed topology, a small proposed large ratio dc-dc converter

topology has been constructed based on Fig. 2(e) for buck converter and Fig. 3 for boost converter.

A. Ripple Analysis Fig. 18 and Fig. 19 show experimented result of output current ripple and source current

ripple in large ratio buck dc-dc converter. As can be seen, the experimented results appropriate to the calculated results.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

Duty Cycle

Ria

kAr

usKe

luar

an(A

)

perhitunganeksperimen

Out

putC

urre

ntR

ippl

e(A

)

Fig. 18. Experimented result of output current ripple.

-40

-20

0

20

40

60

Mag

nitu

de(d

B)

100 101 102 103 104-90

-45

0

45

90

Phas

e(d

eg)

Bode Diagram

Frequency (rad/sec) (a)

-60

-40

-20

0

20

40

Mag

nitu

de(d

B)

100

101

102

103

104

90

135

180

225

270

Phas

e(d

eg)

Bode Diagram

Frequency (rad/sec) (b)

Fig. 17 (a) bode diagram of output voltage response vs. duty cycle and (b) load current

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.90

0.05

0.1

0.15

0.2

0.25

0.3

0.35

Rasio Tegangan

Ria

kAr

usSu

mbe

r(A)

perhitunganeksperimen

Sour

ceC

urre

ntR

ippl

e(A

)

Fig. 19. Experimented result of source current ripple.

B. Loss Analysis Fig. 20 shows the experimented result compared with calculated result. As can be seen that

the experimented result approaching the calculated result. The differences are caused by either inaccurate parameter and output current contains ripple in experiment.

0 1 2 3 4 5 6 7 80

5

10

15

20

25

30

35

40

Arus Keluaran (A)

Rug

i-rug

i(W

)

perhitungan rugi totalperhitungan rugi konduksieksperimen rugi totaleksperimen rugi konduksi

Loss

es(W

)

Fig 20. Experimented result of total losses.

C. Control Technique Experiments is done to see the system response as the consequence of load disturbance and

reference voltage changes. In current controller, current sensor used has the parameter of 2A/V and hysteresis band of 400mA. Experiment results for load disturbances can be seen in Fig. 21. With the existence of load disturbance, the output voltage is constant.

The experiment results using input voltage with some ripple component is drawn in Fig. 22. We can see that output voltage is not altered by high frequency ripple components in input voltage. With the reference voltage changed, experiment results is as can be seen in Fig. 23. In the low frequency, the output voltage will follow the voltage given by the reference. But in higher frequency, the output voltage cannot follow the reference anymore.

1 >

2 >

Fig. 21 Output voltage signal (25V/div) when load is changed (500mA/div) at 250ms/div.

1 >

2 >

Fig. 22 Output voltage signal (25V/div) when input voltage contain some ripple (5V/div) at 10ms/div.

1 >

2 >

Fig. 23 Output voltage signal (25V/div) in respect to reference (20V/div) at 250ms/div.

6. Conclusions A large ratio dc-dc converter topology is derived. This high ratio dc-dc converter topology

is able to convert its input voltage into very small/big output voltage without need to operate its switching devices in the extreme duty cycle as in the conventional dc-dc converter.

Analytic equation for input and output ripple of large ratio has been discussed. At extreme voltage ratio, large ratio dc-dc converter has smaller or equal ripple than two-phase and three-level dc-dc converter. Analytic equation of switching and conduction losses has been derived. The total loss of large ratio dc-dc converter is larger than the others.

Control technique of large ratio boost dc-dc converter has been discussed. Double loop control technique with hysteresis current controller and PI voltage controller is proven to work well in existence of load disturbance to maintain output voltage.

Large ratio boost dc-dc converter is appropriate for renewable energy power generator with low dc voltage output. Experimental result has been included to verify the proposed topology.

References [1] Agus Purwadi, K.A. Nugroho, F. Sasongko, K.F. Sutrisna, and P.A. Dahono, “Performance

Evaluation and Control Technique of Large Ratio DC-DC Converter”, to be published in ICEEI 2009. Malaysia.

[2] Agus Purwadi, P.A. Dahono and A. Rizqiawan, “A New Approach to Synthesis of Static Power Converters”, to be published in ICEEI 2009. Malaysia

[3] A. Husnan Arofat, P. A. Dahono. ”Output Current Ripple Analysis of Multiphase Chopper”. Electrical Machine and Power Electronics (SMED) 2005, Dec. 2005. Malang

[4] J.H. Rockott. “Losses in High-Power Bipolar Transistors”. IEEE Trans. Power Electronics,PE-2, No. 1, 72. 1987

[5] P. A. Dahono, Y. Sato, and T. Kataoka. “Analysis of Switching and Conduction Losses in Hysteresis Current-Controlled Inventers”, Trans IEE of Japan, Vol. 113-D, No. 10, Oct., 1993.

[6] Dixon Juan. W., Ooi Boon T., “Series and Parallel Operation of Hysteresis Current-Controlled PWM Rectifiers”, IEEE Trans. on Industry Applications, Vol. 25, No. 4, 1989.

[7] Shin Eun-Chun. et. al, “A Novel Hysteresis Current Controller to reduce the Switching Frequency and Current Error in D-STATCOM”, The 30th Ann. Conf. of the IEEE Industrial Elect. Society, November, 2004.

[8] Tilli Andrea, Tonielli Alberto, “Sequential Design of Hysteresis Current Controller for Three-Phase Inverter”, IEEE Trans. on Industrial Electronics, Vol. 45, No. 5, 1998.

[9] Dahono P.A., et al., “Output Ripple Analysis of Multiphase DC-DC Converters”, Proc. IEEE PEDS’99, July 1999, Hongkong, pp. 626-631

[10] Dahono, P.A., “A New Multi Level DC-DC Converter”, International Conference on Electrical Engineering, Sapporo, 2004.

Table 1. Ripple equations for dc-dc converters.

Parameter Two-Phase Three-level Large ratioOutput CurrentRipple ( oI% )

2

2

for 0 1/ 2(1 2 )

( ) 2 3for 1/ 2 1

(1 )(2 1)( ) 2 3

d

s

d

s

EL f

EL f

αα α

αα α

≤ ≤−

≤ ≤− −

12 2

for 0 1/ 2

( 0.25)4 3

for 1/ 2 1(1 )(2 1)

4 3

d

s

d

s

EL f

EL f

α

α α α

αα α

≤ ≤

− +

≤ ≤− −

(1 )4 3

d

s

EL f

α α−

Output VoltageRipple

2 1 2

2

2 1 2

2

if 0 1 2 :(1 2 )(1 4 8 )

( ) 24 5

if 1 2 1:(1 )(2 1)( 3 12 8 )

( ) 24 5

d

s

d

s

Ef C L M

Ef C L M

αα α α α

αα α α α

≤ ≤− + −

+

≤ ≤− − − + −

+

( )22

1 (1 ) 1 2 248 5

d

s

ELC f

α α α α− + −

Source Current

Ripple ( LI~ ) ( )

( )

2

2

2

2

for 0 1/ 2

1 2 1 4 848 5

for 1/ 2 1

2 1 (1 ) 3 12 848 5

o

s s s

o

s s s

IL C f

IL C f

α

α α α α

α

α α α α

≤ ≤

− + −

≤ ≤

− − − + −

( )

( )

2

2

2

2

for 0 1/ 2

2 1 2 1 4 848 5

for 1/ 2 1

2 2 1 (1 ) 3 12 848 5

o

s s s

o

s s s

IL C f

IL C f

α

α α α α

α

α α α α

≤ ≤

− + −

≤ ≤

− − − + −

( )180

2218

1 2

2

αααα −+

−

sss

o

fCLI

arameter Two-Phase Three-level Large ratioitchingsses 2

0 1 21 12 4d s o oE f C C DI C DI + +

( )2

0 1 212 d s o oE f C C DI C DI+ + ( ) ( )( )2

0 1 21 2 1 12 d s o oE f C C D I C D I+ + + +

nductionsses ( )

( )

2

2

1 12

1 12

T o T o D o

D o

V DI R DI V D I

R D I

+ + − + −

( )( )

2

2

2 2 2 1

2 1T o T o D o

D o

V DI R DI V D I

R D I

+ + − + −

( ) ( )( ) ( )

2

2

1 1

1 1T o T o

D o D o

V D I R D I

V D I R D I

+ + + + − + −

talsses

( )

( )

20 1 2

2

2

1 12 4

1 12

1 12

d s o o

T o T o D o

D o

E f C C DI C DI

V DI R DI V D I

R D I

+ + +

+ + − + −

( )( )

( )

20 1 2

2

2

122 2 2 1

2 1

d s o o

T o T o D o

D o

E f C C DI C DI

V DI R DI V D I

R D I

+ + +

+ + − +

−

( ) ( )( )( ) ( )( ) ( )

20 1 2

2

2

1 2 1 12

1 1

1 1

d s o o

T o T o

D o D o

E f C C I C I

V I R I

V I R I

α α

α α

α α

+ + + + +

+ + + +

− + −

Table 2. Losses equations for dc-dc converters.