Performance and Design Considerations for Gate-All-around ... · Performance and Design...
Transcript of Performance and Design Considerations for Gate-All-around ... · Performance and Design...
Performance and Design Considerations for Gate-All-around
Stacked-NanoWires FETs
S. Barraud, V. Lapras, B. Previtali, M.P. Samson, J. Lacord, S. Martinie,
M.-A. Jaud, S. Athanasiou, F. Triozon, O. Rozeau, J.M. Hartmann, C.
Vizioz, C. Comboroure, F. Andrieu, J.C. Barbé, M. Vinet, and T. Ernst
CEA-LETI, Minatec Campus, Grenoble, France
STMicroelectronics, Crolles, France
Context of this work
22nm INTEL
14nm INTEL
16nm TSMC
14nm SAMSUNG
3D FinFET
2D FDSOI
28nm ST
22nm GF
Back-gate control using
thin BOX capacitive
Single-gate reduction
of SCE controlled by
thinner TSi or TBOX
?
New MOSFET
architectures need
to be proposed
Two main MOSFET architectures for advanced CMOS
2.
Context of this work
Max M. Shulaker et al., Nature 2017, Stanford
Plenty of space … at the top !
3.
2017 press releases
4.
May │ 2017Samsung set to lead the future of foundry with comprehensive process roadmap down to 4nm
4LPP (4nm Low Power Plus): 4LPP will be the first implementation of next generation device
architecture – MBCFETTM structure (Multi Bridge Channel FET). MBCFETTM is Samsung’s unique
GAAFET (Gate All Around FET) technology that uses a Nanosheet device to overcome the
physical scaling and performance limitations of the FinFET architecture.
https://news.samsung.com/global/samsung-set-to-lead-the-future-of-foundry-with-
comprehensive-process-roadmap-down-to-4nm
June │ 2017IBM claims 5nm Nanosheet breakthough
IBM researchers and their partners have developed a new transistor architecture based on Stacked
Silicon Nanosheets that they believe will make FinFETs obsolete at the 5nm node
http://www.eetimes.com/document.asp?doc_id=1331850&
GAA MOSFET devices are becoming an industrial reality
3D stacked structures
5.
15 years of innovation
T. Ernst et al. ,
IEDM06
First Stacked
NW CMOS
10-14
10-12
10-10
10-8
10-6
10-4
-1 -0.5 0 0.5 1 1.5 2
Dra
in C
urr
en
t I D
(A
)
Gate 1 voltage VG1
(V)
VD=50mV L=550nm V
G2=0.8 to -1.4V
step = -0.2V
3T-FET4T-FET
SS
=62m
V/d
ec.
SS
=82m
V/d
ec.
VG2VG1
VS
VD
4T-FET
VG
VD
3T-FET
exx
eyySi0.7Ge0.3
Si0.7Ge0.3
Si0.7Ge0.3
Si0.7Ge0.3Si Si
exx
Si Si
eyy
Si0.7Ge0.3
Si channel
Si channel
Inner spacer
Si0.7Ge0.3
Si channel
Si channel
Si Si
Inner spacer
In-plane deformation
Out-of-plane deformation
In-plane deformation
Out-of-plane deformationa b
Nanowires with
independent
gates
Internal spacers
introduction
ONO
crystalline
3D Flash Strain
booster
High density
13 crystalline
levels !
E. Bernard et al.
VLSI 08
LETI - STM
A. Hubert et al.
IEDM 2008 -LETI
S. Barraud et al.
IEDM 2016C. Dupré et al. LETI
IEDM 2008 T. Ernst et al.
Micro. Eng. 2011
IBM
N. Loubet & al. (VLSI 2017)
MultiBridge
Channel
MOSFETS.Y. Lee et al SAMSUNG
IEEE Trans Nano 2003
10 15 20 25 30 35 40
20
40
60
DIB
L (
mV
/V)
Gate length (nm)
From FinFet to stacked NW
14nm INTEL [1]
Fin FETs GAA Wire FETs
[2] H. Mertens et al., VLSI Technology, 2016.
[1] S. Natarajan et al., IEDM, 2014.
IMEC [2]
GAA 7nm
LG=10nm
W=7nm, HFin=45nm
FinFET
6.
TCADSame process (LETI 2008 – IEDM)
Switching delay, ps
En
erg
y p
er
sw
itch
, fJ
• Increase Ieff per footprint
• Decrease Ceq per footprint
Alternative
options: GAA
structures
ELECTROSTATICS
FF/NW/NS
MOBILITY
FF/NW/NSCPARASITICS
FF/NW/NS
Motivation/Objective
3 Fins
Layout
Footprint
(LF)
Metal
Gate
Fins
Contact
FP
CPPDevice architecture scaling
CPP scaling
LG reduction
Electrostatic booster
to keep low
leakage current
Device FabricationFF/NW/NS
7.
Outline
• Performance/Design consideration
• Device Fabrication
– Inner spacer
– SiGe S/D
• Strain Characterization
– Precession Electron Diffraction
• Perspectives
• Summary and Conclusion
8.
0,2 0,4 0,6 0,8
40
80
120
Fo
otp
rin
t (n
m)
Weff
(µm)
NW
FF
FinFET
Weff=circonference of Fin (2HFin+W)
TCAD
9.
Layout footprint (nm)
Layout fo
otp
rint (n
m) FF W=7nm
HFin=43nm
0,2 0,4 0,6 0,8
40
80
120
Footp
rint (n
m)
Weff
(µm)
NW
FF
Layout fo
otp
rint (n
m)
FinFET to GAA NanowiresLayout footprint (nm)
Weff=circonference of Fin (2HFin+W)
FFNW W=7nm
HFin=43nm
-14%
10.
?
TCAD
0,2 0,4 0,6 0,8
40
80
120
Fo
otp
rin
t (n
m)
Weff
(µm)
NW
NS
FF
GAA Nanowires to Nanosheets
Weff=circonference of Fin (2HFin+W) 11.
82nm
57nm
32nm
107nm
132nm
W=82nm
W=32nm
W=15nm
+5% weff
+24% weff
+42% weff
x3GAA
WNS
0 20 40 60 80 100 120 140
30
40
50
60
DIB
L (
mV
/V)
WNS
(nm)
Short-channel effects
12.
FinFET (HFin=43nm, W=7nm)
TCAD (LG=16nm)
Electrostatics of multi-gates MOSFET transistors
1st boundary
condition
0 20 40 60 80 100 120 140
30
40
50
60
DIB
L (
mV
/V)
WNS
(nm)
Short-channel effects
13.
FinFET (HFin=43nm, W=7nm)
Electrostatics of multi-gates MOSFET transistors
1st boundary
condition
2nd boundary
condition
• Strong reduction of DIBL for Gate-all-around nanowire. → Optimal electrostatics control!
NW
TCAD (LG=16nm)
0 20 40 60 80 100 120 140
30
40
50
60
DIB
L (
mV
/V)
WNS
(nm)
Short-channel effects
14.
FinFET (HFin=43nm, W=7nm)
Electrostatics of multi-gates MOSFET transistors
1st boundary
condition
NW 2nd boundary
condition
• GAA Nanosheets (thin and wide wires) show intermediate DIBL
between NW and FinFET. DIBL depends on wire width (W).
TCAD (LG=16nm)
• GAA stacked-nanosheets maximize Weff (drive current)
per layout footprint with improved channel electrostatics.
LG=13nm
LF=57nm
FF
15.
Tradeoff between SCE and Weff
FF
NW
NS
0,2 0,420
30
40
50
60
DIB
L (
mV
/V)
Weff
(µm)0,4 0,6
20
30
40
50
60
DIB
L (
mV
/V)
Weff
(µm)
0,4 0,620
30
40
50
60
DIB
L (
mV
/V)
Weff
(µm)
LG=13nm
LF=82nmLG=13nm
LF=107nm
FF FF
NW NW NW
Power/Perf. Optimization
GAA Nanosheet transistors offers more freedom to
designers for the power-performance optimization thanks
to a fine tuning of the device width.16.
0,5 1,0 1,510
-2
10-1
100
Norm
aliz
ed I
OF
F
Normalized ION
LF=57nm
LF=82nm
LF=107nm
FP=25nm
3 stacked GAA
LG=16nm
HNW=6.5nm
FF
LP
HP
W=7nm
13nm15nm
19.5nm
24nm
32nm57nm
Parasitic capacitances and delay
17.
With ) & )
t: Delay
Ieff: Effective drive current
Ieff=(IH+IL)/2
IH=IDS(VGS=VDD, VDS=VDD/2)
IL=IDS(VGS=VDD/2, VDS=VDD)
Supply voltage VDD=0.7V
FO=3
LG=16nm
Spacer size: 4.2nm
EOT=0.67nm
Cback-end=2fF
M=2: Miller effect in inverter
FF NW
-40 -20 0 20 40-10
0
10
20
Ceq (%)
Ceq (%)
tp (%)tp (%)
LF=82nm (4 Fins with FP=25nm)
LF=57nm (3 Fins with FP=25nm)
57nm
19.5nm
82nm
32nm
15.3nm
NW
(W=7nm)
Ceq is reduced for NWs (W=7nm)
but no delay reduction is achieved,
while performance can be
significantly improved for
nanosheet design having wider
wires. A delay reduction of around
20% is expected for WNS~30nm
Number of Stacked-GAA NS
2 3 4 5 6 7 8 9 10 110
10
20
30
40
50
60
70
80
t p r
eduction (
%)
Number of stacked GAA
0.5fF
1fF
2fF
4fF
6fF
HFin=29nm HFin=72nm HFin=115nm
High Ieff Increase
vs Ceq increase
LF=57nm
W=19.5nm
VDD=0.7V
Saturation of tp reduction when the number of stacked
nanowires increase (Ieff increase from N to N+1 is close to Ceq
increase). 18.
Electron mobility in NW/NS
In GAA NanoSheet, µelectron is increased due to high mobility
in the (100) plan.
FF mobility
19.
Hole mobility in NW/NS
FF mobility
Horizontal GAA NS for n-FETs and vertical GAA NS for p-FETs turn out
to be the most effective solutions to promote electron and hole
transport, respectively.
[110] FinFET
20.
Outline
• Performance/Design consideration
• Device Fabrication
– Inner spacer
– SiGe S/D
• Strain Characterization– Precession Electron Diffraction
• Perspectives
• Summary and Conclusion
21.
Devices FabricationxN-(SiGe/Si) EPI
Growth
(Si0.7Ge0.3/Si)Fin Patterning
TEOS/Poly-SiDummy Gate
CMP Poly-Si
Dummy GatePatterning
RMG Process
300mm (100) SOI substrates
(Si/SiGe) multilayer:
Option1:(Si/SiGe/Si) ≡
(12nm/12nm/12nm)
Option2:(Si/SiGe/Si/SiGe/Si) ≡
(7nm/8nm/7nm/8m/7nm)Spacer 0
Deposition/Etch
Inner SpacerDeposition/Etch
S/D EPI Growth
Spacer 1Deposition/Etch
ILD and CMP
Dummy Gateremoval
Release of stacked-NW
RMG moduleHfO2/TiN/W
Contact
BEOL modules
Horizontal Wires 1.
2.
3.
4.
5.
Grey steps are not different
that FinFET process-Flow 22.
Devices Fabrication
Superlattice (SiGe/Si)
Fin Patterning
Dummy Gate Deposition
& RIE
Spacer Deposition and RIE
Source/Drain Epitaxy
ILD & CMP
Dummy Gate Removal
Formation of Suspended NW
(release of NW)
Gate Stack Formation
Contact/BEOL
Inner spacer formation
Vertically stacked wires FETs
Process-Flow
23.
Devices Fabrication
Superlattice (SiGe/Si)
Fin Patterning
Dummy Gate Deposition
& RIE
Spacer Deposition and RIE
Source/Drain Epitaxy
ILD & CMP
Dummy Gate Removal
Formation of Suspended NW
(release of NW)
Gate Stack Formation
Contac/BEOL
Inner spacer formation
Vertically stacked wires FETs
Process-Flow
Individual and dense arrays of
fins were patterned to fabricate
stacked wires FETs. 40 nm Fin
pitch / 60 nm height / 20 nm
width
24.
S. Barraud & al. (IEDM 2016)
Devices Fabrication
Superlattice (SiGe/Si)
Fin Patterning
Dummy Gate Deposition
& RIE
Spacer Deposition and RIE
Source/Drain Epitaxy
ILD & CMP
Dummy Gate Removal
Formation of Suspended NW
(release of NW)
Gate Stack Formation
Contac/BEOL
Inner spacer formation
Vertically stacked wires FETs
Process-Flow
Not different that FinFET
SiO2/Poly-Si
Dummy Gate
spacer
25.
Devices Fabrication
Superlattice (SiGe/Si)
Fin Patterning
Dummy Gate Deposition
& RIE
Spacer Deposition and RIE
Source/Drain Epitaxy
ILD & CMP
Dummy Gate Removal
Formation of Suspended NW
(release of NW)
Gate Stack Formation
Contac/BEOL
Inner spacer formation
Vertically stacked wires FETs
Process-Flow 1. 2.
3. 4.
5.
Definition and benefit of inner spacer ?
13.
5.
Si
Si
SiGe
Fin
recess
SiGe
etchingInner
spacerRaised-
S/D
Devices Fabrication
Superlattice (SiGe/Si)
Fin Patterning
Dummy Gate Deposition
& RIE
Spacer Deposition and RIE
Source/Drain Epitaxy
ILD & CMP
Dummy Gate Removal
Formation of Suspended NW
(release of NW)
Gate Stack Formation
Contac/BEOL
Inner spacer formation
Vertically stacked wires FETs
Process-Flow
After the Fin recess
Fin recess SiGe etching
27.
Devices Fabrication
Superlattice (SiGe/Si)
Fin Patterning
Dummy Gate Deposition
& RIE
Spacer Deposition and RIE
Source/Drain Epitaxy
ILD & CMP
Dummy Gate Removal
Formation of Suspended NW
(release of NW)
Gate Stack Formation
Contac/BEOL
Inner spacer formation
Vertically stacked wires FETs
Process-Flow
0 10 20 30 40 50 600
20
40
60
80
100
120
140
SiG
e E
tch
ing
(n
m)
Time (sec)
Etch rate Ge 45%
Ge 30%
Second step
Etch depth profile with Si 7nm and SiGe 8nm
28.
Devices Fabrication
Superlattice (SiGe/Si)
Fin Patterning
Dummy Gate Deposition
& RIE
Spacer Deposition and RIE
Source/Drain Epitaxy
ILD & CMP
Dummy Gate Removal
Formation of Suspended NW
(release of NW)
Gate Stack Formation
Contac/BEOL
Inner spacer formation
Vertically stacked wires FETs
Process-Flow
The depth of the SiGe recess was adjusted to
match the thickness of future inner spacers
50nm
29.
Devices Fabrication
Superlattice (SiGe/Si)
Fin Patterning
Dummy Gate Deposition
& RIE
Spacer Deposition and RIE
Source/Drain Epitaxy
ILD & CMP
Dummy Gate Removal
Formation of Suspended NW
(release of NW)
Gate Stack Formation
Contac/BEOL
Inner spacer formation
Vertically stacked wires FETs
Process-Flow
LG=20nm
Spacer=9nm
TSi=12nm
TSiGe=12nm
30.Which benefits for parasitic capacitances?
S. Barraud & al. (IEDM 2016)
IBM
N. Loubet & al. (VLSI 2017)
GAA nanosheet (x3)
TSi=5nm
TSiGe=10nm
44/48 CPP ground
rules
CEA-LETI
10 15 20 25 30 35-40
-35
-30
-25
-20
-15
-10
CG
D r
eduction (
%)
NW width (nm)
Benefit of inner spacer
31.
Inner spacer is crucial for reducing intrinsic capacitances
and to improve dynamic perf.
10 20 30 40 50 60-40
-35
-30
-25
-20
-15
-10
Cgd
red
uctio
n (%
)
Gate length (nm)
W=15nm
W=20nm
W=30nm
Inner spacer is crucial for reducing
intrinsic capacitances and to
improve dynamic performances.
10 20 30 40 50 60-40
-35
-30
-25
-20
-15
-10
Cgd
red
uctio
n (%
)
Gate length (nm)
W=15nm
W=20nm
W=30nm
Inner spacer is crucial for reducing
intrinsic capacitances and to
improve dynamic performances.
NW
NS
L. Gaben & al., ECS (2016)
The benefit of inner spacer is higher as the width is
increased 30-40% reduction of Cgd (W=20/30nm)
TCAD
Devices Fabrication
Superlattice (SiGe/Si)
Fin Patterning
Dummy Gate Deposition
& RIE
Spacer Deposition and RIE
Source/Drain Epitaxy
ILD & CMP
Dummy Gate Removal
Formation of Suspended NW
(release of NW)
Gate Stack Formation
Contac/BEOL
Inner spacer formation
Vertically stacked wires FETs
Process-Flow
In-situ Boron doped SiGe(:B) Source/Drain
In-situ Phosphorus doped Si(:P) Source/Drain
J. M. Hartmann et al., Thin Solid Films, 520, p. 3185, 2012.
J. M. Hartmann et al., Solid State Electronics, 83, p. 10, 2013. 32.
Wide variety of stacked-wires
33.
NW NS
NW/NS Cross-section
Along source-drain direction
Si channel
Si channel
Inner spacer
SiGe SiGe
Short-LG (20nm) Long-LG (>300nm)
After HfO2/TiN/W deposition (LG=200nm)
LETI
S. Barraud & al., IEDM 2016
Strain characterization
Superlattice (SiGe/Si)
Fin Patterning
Dummy Gate Deposition
& RIE
Spacer Deposition and RIE
Source/Drain Epitaxy
ILD & CMP
Dummy Gate Removal
Formation of Suspended NW
(release of NW)
Gate Stack Formation
Contac/BEOL
Inner spacer formation
1.
2.
3.
4.* M.P. Vigouroux et al., APL 105, 191906 (2014)
Strain maps were obtained by
TEM using Precession Electron
Diffraction technique*
* D. Cooper et al., Nano Lett. 15, 5289 (2015)
Strain engineering is another
key factor for stacked-wires
FETs.
34.
Is initial strain (substrate-induced strain) can
be used to boost performances?
Strain characterization
35.
Strain characterization
36.
Blanket wafer data
The substrate induced-strain (~1.4-GPa biaxial stress:
exx=0.77%) is well transferred in the stack.37.
Fin patterning data
EDX - Si
EDX - Ge
0 100 200 300 400 5000,0
0,4
0,8
1,2
De
f. (
%)
Distance (nm)
Measurement in sSi channels
Relaxation of sSi (free edges)
C1
C2
C3
0 100 200 300 400 5000,0
0,4
0,8
1,2
De
f. (
%)
Distance (nm)
Relaxation of SiGe (free edges)
Measurement in SiGe channels
S1
S2
+0.4
0.0
-0.4
(s)Si
Def. (ezz)
Fin width
Along the source-drain direction
38.
Si Source/drain data
exx
eyySi0.7Ge0.3
Si0.7Ge0.3
Si0.7Ge0.3
Si0.7Ge0.3Si Si
exx
Si Si
eyy
Si0.7Ge0.3
Si channel
Si channel
Inner spacer
Si0.7Ge0.3
Si channel
Si channel
Si Si
Inner spacer
In-plane deformation
Out-of-plane deformation
In-plane deformation
Out-of-plane deformationa b
Du
mm
y g
ate
The silicon channels as well as the source and drain are unstrained
A deformation close to 0% is observed
0 10 20 30 40 50 60 70 80-1,0
-0,5
0,0
0,5
1,0
1,5
De
form
atio
n (
%)
Channel
Top
channel
Bottom
channel
Source DrainChannel
In-plane (exx) PED deformation maps of stacked-wire transistor. Here,
inner spacer and Si source/drain are considered.
39.
Si Source/drain data
exx
eyySi0.7Ge0.3
Si0.7Ge0.3
Si0.7Ge0.3
Si0.7Ge0.3Si Si
exx
Si Si
eyy
Si0.7Ge0.3
Si channel
Si channel
Inner spacer
Si0.7Ge0.3
Si channel
Si channel
Si Si
Inner spacer
In-plane deformation
Out-of-plane deformation
In-plane deformation
Out-of-plane deformationa b
Du
mm
y g
ate
0 10 20 30 40 50 60 70 80-1,0
-0,5
0,0
0,5
1,0
1,5
De
form
atio
n (
%)
Channel
Top
channel
Bottom
channel
Relax. SiGe
Source DrainChannel
Full strain relaxation of sacrificial Si0.7Ge0.3 layer after the Fin recess
In-plane (exx) PED deformation maps of stacked-wire transistor. Here,
inner spacer and Si source/drain are considered.
40.
An initial strain (substrate-induced strain) is useless
SiGe:B Source/drain data
exx
eyySi0.7Ge0.3
Si0.7Ge0.3
Si0.7Ge0.3
Si0.7Ge0.3Si Si
exx
Si Si
eyy
Si0.7Ge0.3
Si channel
Si channel
Inner spacer
Si0.7Ge0.3
Si channel
Si channel
Si Si
Inner spacer
In-plane deformation
Out-of-plane deformation
In-plane deformation
Out-of-plane deformationa b
In-plane (exx) PED deformation maps of stacked-wire transistor. Here,
inner spacer and SiGe source/drain are considered.
Optimized engineering of process-induced stress
techniques such as SiGe S/Ds (for p-FET) can be
efficient in 3D stacked-NWs devices
0 10 20 30 40 50 60 70 80 90-1,0
-0,5
0,0
0,5
1,0
De
form
atio
n (
%)
Channel
channelsource drain
SiSiGe SiGe
top
bottom
41.
Outline
• Performance/Design consideration
• Device Fabrication
– Inner spacer
– SiGe S/D
• Strain Characterization– Precession Electron Diffraction
• Perspectives
• Summary and Conclusion
42.
Today u-dense nanowire in industry
(poly Si)
43.
Next step …
• To switch to crystalline nanowires?
• To mix 3D logic & 3D memories ?
• Both ?
44.
Feasibility of Mo(W)S2 synthesis ALD demonstrated
Screening of dedicated precursors, H2S free
450°C 800°C
Replace Si by 2D materials?
MoS3,3C4,7H12N
S.Cadot et al J. Vac. Sci. Technol. A, Nov/Dec 2017, 06150245.
Summary Fabrication of vertically stacked Nanosheet MOSFETs (RMG process)
are now demonstrated (inner spacers, SiGe:B S/D, 44/48 CPP)
Horizontal GAA Nanosheet also have the advantage of being
fabricated with minimal deviation from FinFET (FF) devices in
contrast to vertical NWs which require more disruptive technological
changes
Strain characterization at different steps of fabrication (PED)
Efficiency of process-induced strain (SiGe S/D) significant
compressive strain (~0.5 to 1%) in top and bottom Si p-channels
Design flexibility: Nanosheet transistors offers more freedom to
designers for the power-performance optimization thanks to a fine
tuning of the device width.
46.
Thank You for your attention
This work was partly funded by the French Public Authorities through the NANO 2017 program. It is also partially funded by the SUPERAID7 (grant N° 688101) project
47.