Achintya Priydarshi & Manju K. ChattopaadhyaySchool of Electronics

Devi Ahilya University , IndoreM.P. India

Performance Analysis of Encoder in Different Logic Techniques for High-Speed & Low-Power

Application

CONTENTS

INTRODUCTIONLITERATURE REVIEWEVOLUTION OF TECHNIQUE COMPARISON OF RESULTSCONCLUSIONFUTURE ENHANCEMENTREFERENCES

INTRODUCTION Standard CMOS logic is slower and takes larger area.Domino logic circuits are extensively used in high performance

digital implementation.Due to their superior speed characteristics. Domino logic circuits are extremely susceptible to noise and are

highly leaky. AVL (Adaptive Voltage Level) circuit technique and body bias

technique which will reduce leakage power as well as improve the noise immunity.

LITERATURE REVI

Domino LogicAVL circuit techniqueBody bias technique

PRE-CHARGE EVALUATION LOGIC

In dynamic CMOS logic a single clock can

be used to accomplish both the pre-charge and evaluation operations.

When clock is low, PMOS pre-charge

transistor is turn on, output becomes high.

When clock goes high, PMOS is turned off and the NMOS transistor is turned on, allow the output to be selectively discharged to GND depending on the logic inputs.

STATIC CMOS LOGIC

Low powerOnly leakage when not switchingHigh Noise ToleranceNo clock neededHigh fan-out load (lower speed) pFET and nFET loadsHigh noise generation

DOMINO LOGIC The problem with faulty discharge of pre-charged nodes in CMOS

dynamic logic circuits can be solved by placing an inverter in series with the output of each gate.

An elegant solution to the dynamic CMOS logic erroneous evaluation problem is to use NP Domino Logic as shown below.

ADAPTIVE VOLTAGE LEVEL CIRCUIT TECHNIQUE

Consists of a single p-MOS switch and m number of series connected n-MOS switches.

Reduces the drain-source voltage appearing across the load circuit.

BODY BIASING TECHNIQUE The voltage applied to the substrate affects the threshold voltage of a

MOSFET. The voltage difference between the source and the subs-trate, VBS

changes the threshold voltage.

DOMINO INVERTER STATIC INVERTER

BODY BIAS INVERTER AVL INVERTER

IMPLEMENTATION OF 4-INPUT NOR GATE

Static NORD

Domino NORa

AVL NOR

Body Bias NOR

IMPLEMENTATION OF 8×3 ENCODER

STATIC ENCODER DOMINO DECODER

BODY BIAS ENCODER AVL ENCODER

COMPARISION OF POWER CONSUMPTION

COMPARISION OF NMH & NML

CONCLUSION AVL circuit technique consume less dynamic power than the

others. AVL technique requires large number of transistors to

implement the encoder which increases the complexity of the circuit.

Body biasing increases the threshold voltage of the circuit both of these techniques help to improve the noise margin of the circuit. But it has highest dynamic and static power consumption.

In this paper, we observed that encoder based on AVL technique is better as compare to other because there is comparatively less power consumption and it has high noise margin.

FUTURE ENHANCEMENT We have designed a cell library for combinational

circuits, like Inverter, NOR gate and 8×3 Encoder.

In designing a system, we can replace cell components by appropriate technique based cell so that the noise margin of overall circuit is improved. In future we can also implement some techniques for sequential circuits.

REFERENCES

[1] R. H. Krambeck, C. M. Lee, H. S. Law, High-Speed Compact Circuits with CMOS, IEEE Journal of Solid State Circuits, pp.614-619, Vol. SC-17, No.3, June 1982.

[2] N. F. Goncalves, H. J. Deman, NORA: A Race Free Dynamic CMOS Technique for Pipelined Logic Structures‖, IEEE Journal of Solid State Circuits, pp.261-266, Vol.18, No.3, June 1983.

[3] Park, J. C., Mooney, Sleepy Stack Leakage Reduction Very Large Scale Integration (VLSI) Systems, IEEE Transactions, pp.1250-1263, vol.14, No.1, November 2006.

[4] S. Kang, Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, 3 rd ed, The McGraw-Hill Companies, New Delhi, 2005.

 

 

[5] Dhananjay, E. Upasani, Sandip, B. Shrote, Pallavi, S. Deshpande, Standby Leakage Reduction in Nanoscale CMOS VLSI Circuits, International journal of computer application, pp.1-4, Vol.7, No.5, September 2010.

[6] R. K. Brayton, R. L. Rudell, A. L. Sangiovanni-Vincentelli, A Multiple-Level Logic Optimization System‖, IEEE Trans. on Computer Aided Design, pp. 1062-1081, Vol.6, No.6, June 1987.

[7] P. Raikwal, M.Tech Thesis, School of Electronics, Devi Ahilya University, 2012.