Pentium Processor

• An improvement over the architecture found in the 80486 microprocessor

• Compatible with 8086, 80286, 80386, 80486

• Has all the features of 80486 plus some additional enhancements

Additional features

1. 64 bit data bus

• 8 bytes of data information can be transferred to and from memory in a single bus cycle

• Supports burst read and burst write back cycles

• Supports pipelining

2. Instruction cache

• 8 KB of dedicated instruction cache

• Two Integer execution units, one Floating point execution unit

• Dual instruction pipeline

• 256 lines between instruction cache and prefetch buffers; allows 32 bytes to be transferred from cache to buffer

3. Data cache

• 8 KB dedicate data cache gives data to execution units

• 32 byte lines

4. Two parallel integer execution units

• Allows the execution of two instructions to be executed simultaneously in a single processor clock

5. Floating point unit

• It includes • Faster internal operations • Local advanced programmable interrupt controller

• Speeds up upto 5 times for common operations including add, multiply and load, than 80486

6. Branch Prediction Logic

• To reduce the time required for a branch caused by internal delays

• When a branch instruction is encountered, microprocessor begins prefetch instruction at the branch address

7. Data Integrity and Error Detection

• Has significant error detection and data integrity capability

• Data parity checking is done on byte – byte basis

• Address parity checking and internal parity checking features are added

8. Dual Integer Processor

• Allows execution of two instructions per clock cycle

9. Functional redundancy check

• To provide maximum error detection of the processor and interface to the processor

• A second processor ‘checker’ is used to execute in lock step with the ‘master’ processor

• It checks the master’s output and compares the value with the internal computed values

• An error signal is generated in case of mismatch

10. Superscalar architecture

• Three execution units

• One execution unit executes floating point instructions

• The other two (U pipe and V pipe) execute integer instructions

• Parallel execution of several instructions – superscalar processor

Pentium Processor Architecture

Bus unit

• Gives physical interface between processor and external world using address, data and control bus

• 32 bit address bus and 64 bit data bus

• Supports pipelining

• Capable of burst reads and writes of 32 bytes to memory

Code cache

• 8KB memory, 32 bytes line size

• Keeps copy of most frequently used instructions which will be supplied to the processor’s execution pipelines

• Triple ported – allows simultaneous accesses from the prefetcher and to support cache unit

Data cache

• 8KB memory, 32 bytes line size

• Keeps copy of most frequently used data which will be supplied to the processor’s execution units (integer pipelines and floating point unit)

• Triple ported – allows simultaneous accesses from each of the pipelines and to support cache snoop

Prefetcher

• Burst bus cycle is used by the prefetcher to fill the cache

• Prefetching is sequential as long as there is a branch instruction

• It can also access two lines – to get the data which resides partially in two separate line within the cache

Prefetch buffers

• 4 prefetch buffers as two independent pairs

• When instructions are taken from the cache, they are placed in one of the pairs and the other pair remain idle

• The other pair come into the picture if a branch is predicted in a Branch Target Buffer (BTB)

• The predicted branch address is placed in the second pair of buffers

• It continue to be used till it gets another branch in BTB

• This time the predicted address comes in the first buffer pair and so on

Decoder unit

• Two stages: decode – 1 (D1) and decode -2 (D2)

• During D1 the opcode is decoded in both the pipeline to find whether the two instructions can be paired

• If pairing is possible, both the instructions will be sent to D2

Control unit

• Has two sub units • Microcode sequencer • Microcode control ROM

• Interprets the instruction and microcode given by decoder

• Controls the integer unit and floating point unit

ALU

• Performs arithmetic – logical operations

• An ALU in U pipeline can complete an operation prior to ALU in V pipeline but the reverse is not true

Address generators

• Two address generators

Paging unit

• Translates the linear address from the address generator to a physical address

• This unit is enabled by setting the PG bit of CR0

Floating point unit (FPU)

• Three internal units add, divide and multiply

• FPU can do simultaneous addition, multiplication and division

• FPU can accept up to two floating point operations per clock

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Pentium Pro Processor

• The Pentium Pro processor has 36 address lines – can address up to 64GB physical memory

• The Pentium Pro processor has an additional 256/512 KB L2 cache memory on chip

• On chip L2 cache speeds processing and reduces the number of components in a system

• The L2 cache is connected to BIU, which in turn provides access to the L1 cache

• BIU generates memory addresses and control signals and passes or fetches data or instructions either to L1 data cache or L1 instruction cache

• The L1 code cache provides the instructions to the instruction fetch and decode unit

• The Instruction Fetch and Decode Unit (IFDU), contains three separate instruction decoders that decode three instructions simultaneously

• It also include is Branch Prediction Logic

• It predicts if the branch will be taken or not for a conditional jump instruction

• Branch is predicted by looking ahead in code sequence to determine the next instruction in the flow of program

• The instruction are then put into the instruction pool

• The instruction pool is a memory accessible with its content

• The decoded instructions from this pool are dispatched to the execution unit by dispatch unit

• The decoded instructions are retrieved by the execution unit and executed

• The execute unit consists of three units namely two integer execution unit and one floating point unit – two integer and one floating instruction can be executed simultaneously

• Pentium Pro also has one jump execution unit (address generation unit)

• The instruction once executed is retired and the result is written into the destination location by the retire unit

• It is the last stage of the instruction execution

• This unit checks the instruction pool for the completed instruction and removes them from the instruction pool

• It is capable of removing up to three instructions per cycle

• The scheduling is performed by reservation station (RS) which can schedule up to five events for execution and process four simultaneously

Pentium Pro Internal Memory System

• 4 Gbytes memory system

• Access to an area between 4 GB to 64 GB is made possible by additional address lines A32 – A35

• 64 bit data bus is used to address memory organized in 8 banks

• Each bank is 1 byte wide and 8GB long if 32 bit addressing is enabled

• One byte data has a parity bit – internal parity generation and checking unit

• The additional memory is enabled with PAE (bit 5 of CR4) i.e. page address extension, and is accessible only when 2M paging is enabled

Special Pentium Pro Features

Control register 4 (CR4)

31 7 6 5 4 3 2 1 0

PGE MCE PAE PSE DE TDS PVI VME

VME Virtual module extension Enables support for the virtual mode in protected mode If VME = 0, virtual support is disabled

PVI Protected mode virtual interrupt Enables support for the virtual interrupt flag in protected mode

TDS Time Stamp disable Controls the RDTSC instruction

DE Debugging Extension Enables I/O breakpoint debugging when set

PSE Page size extension Enables 2 Mbyte memory pages when set in the pentium pro

PAE Page address extension Enables address lines A32 – A35

MCE Machine check Enables machine checking interrupt

PGE Page extension Controls new, larger 64G addressing mode whenever it is set along with PAE and PSE

Pentium MMX

MultiMedia eXtension

Special features over Pentium processor

• 57 extra instructions named MMX instruction set

• Multimedia operation is 10 - 20 times better over non MMX chip

• Several tasks in single instruction

• 16 KB Data and Code cache each

• Speed up to 266 MHz

Pentium MMX processor contains 5 different blocks as compared to the pentium processor

1. The split code and data cache are of 16 KB as against 8 KB in Pentium processor

2. A MMX technology unit with SIMD (Single Instruction Multiple Data) instruction required for multimedia operation, is connected along with floating point unit

3. The bus connected from the code cache to the prefetch queue is of 128 bits as against 256 bits in pentium processor

4. Includes DPL (Data Prediction Logic) that predicts further data required

5. Has an on chip APIC (Advanced Programmable Interrupt Controller)

Hyper-Threading Technology

• Two execution units into a single package

• The hyper threaded processor contains two execution units

• Each contain a complete set of the registers capable of running software independently or concurrently

• These two separate machine contexts share a common bus interface unit

• Each EU is capable of running a process – ‘thread’ independently

• Increases the execution speed of an application that is written using multiple threads

• The bus interface unit contains the level 2 and level 3 caches and the interface to the memory or I/O structure of the machine

• When either EU needs to access memory or I/O, it must share the bus interface unit

• Memory is accessed in burst mode, so bus interface

unit is found idle

• A second processor can use this idle time to access memory while the other processor is busy executing instructions – ‘Dual processor’ (core 2 Duo)

• Does the speed of the system double? – Yes and No

• Some threads can run independently of each other as long as they do not access the same area of memory

• If each thread accesses the same area of the memory actually runs slower with hyper-threaded technology

• This does not occur very often – the system performance is increased with hyper-threading

• Nearly the same performance as with a dual processor system

Core 2 Duo processor

• Two cores on a single chip and a shared cache L2

New Features

Dual core processing

• Two independent processor cores in one physical package

• Run at same frequency

• Share up to 6 MB of L2 cache as well as up to 1333 MHz Front Side Bus (FSB)

• Parallel computing

Wide dynamic execution

Each core can compute up to four full instructions simultaneously

Smart memory access

• Newly designed prediction mechanisms

• New prefetch algorithms, keeps pipelining full

Advanced smart cache

Shared L2 cache is dynamically allocated to each processor core based on workload

Advanced digital

Accelerate the execution of Streaming SIMD Extension (SSE) instructions to significantly improve the performance of video, audio, image processing, multimedia, engineering etc.

Virtualization technology

Allows one hardware platform to function as multiple ‘virtual’ platform

Trusted execution technology

• Protection against software based attack

• Protects the confidentiality and integrity of data solved or created on the system

Intel 64 architecture

Can access larger amount of memory

Execute disable bit

• Provides enhanced virus protection when deployed with a supported operation system

• Allows memory to be marked as executable or non-executable

Designed thermal solution for boxed processor

• 4 pin connector for fan speed control

• Minimizes the acoustic noise level generated from running the fan at higher speeds

Core 2 Duo architecture

• Instruction fetch and predecode unit fetches the instructions from shared L2 cache and stores them into instruction queue

• Instruction from the queue is decoded and are forwarded to allocation unit

• Allocation unit check the dependability and accordingly issues the instructions to the schedulers

• The allocation unit has renaming unit that renames the registers to avoid hazards

• The scheduler issues the instruction to the respective execution units e.g. load data unit, store data unit, integer ALU and FPU

• The execution unit accesses the L1 data cache for the required data and after execution of instruction inform the retirement unit

• Instruction may be executed out of order, but their retirement will be done in order