CAD ECE - UIC Engineeringdutt/courses/ece368/lect-notes/lect1.pdfCAD Based Logic Design Lectur e...
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ECE368:CADBasedLogicDesign
LectureNotes#1
Introduction:CombinationalLogicandItsDescriptionUsingHardwareDescriptionLanguages(HDLs)
SHANTANUDUTT
DepartmentofElectricalandComputerEngineeringUniversityofIllinois,Chicago
Phone:(312)355-1314;e-mail:[email protected]:http://www.ece.uic.edu/˜dutt
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ApplicationofLogicCircuits–TheBigPicture
Besides,computers,logiccircuitsfindthebulkoftheirapplicationastheembeddedsystemsorbrainsofanenormousvarietyofpruducts.Insuchsys-temstheyaregenerallyusedascontrollersofalarger(non-logic–eg.,analog,electro-mechanical)system
non-digital) systemLarger (possibly
Logic Circuit(Digital Circuit)
nkml
A/D SensorsD/A
Control
Actuators
n1
n2
m1
m2
Signals
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ApplicationofLogicCircuits�Computers:Thebrain,bodyandlimbsofcomputersystems—everything
initexceptperipherals
�EmbeddedSystems:Thebrainsthatcontrolthesystem(e.g.avionics,autoelectronics,VCRs,microwaves,etc.)
�DigitalSignalProcessing(DSP):E.g.indigitalcellularphones,digitalTV
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ApplicationofLogicCircuits(contd.)�LogicCircuitsareusedtorealizefunctionsofthetype:
IfinputconditionC1holdsthendooutputactionA1
elseifinputconditionC2holdsthendooutputactionA2...
�Orhaveloopingsintheseconstructs.E.g.,
RepeatIfinputconditionC1holdsthendooutputactionA1
elseifinputconditionC2holdsthendooutputactionA2...Untilcondition�C0�
�Inshort,anyfunctionthatcanbespecifiedbya“program”canbeim-plementedbyacombinationofcombinationalcircuits,sequentialcircuitsandmemory(besidesthememoryinherentinsequentialcircuits)
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�ConditionsCicanbeofthetype:
–Thetemp.70degreesF–Thetime12:30pm–ValueofvariablesA1A2�10
�ActionsAicanbeofthetype:
–Turnthefurnaceon–Tapetheprogramonchannel7–Turnonthelight
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TheRoleofLogic–AnIntroduction�Digitalsystemdesignisbasedontheprincupleoflogicandthemanipu-
lationoflogicsymbols
�Digitalsystemdesignisthusalsotermedlogicdesign
�BooleanLogic:Thereareonly2valuesassociatedwithastatementorcomputation—True(T)orFalse(F)
�Example:StatementA:Todayisaniceday�FStatementB:Thisisaclassofbrightstudents�T
�CompoundStatement:Formedofatomicorsimplestatementsthatarejoinedtogetherbythe3basicoperators:AND,OR,NOT.Itisalsocalledalogicexpression
�Example:AANDB�(Todayisaniceday)AND(Thisisaclassofbrightstudents)�F
�Similarly,AORB�T;NOT�B��F;AOR(NOT(B))�F
�SwitchingLogic:Tisrepresentedby1andFisrepresentedby0
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Introduction:TheRoleofLogic(contd.)�Defn.Alogicfunctionf�A1�A2�
���
�An�,whereA1�
���
�Anarelogicvari-ablesthatcantake1/0values,isonewhichhaseither1or0valuesasitsoutputdependingontheinputcombinationofits1/0values
�Fact:AnylogicfunctioncanberepresentedbyacombinationofAND,OR,NOToperatorsontheinputvariables
�Fact:AnylogicfunctioncanalsoberepresentedbyaTruthTable(TT)
�ATruthTableisatabularrepresentationofalogicfunction(oroperation)wheretheoutputvalue(1/0)isindicatedforeachinput1/0combination.ExamplesfortheAND,OR,NOTfunctions:
�DefnAlogiccircuitisacircuitthatrealizesalogicfunctionf�A1�
���
�An�
”electrically”.Itdoessobyelectricallyrepresenting1’sand0’sasvoltagelevels,andmanipulatingthemtoproduce1or0attheoutputasrequiredbyfunctionf.
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ABAANDBABAORBANOT(A)0000000101001110100101111111
�MoreExamples:Ageneric2-inputfunction
A1A2f�A1�A2�
000011101110
–Thereareatotalof22combinationsof2inputs(i/p)–sotheTThas4rows
–Eachoutput(o/p)ofarowcanhave2pos-siblevalues(1/0)–sothereare24�16pos-siblecombinationsofvaluesfora4-rowTT
–Eachofthese16combinationsisadistinctTT–thusthereare16different2-i/pfunc-tions
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�Ageneric3-i/pfunction:
A1A2A3f�A1�A2�A3�
00000011010101101000101111011110
–Thereare23�8inputcombinations–thus8rows
–Thusa3-i/pTTcanhave28�256possibleoutputcombinationsinits8rows–thus256different3-i/pfunc-tions
–Ingeneralann-i/pfunction/TThas2ninputcombinations
–Itthushas22noutputcombination,
oneforeachdistinctfunction–thusthereare22n
differentn-i/pfunctions
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ASimpleDesignProblem
Problem:Designalogiccircuitthatallowsalightbulbtobecontrolledbytogglinganyoneofthetwoprovidedswitchess1�s2.
+5v
+5v
LogicCircuit
S1
S2S2
S1
Bulb
SW
AC Power
Z
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ADesignProblem(Contd.)DesignSteps:
1.Encodetheinput(s)andoutput(s)ofthelogiccircuitaslogicvariablessothatCandAarelogicexpressions
InputEncoding:Switchs1ispushed�logicinputs1�1Switchs1isnotpushed�logicinputs1�0Similarlyforswitchs2andlogicinputvariables2
(Inthiscaseweareusingthesamenameforboththeinputsensorandthecorrespondingsingleinputvariable–thismaynotalwaysbethecase)Imp.Note:Theterms1�1canbemoresimplyrepresentedasthelogicexpressions1;theterms1�0canbemoresimplyrepresentedasNOT�s1�ors̄1
OutputEncoding:Turnthe(electro-mechanical)switchSWon�logicoutputZ�1Turnthe(electro-mechanical)switchSWoff�logicoutputZ�0
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2.GetTTsforeachoutputvariable(i.e.,foreachlogicfunctionrequired)afteranalyzingtherequirementandfromtheTTobtainitslogicexpres-sion
NOTE:ThisTT-basedapproachshouldreallyshouldbeandcanbedoneonlyforsmalldesignproblems(upto,say,6inputvariables).Forlargerproblems,oneneedstothinkinamoredivide-and-conquer/hierarchical,and/orhigh-leveland/oralgorithmicmanner.Willlaterseetheselatterapproachesforthedesignofarithmeticcircuits.
TheTTobtainedassumingthelightshouldbeOFFwhenbothswitchesare0(anotherTTwillbeobtainediftheassumptionisthattheLIGHTshouldbeONwhenbothswitchesare0;bothleadtocorrectdesignsintermsofthegivenspecification).
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s1s2Z000011101110
–EachrowinaTTcorrespondstoanANDtermorprod-ucttermormintermoftheinputvariables
–Intheproducttermani/pvariableXoccursasX̄ifitis0inthatrowotherwiseasX
–TheoutputcolumnistheORofalltheprod-uctterms(rows)forwhichitisa1–thusZ�
�s̄1ANDs2�OR�s1ANDs̄2�
–Morecompactly,Z�
�s̄1s2���s1s̄2�,productformre-placesANDandplus(+)formreplacesORThisiscalledacanonicalsum-of-product(SOP)expression.
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3.Minimizethelogicexpression(s)usingvariousmethodslikealgebraicmanipulation,K-Maps,Quine-McCluskeyandPetrick’salgorithm.TheaboveexpressionforZisalreadyinminimizedform.
4.Implementthelogicexpression(s)using“switches”or“gates”(orsomeothertechnologieslikePLA,multiplexers,ROMs–willdolater)
S1
S2
S1S2
NOT gate
AND gate
OR gate
S2 S1
S1S2
S2 S1S1S2 + Z=
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DescribingCombinationalCktsandDataPathsUsingProgramming-LanguageConstructs—Concepts
S1S2
NOT gate
AND gate
OR gate
X
Y
Sbar2
Sbar1S2 S1S1S2 + Z=
�Q.Howcanthiscombinationalcircuitbedescribedusingprogramminglanguagetypeconstructs?Ans.Threewaysrangingfromtheabstractlevelwhichhasnoimplemen-tationdescriptionstotheimplementationlevelthatspecifiestheintercon-nections(wiring)betweenmodules/gatesbutdoesnotexplicitlyrevealtheprocessingofthelogicsignalsortheflowofthecomputation:(1)Behavioral;(2)DataFlow;(3)Structural
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PurposeofHardwareDescriptionLanguage(HDL)�Q.Whatisthepurposeofdescribingadigitalcircuitorsysteminthis
manner?Ans.
–Easeofspecifyingthedesignoflargecircuits/systemsusingwellun-derstoodprogramminglanguageandalgorithmicconstructs.
Note:Didyouknowthatanyalgorithmthatcanbemappedtoapro-gram(insayC++)canalsobemappedtohardwarethatthendirectlyimplementsthealgorithm?Thisisbecauseaprogramisultimatelyexecutedbyahardware–acomputer,andadirectmappingofthealgo-rithmtohardwareexecutesthatalgorithmbymimickingthecomputerexecution(asabyproductofthemapping,fore.g.,idthereisanADDoperationtobeperformedthecomputerwillprocessitviaageneralpurposeADDinstructionwhilethespecialisedhardwarewillprocessitbysourcingtherelevantoperandstotheinputsofanadderviacon-trolsignalsfromacontroller).
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HardwareSynthesis–Example1
GenerationComputer Code
Unit (FSM)
ldc
lda
ldb CPU
Mux3_select
bc
a
ADDER
Mux
Mux MuxMux2_select Mux1_select
Hardware Synthesis
Execution in a C
PU
Control
Read Bus ARead Bus B
Mux
Register File
Write Bus
Conrtol signals
Conrtol signals
Programming language statement
a := b + c;
Load r5 bLoad r7 c
Store r2 a
(r2 <- r5 + r7)ADD r2 r5 r7
Reg_r/w
Reg_addr
Alu_oper_select
Mux_select
r2
32
ADDALU
r7
r5
32 32
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HardwareSynthesis–Example2
O/Ps of code block
I/Ps to code block
SynthesizedRecursively
Computer
a computerExecution in
1 0
1 0
ldb lda
Mux1_select
zero
ovflsign
Demux1_selectDemux
Block B forHardware
Mux
2’s compl
b a
Hardware Synthesis
Block BAdder
Block A forHardware
GenerationComputer Code
Programming language construct
end Block B of code;else beginend Block A of code;if (a <= b) then begin
assmb code
operations)
(Adder may bereused for other
Unit (FSM)Control
Conrtol signals
Conrtol signals
Block C
B:
Load r3 bLoad r2 a
BZ ABNEG A
SUB r2 r2 r3
assmb codeBlock A A:JMP C
assmb codeC:
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PurposeofHDL(contd.)–Simulatingandtestingdesignsforcorrectnessbeforeactualimplemen-
tation/fabrication.–Automaticsynthesisoflargedesignsspecifiedbehaviorallyoralgo-
rithmicallyusingCADtools:
�canalsoverifyeachtransformation(algorithm�circuit(netlist)�
chiplayout)usingverificationtools
�reduceshumanerror
�increasesdesignproductivity
�canleadtomoreinnovativedesignsasitfreesthedesignerfromwell-knownnitty-grittydetailsofcircuitdesign(e.g.,designoifafastadder)allowingthedesignertoexplorealternativede-signs/algorithmsatahigherlevel
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DescribingCombinationalCktsandDataPaths(Contd.)
S1S2
NOT gate
AND gate
OR gate
X
Y
Sbar2
Sbar1S2 S1S1S2 + Z=
�Firsttheentitydescriptionspecifyinginput/outputsignals:entityckt1isport(s1�s2:inbit;Z:outbit);–i/osignalsoftypebitcanonlytakeon‘0’and‘1’valuesendentityckt1;
(1)Behavioral:Justspecifytheo/pfunction’sconditionsforbeing1and0:architecturebehav1ofckt1isbeginsw-controller:processisbeginifs1�0ands2�1thenZ��1;elsifs1�1ands2�0thenZ��1;elseZ��0;
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endif;endprocesssw-controller;endarchitecturebehav1;
ORspecifyitsexpressiondirectlyifknown:architecturebehav2ofckt1isbeginZ��(not(s1)ands2)or(s1andnot(s2));endarchitecturebehav2
Whatismissingfromthisdescriptionwithrespecttoanactualcircuit?Ans.Delay;sothisattributeneedstobepresentinahardwaredescrip-tionlanguage(HDL).E.g.,Z��(not(s1)ands2)or(s1andnot(s2))after5ns;
Disadvantage:Havetocalculatethegatedelaysofanactualimplemen-tationtospecifythedelayinabehavioraldescriptionofanon-trivialSOP/POSexpression.Thisisnotthecasewithdataflowandstructuraldescriptions,wherethedelayoftheoverallfunctionisautomaticallycom-putedbythecompiler/simulatorwhenthedelaysoftheindividualatomicfunctionsormodules/gatesisspecified.
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S1S2
NOT gate
AND gate
OR gate
X
Y
Sbar2
Sbar1S2 S1S1S2 + Z=
(2)DataFlow:Asthenameimpliestheprocessingflowofthesignals(i.e.,data)isspecifiedatsomelevel(lowlevelconsistingofbasicBooleanoperationslikeAND,OR,NOT,NAND,NOR,etc.,oratahigherlevelwherethebasicoperationsarearithmeticoperationslike���
�
������,etc.).Fortheabovee.g.:architecturedataflowofckt1is...(signal,etc.declarations)beginsbar1��not�s1�;(orsbar1��not�s1�after1ns;)sbar2��not�s2�;(orsbar2��not�s2�after1ns;)x��s1andsbar2;(orx��s1andsbar2after2ns;)y��s2andsbar1;(ory��s2andsbar1after2ns;)Z��xory;(orZ��xoryafter2ns;)endarchitecturedataflow
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wheresbar1�sbar2�x�yareintermediatesignals.Noticehowtheprocess-ingofthefunctionZisdescribedindetailviaallintermediatesignals.
–Theabovestatementsarecalledconcurrentstatementsaretobeex-ecutedconcurrently(i.e.,simulatedconcurrency)byasimulatorandnotsequentiallyasinaregularprogramminglanguage.
–Concurrentstatementsrepresenthardwareperfectlysincethehardwareisalways“executing”eachstatementconcurrently!
–Astatementisexecutedonlywhenoneofthesignals,say,xonitslefthandside(LHS)changes—thisiscalledaneventonxandsuchasimulationofacircuitiscalledadiscreteeventsimulation.
–TherearealsosequentialstatementsinVHDLwhichareincludedinaprocessdefinitionasinthebehavioraldescriptionofthecircuitgivenearlier.
–Statementsinaprocessareexecutedinorderoftheirappearancese-quentiallyjustlikestatementsinaregularprogramminglanguage.
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Digression—DiscreteEventSimulation(DES)–w/oDelays–Aneventissaidtooccuronasignalwheneveritsvaluechanges.
–AlldiscussionofDES(w/andw/odelays)applyonlytoconcurrentstate-ments(henceforthreferredtoonlyas“statement”indisc.ofDES)
–Astatementissimulatedonlywhenaneventoccursonatleastoneofitsinputs.IftheoutputsignalXofthisstatementchangesafterevaluation,thenXisputinineventqueue.
–WhenXispickedfromtheeventqueue(inthenextroundorattherighttimeincaseofspecifieddelays),thenallstatementsormodulesforwhichXisaninputareevaluated.
–However,atthebeginningeachstatement(incaseofbehavioralordataflowdescriptions)andmodule(incaseofstructuraldescriptions)iseval-uatedoncetodeterminetheinitialvalueofeachsignalandvariable.
–Whentherearenodelaysspecifiedwithstatementsormodules,DESpro-ceedsinrounds.Inroundi�1evaluationtakesplaceofallstatementsandmoduleswhoseoneormoreinputsignalshavebeenputintheeventqueueinroundi.
–Also,thenewvaluesonsignalsthatchangeaftertheevaluationoftheirassignmentstatementsordrivingmodulesinroundi,are“displayed”in
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roundi�1
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DiscreteEventSimulation–E.g.w/oDelays
sbar1��not�s1�;sbar2��not�s2�;x��s1andsbar2;y��s2andsbar1;Z��xory;
�Start:s1�0�s2�0�sbar1�1�sbar2�1�x�0�y�0�Z�0
�Rnd1(I/Psignals2changes):s1�0�s2�1�sbar1�1�sbar2�1�x�
0�y�0�Z�0Evalsbar2��not�s2�;Thevalue‘0’isscheduledonsbar2.Evaly��s2andsbar1;Thevalue‘1’isscheduledony.
�Rnd2:s1�0�s2�1�sbar1�1�sbar2�0�x�0�y�1�Z�0Evalx��s1andsbar2;Nochangeinx,sonoeventscheduledonxEvalZ��xory;Thevalue‘1’isscheduledonZ.
�Rnd3:s1�0�s2�1�sbar1�1�sbar2�0�x�0�y�1�Z�1Noneweventsarescheduled.Simulationsuspendsuntilthevalueofsomesignal(generally,input)changes.
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DiscreteEventSimulation–WithDelays
–Thefirstthreedefinitionsandissues(aboutevent,whensimulationisperformedofstatementsandmodules,andtheinitialevaluations)alsoapplyinDESwithdelays.Inadditionwehavethefollowingconcepts.
–ThecurrentsimulationtimeisthecircuittimetillwhichtheDEShasperformedsimulationsofthevariousstatementsormodulesofthecircuit.
–Ifadelayof,say,10ns,isassociatedwithanoutputsignalXandwhenitscorespondingstatementisexecuteditsvaluechanges,thenXisputintheeventqueuewithatimetagof�t�10�ns,wheretisthecurrentsimulationtime.
–TheeventqueueiskeptsortedbyincreasingtimetagsandtheDESpickssignalstobedisplayedfromthebeginningoftheeventqueue.
–Statement/moduleevaluationtakesplaceatacertaintimetafterallsig-nalsscheduledfordisplayattimetaredisplayedandtheirnewvaluesas-serted.Onlythosestatements/modulesareevaluatedwhichhaveatleastoneinputfromthesedisplayedsignals.
–Thecurrentsimulationtimeisthetimetagofthestatementormodulepickedfromtheeventqueuetobeexecuted.
–Insteadofrounds,wenowhavetheconceptofsimulationtime.
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DiscreteEventSimulation–E.g.WithDelays
sbar1��not�s1�after1ns;sbar2��not�s2�after1ns;x��s1andsbar2after2ns;y��s2andsbar1after2ns;Z��xoryafter2ns;
S1
S2
Sbar1
Sbar2
x
y
Z
1ns2ns3ns4ns5ns6ns
Eval Sbar2 <= not(S2) @ t =1ns
Eval x <= S1 and Sbar2 @ t=2ns (no change in x)
Eval y <= S2 and Sbar1 @ t=1ns
Eval Z <= x or y @ t=3ns
event
event
event
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BacktoDescriptionofCombinationalCktsandDataPaths
(3)Structural:
–Specifytheinterconnectionofthemodules/gates.Themodules/gatesthemselvesneedtobedescribedasseparateentitiesineitherabehav-ioral,data-floworstructuralmannerandsoforth.
–Astructural(ormixed)descriptionalsoallowsustospecifythedesigninatop-downhierarchicalmanner.
–However,thealgorithm,dataflow,etc.oftheprocessingisnotclearlyevidentinsuchadescription.
–Suchadescriptionismainlyusedforsimulationandtestingtoverifythecorrectnessofacircuitleveldesign.
Fortheabovee.g.:
S1S2
NOT gate
AND gate
OR gate
X
Y
Sbar2
Sbar1S2 S1S1S2 + Z=
–Firstdeclaretheinput/outputportsorsignalsofeachmodule(enclosed
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intheentitydefinition)andthearchitectureofthemodule:
–entitynotgateisport(a:inbit;b:outbit);endentitynotgate;
–entityandgateisport(a�b:inbit;c:outbit);endentityandgate;
–entityorgateisport(a�b:inbit;c:outbit);endentityorgate;
–E.g.architecturedefinitionoforgate:architecturebehavofckt1isbeginc��borc;–orisaninbuiltoperatorofVHDLendarchitecturebehav;
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(a) Circuit(b) Module interconnection from VHDL struct descr
Z Sbar2
Sbar1
Y
X
OR gate
AND gate
NOT gate
S2S1
ac
b
andgate
ac
b
andgate
b anotgate
b anotgate
sbar1sbar2
s2
s1
y
x
Z ac
b
andgate
–Thenspecifytheinterconnectionsofthesemodulestorepresentthecircuit:architecturestructuralofckt1is
signalsbar1�sbar2�x�y:bit;–signals/variablesoftypebitcanonlytakeon‘0’and‘1’valuesbeginnot1:entitywork.notgate(behav)portmap(s1�sbar1);not2:entitywork.notgate(behav)portmap(s2�sbar2);and1:entitywork.andgate(behav)portmap(s1�sbar2�x);
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and2:entitywork.andgate(behav)portmap(s2�sbar1�y);or1:entitywork.orgate(behav)portmap(x�y�z);endarchitecturestructural;
�TheabovetypeofcomponentinstantiationisavailableonlyinVHDL-90andiscalleddirectinstantiation.ThiswillnotworkinVHDL-87.WillshowinstantiationmechanismlaterforVHDL-87.
�NotethatmultiplearchitecturedefinitionsarepossibleinVHDLforthesamecircuit/system.
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Switch-BasedLogicCircuits�ASwitchisa“mechanism”(mechanical,electrical,electro-mecahnical)
thatgivensomeexternalstimuluswillmakeorbreakanelectricalcon-nection
Broken Connection
A=0
Y X
A=1
Made ConnectionXY
NORMALLY OPEN (NOP) SWITCH:
Made Connection
A=0
XY
A=1
Broken ConnectionY X
NORMALLY CLOSED (NOC) SWITCH:
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ImplementingNOT,AND,ORfunctions:
AAB
+5v
B
Z=AB+5vZ=AB
Implementing Product Terms (Series Connections):
A
Z=A+B B
A
+5v Z=A+B B +5v
Implementing OR Terms (Parallel Connections):
A
+5vZ=A+5vZ=A
A
Implementing A:Implementing A:
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�ImplementingZ�
�s̄1s2���s1s̄2�:
S1S2
S1S2
S2 S1
S1S2
S1S2
+5vS1S2
S2 S1
S1S2
S2 S1
S1S2
Z
Z Network
Z Network
GND(0v)
+5vS1S2
S1S2
Z=S1S2+S1S2Z=S1S2+S1S2
Z=S1S2+S1S2
Thecorrectimplementationisontherightandiscalledacomplemen-taryswitchingnetwork.
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TransistorImplementationofSwitches
Broken Connection
A=0
Y X
A=1
Made ConnectionXY
NORMALLY OPEN (NOP) SWITCH:
Cur
rent
Flow
Conducts when A=1Open when A=0
Source
Drain
GateA
Made Connection
A=0
XY
A=1
Broken ConnectionY X
NORMALLY CLOSED (NOC) SWITCH:
Cur
rent
Flow
NMOS Transistor
PMOS Transistor
Source
Drain
Gate
Conducts when A=0Open when A=1
A
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ProblemwithLargeSwitchingNetworks�nMOStransistorsdonotconducta“good”1;pMOStransistorsdonot
conducta“good”0
�ThusinlongseriespathswithmanynMOStransistors,apoor1(thatcanbeinterpretedasa0)canappearattheoutput
�SimilarlylongseriespathswithmanypMOStransistors,apoor0(thatcanbeinterpretedasa1)canappearattheoutput
�Thusneedtouseblocksofsmallswitchingnetworkscalledgatestoim-plementlogiccircuits
�ExamplesoftypicalgatesareAND,OR,NOT,NAND,NOR,EXORandXNOR
NORXOR
ANDORNAND
XNOR
NOT
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TransistorImplementationofGates
�Duetotheaboveproblemsofgood1and0conductioninCMOStech-nology,NANDandNORgatesarepreferredbuildingblocksinsteadofANDandORgates
�IllustrationforpreferenceofNANDoverAND(NORoverORstemsfromasimilarreason):
GND
Vdd
AB
B
A
AB
This implementation willnot conduct good 1s and 0s
AND
BA
AB
AB
B
A
NAND
AB = A + BAB
AB
GND
Vdd Reversing positions of NMOS
obtain the inverse function NANDand PMOS sub-networks we
that conducts good 1s and 0s:
�TheNOPandNOCswitchescanalsobedescribedbehaviorallyinanHDL(more“values”besides‘1’and‘0’arenowneededforsignals,e.g.,“floating/high-impedance”isneeded–‘Z’inVHDLfortypestdlogic(standardlogic))
�Gatescanthenbedescribedstructurallyusingsuchswitchmodulesac-cordingtothedesignswehavediscussed(parallelandseriesnetworks)
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