©2002 Fairchild Semiconductor Corporation

www.fairchildsemi.com

Rev. 1.0.1

Features• Low Start up Current• Maximum Duty Clamp • UVLO With Hysteresis• Operating Frequency up to 500KHz

DescriptionThe UC3842/UC3843/UC3844/UC3845 are fixedfrequencycurrent-mode PWM controller. They are specially designed for Off-Line and DC to DC converter applications with minimum external components. These integrated circuits feature a trimmed oscillator for precise duty cycle control, a temperature compensated reference, high gain error amplifier, current sensing comparator and a high current totempole output for driving a Power MOSFET. The UC3842 and UC3844 have UVLO thresholds of 16V (on) and 10V (off). The UC3843 and UC3845 are 8.5V(on) and 7.9V (off). The UC3842 and UC3843 can operate within 100% duty cycle. The UC3844 and UC3845 can operate with 50% duty cycle.

8-DIP

14-SOP

1

1

8-SOP

1

Internal Block Diagram

UC3842/UC3843/UC3844/UC3845SMPS Controller

* NORMALLY 8DIP/8SOP PIN NO.* ( ) IS 14SOP PINNO.* TOGGLE FLIP FLOP USED ONLY IN UC3844, UC3845

UC3842/UC3843/UC3844/UC3845

2

Absolute Maximum Ratings

Note:1. Board Thickness 1.6mm, Board Dimension 76.2mm ×114.3mm, (Reference EIA / JSED51-3, 51-7)2. Do not exceeed PD and SOA (Safe Operation Area)

Power Dissipation Curve

Thermal Data

Pin Array

Parameter Symbol Value UnitSupply Voltage VCC 30 VOutput Current IO ±1 AAnalog Inputs (Pin 2.3) V(ANA) -0.3 to 6.3 VError Amp Output Sink Current ISINK (E.A) 10 mAPower Dissipation at TA≤25°C (8DIP) PD(Note1,2) 1200 mWPower Dissipation at TA≤25°C (8SOP) PD(Note1,2) 460 mWPower Dissipation at TA≤25°C (14SOP) PD(Note1,2) 680 mWStorage Temperature Range TSTG -65 ~ +150 °C Lead Temperature (Soldering, 10sec) TLEAD +300 °C

Characteristic Symbol 8-DIP 8-SOP 14-SOP UnitThermal Resistance Junction-ambient Rthj-amb(MAX) 100 265 180 °C/W

800

700

600

500

400

300

900

1000

1100

0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150

AMBIENT TEMPERATURE ()

POW

ER D

ISSI

PATI

ON

(mW

)

12008DIP

14SOP

8SOP

800

700

600

500

400

300

900

1000

1100

0 10 20 30 40 5030 40 50 60 70 8060 70 80 90 100 11090 100 110 120 130 140120 130 140 150

AMBIENT TEMPERATURE ()

POW

ER D

ISSI

PATI

ON

(mW

)

12008DIP

14SOP

8SOP

VCC

GND

PWR GND

COMP 1

N/C 2

VFB

N/C

3

4

VREF

N/C

PWR VC

14

13

12

11

CURRENT SENSE 5

N/C

RT/CT

6

7

OUTPUT10

9

8

COMP 1

VFB 2

CURRENT SENSE

RT/CT

3

4

VREF

VCC

OUTPUT

GND

8

7

6

5

8DIP,8SOP 14SOP

VCC

GND

PWR GND

COMP 1

N/C 2

VFB

N/C

3

4

VREF

N/C

PWR VC

14

13

12

11

CURRENT SENSE 5

N/C

RT/CT

6

7

OUTPUT10

9

8

VCC

GND

PWR GND

COMP 1

N/C 2

VFB

N/C

3

4

VREF

N/C

PWR VC

14

13

12

11

CURRENT SENSE 5

N/C

RT/CT

6

7

OUTPUT10

9

8

COMP 1

VFB 2

CURRENT SENSE

RT/CT

3

4

VREF

VCC

OUTPUT

GND

8

7

6

5

COMP 1

VFB 2

CURRENT SENSE

RT/CT

3

4

VREF

VCC

OUTPUT

GND

8

7

6

5

8DIP,8SOP 14SOP

UC3842/UC3843/UC3844/UC3845

3

Electrical Characteristics(VCC=15V, RT=10kΩ, CT=3.3nF, TA= 0°C to +70°C, unless otherwise specified)

Parameter Symbol Conditions Min. Typ. Max. UnitREFERENCE SECTIONReference Output Voltage VREF TJ = 25°C, IREF = 1mA 4.90 5.00 5.10 VLine Regulation ∆VREF 12V ≤ VCC ≤ 25V - 6 20 mVLoad Regulation ∆VREF 1mA ≤ IREF ≤ 20mA - 6 25 mVShort Circuit Output Current ISC TA = 25°C - -100 -180 mAOSCILLATOR SECTIONOscillation Frequency f TJ = 25°C 47 52 57 kHzFrequency Change with Voltage ∆f/∆VCC 12V ≤ VCC ≤ 25V - 0.05 1 %

Oscillator Amplitude VOSC - - 1.6 - VP-PERROR AMPLIFIER SECTIONInput Bias Current IBIAS - - -0.1 -2 µAInput Voltage VI(E>A) Vpin1 = 2.5V 2.42 2.50 2.58 VOpen Loop Voltage Gain GVO 2V ≤ VO ≤ 4V (Note3) 65 90 - dBPower Supply Rejection Ratio PSRR 12V ≤ VCC ≤ 25V (Note3) 60 70 - dBOutput Sink Current ISINK Vpin2 = 2.7V, Vpin1 = 1.1V 2 7 - mAOutput Source Current ISOURCE Vpin2 = 2.3V, Vpin1 = 5V -0.6 -1.0 - mAHigh Output Voltage VOH Vpin2 = 2.3V, RL = 15kΩ to GND 5 6 - VLow Output Voltage VOL Vpin2 = 2.7V, RL = 15kΩ to Pin 8 - 0.8 1.1 VCURRENT SENSE SECTIONGain GV (Note 1 & 2) 2.85 3 3.15 V/VMaximum Input Signal VI(MAX) Vpin1 = 5V(Note 1) 0.9 1 1.1 VPower Supply Rejection Ratio PSRR 12V ≤ VCC ≤ 25V (Note 1,3) - 70 - dBInput Bias Current IBIAS - - -3 -10 µAOUTPUT SECTION

Low Output Voltage VOL

ISINK = 20mA - 0.08 0.4 V ISINK = 200mA - 1.4 2.2 V

High Output Voltage VOH

ISOURCE = 20mA 13 13.5 - V ISOURCE = 200mA 12 13.0 - V

Rise Time tR TJ = 25°C, CL= 1nF (Note 3) - 45 150 nsFall Time tF TJ = 25°C, CL= 1nF (Note 3) - 35 150 nsUNDER-VOLTAGE LOCKOUT SECTION

Start Threshold VTH(ST)

UC3842/UC3844 14.5 16.0 17.5 VUC3843/UC3845 7.8 8.4 9.0 V

Min. Operating Voltage(After Turn On) VOPR(MIN)

UC3842/UC3844 8.5 10.0 11.5 V UC3843/UC3844 7.0 7.6 8.2 V

UC3842/UC3843/UC3844/UC3845

4

Electrical Characteristics (Continued)

(VCC=15V, RT=10kΩ, CT=3.3nF, TA= 0°C to +70°C, unless otherwise specified)

Adjust VCC above the start threshould before setting at 15V

Note:1. Parameter measured at trip point of latch 2. Gain defined as:

3. These parameters, although guaranteed, are not 100 tested in production.

Figure 1. Open Loop Test Circuit

High peak currents associated with capacitive loads necessitate careful grounding techniques Timing and bypass capacitors should be connected close to pin 5 in a single point ground. The transistor and 5kΩ potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3.

Parameter Symbol Conditions Min. Typ. Max. UnitPWM SECTION

Max. Duty Cycle D(Max) UC3842/UC3843 95 97 100 %D(Max) UC3844/UC3845 47 48 50 %

Min. Duty Cycle D(MIN) - - - 0 %TOTAL STANDBY CURRENTStart-Up Current IST - - 0.45 1 mAOperating Supply Current ICC(OPR) Vpin3=Vpin2=ON - 14 17 mAZener Voltage VZ ICC = 25mA 30 38 - V

A∆Vpin1∆Vpin3------------------=

UC3842

,0 ≤ Vpin3 ≤ 0.8V

UC3842/UC3843/UC3844/UC3845

5

Figure 2. Under Voltage Lockout

During Under-Voltage Lock-Out, the output driver is biased to a high impedance state. Pin 6 should be shunted to ground with a bleeder resistor to prevent activating the power switch with output leakage current.

Figure 3. Error Amp Configuration

Figure 4. Current Sense Circuit

Peak current (IS) is determined by the formula:

A small RC filter may be required to suppress switch transients.

UC3842/44 UC3843/45

IS MAX( ) 1.0VRS

------------=

UC3842/UC3843/UC3844/UC3845

6

Figure 5. Oscillator Waveforms and Maximum Duty Cycle

Oscillator timing capacitor, CT, is charged by VREF through RT and discharged by an internal current source. During the discharge time, the internal clock signal blanks the output to the low state. Selection of RT and CT therefore determines bothoscillator frequency and maximum duty cycle. Charge and discharge times are determined by the formulas:tc = 0.55 RT CT

Frequency, then, is: f=(tc + td)-1

Figure 8. Shutdown Techniques

Figure 6. Oscillator Dead Time & Frequency Figure 7. Timing Resistance vs Frequency

tD RTCTIn0.0063RT 2.7–0.0063RT 4–

---------------------------------------- =

ForRT 5KΩ f 1.8RTCT---------------=,>

(Deadtime vs CT RT > 5kΩ)

UC3842/UC3843/UC3844/UC3845

7

Shutdown of the UC3842 can be accomplished by two methods; either raise pin 3 above 1V or pull pin 1 below a voltage two diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pins 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR which will be reset by cycling VCC below the lower UVLO threshold. At this point the reference turns off, allowing the SCR to reset.

Figure 9. Slope Compensation

A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for converters requiring duty cycles over 50%. Note that capacitor, CT, forms a filter with R2 to suppress the leading edge switch spikes.

Temperature (°C)Figure 10. Temperature Drift (Vref)

Temperature (°C)Figure 11. Temperature Drift (Ist)

Temperature (°C)Figure 12. Temperature Drift (Icc)

UC3842/UC3843

3

PARAMETER TEST CONDITIONSUC1842/3/4/5UC2842/3/4/5

UC3842/3/4/5 UNITS

MIN TYP MAX MIN TYP MAX

Reference Section

Output Voltage TJ = 25°C, I O = 1mA 4.95 5.00 5.05 4.90 5.00 5.10 V

Line Regulation 12 ≤ VIN ≤ 25V 6 20 6 20 mV

Load Regulation 1 ≤ I0 ≤ 20mA 6 25 6 25 mV

Temp. Stability (Note 2) (Note 7) 0.2 0.4 0.2 0.4 mV/°C

Total Output Variation Line, Load, Temp. (Note 2) 4.9 5.1 4.82 5.18 V

Output Noise Voltage 10Hz ≤ f ≤ 10kHz, TJ = 25°C (Note2) 50 50 µV

Long Term Stability TA = 125°C, 1000Hrs. (Note 2) 5 25 5 25 mV

Output Short Circuit -30 -100 -180 -30 -100 -180 mA

Oscillator Section

Initial Accuracy TJ = 25°C (Note 6) 47 52 57 47 52 57 kHz

Voltage Stability 12 ≤ VCC ≤ 25V 0.2 1 0.2 1 %

Temp. Stability TMIN ≤ TA ≤ TMAX (Note 2) 5 5 %

Amplitude VPIN 4 peak to peak (Note 2) 1.7 1.7 V

Error Amp Section

Input Voltage VPIN 1 = 2.5V 2.45 2.50 2.55 2.42 2.50 2.58 V

Input Bias Current -0.3 -1 -0.3 -2 µA

AVOL 2 ≤ VO ≤ 4V 65 90 65 90 dB

Unity Gain Bandwidth (Note 2) TJ = 25°C 0.7 1 0.7 1 MHz

PSRR 12 ≤ VCC ≤ 25V 60 70 60 70 dB

Output Sink Current VPIN 2 = 2.7V, VPIN 1 = 1.1V 2 6 2 6 mA

Output Source Current VPIN 2 = 2.3V, VPIN 1 = 5V -0.5 -0.8 -0.5 -0.8 mA

VOUT High VPIN 2 = 2.3V, RL = 15k to ground 5 6 5 6 V

VOUT Low VPIN 2 = 2.7V, RL = 15k to Pin 8 0.7 1.1 0.7 1.1 V

Current Sense Section

Gain (Notes 3 and 4) 2.85 3 3.15 2.85 3 3.15 V/V

Maximum Input Signal VPIN 1 = 5V (Note 3) 0.9 1 1.1 0.9 1 1.1 V

PSRR 12 ≤ VCC ≤ 25V (Note 3) (Note 2) 70 70 dB

Input Bias Current -2 -10 -2 -10 µA

Delay to Output VPIN 3 = 0 to 2V (Note 2) 150 300 150 300 ns

UC1842/3/4/5UC2842/3/4/5UC3842/3/4/5

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for -55°C ≤ TA ≤ 125°C for theUC184X; -40°C ≤ TA ≤ 85°C for the UC284X; 0 °C ≤ TA ≤ 70°C for the 384X; V CC = 15V(Note 5); RT = 10k; CT = 3.3nF, TA=TJ.

Note 2: These parameters, although guaranteed, are not 100% tested in production.Note 3: Parameter measured at trip point of latch with VPIN 2 = 0.Note 4: Gain defined as

AVPIN

VPINVPIN V= ≤ ≤∆

∆1

30 3 0 8, .

Note 5: Adjust VCC above the start threshold before setting at 15V.Note 6: Output frequency equals oscillator frequency for the UC1842 and UC1843.

Output frequency is one half oscillator frequency for the UC1844 and UC1845.Note 7: Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation:

Temp StabilityV max VREF min

TJ max TJ min

REF= −−

( ) ( )

( ) ( )

VREF (max) and VREF (min) are the maximum and minimum reference voltages measured over the appropriatetemperature range. Note that the extremes in voltage do not necessarily occur at the extremes in temperature.

4

PARAMETER TEST CONDITIONUC1842/3/4/5UC2842/3/4/5

UC3842/3/4/5 UNITS

MIN TYP MAX MIN TYP MAX

Output Section

Output Low Level ISINK = 20mA 0.1 0.4 0.1 0.4 V

ISINK = 200mA 1.5 2.2 1.5 2.2 V

Output High Level ISOURCE = 20mA 13 13.5 13 13.5 V

ISOURCE = 200mA 12 13.5 12 13.5 V

Rise Time TJ = 25°C, C L = 1nF (Note 2) 50 150 50 150 ns

Fall Time TJ = 25°C, C L = 1nF (Note 2) 50 150 50 150 ns

Under-voltage Lockout Section

Start Threshold X842/4 15 16 17 14.5 16 17.5 V

X843/5 7.8 8.4 9.0 7.8 8.4 9.0 V

Min. Operating VoltageAfter Turn On

X842/4 9 10 11 8.5 10 11.5 V

X843/5 7.0 7.6 8.2 7.0 7.6 8.2 V

PWM Section

Maximum Duty Cycle X842/3 95 97 100 95 97 100 %

X844/5 46 48 50 47 48 50 %

Minimum Duty Cycle 0 0 %

Total Standby Current

Start-Up Current 0.5 1 0.5 1 mA

Operating Supply Current VPIN 2 = VPIN 3 = 0V 11 17 11 17 mA

VCC Zener Voltage ICC = 25mA 30 34 30 34 VNote 2: These parameters, although guaranteed, are not 100% tested in production.Note 3: Parameter measured at trip point of latch with VPIN 2 = 0

.

Note 4: Gain defined as: AVPIN

VPINVPIN V= ≤ ≤∆

∆1

30 3 0 8; . .

Note 5: Adjust VCC above the start threshold before setting at 15V.Note 6: Output frequency equals oscillator frequency for the UC1842 and UC1843.

Output frequency is one half oscillator frequency for the UC1844 and UC1845.

UC1842/3/4/5UC2842/3/4/5UC3842/3/4/5

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for −55°C ≤ TA ≤ 125°C for theUC184X; −40°C ≤ TA ≤ 85°C for the UC284X; 0 °C ≤ TA ≤ 70°C for the 384X; V CC =15V (Note 5); RT = 10k; CT = 3.3nF, TA=TJ.

ERROR AMP CONFIGURATION

Error Amp can Source or Sink up to 0.5mA

5

UC1842/3/4/5UC2842/3/4/5UC3842/3/4/5

UNDER-VOLTAGE LOCKOUT

CURRENT SENSE CIRCUIT

OSCILLATOR SECTION

During under-voltage lock-out, the output driver isbiased to sink minor amounts of current. Pin 6 shouldbe shunted to ground with a bleeder resistor to prevent

activating the power switch with extraneous leakagecurrents.

A small RC filter may be required to suppress switch transients.

Peak Current (IS) is Determined By The Formula

ISMAX ′ 1.0V

RS

6

High peak currents associated with capacitive loads ne-cessitate careful grounding techniques. Timing and by-pass capacitors should be connected close to pin 5 in a

single point ground. The transistor and 5k potentiometerare used to sample the oscillator waveform and applyan adjustable ramp to pin 3.

Shutdown of the UC1842 can be accomplished by twomethods; either raise pin 3 above 1V or pull pin 1 belowa voltage two diode drops above ground. Either methodcauses the output of the PWM comparator to be high(refer to block diagram). The PWM latch is reset domi-nant so that the output will remain low until the next

clock cycle after the shutdown condition at pin 1 and/or3 is removed. In one example, an externally latchedshutdown may be accomplished by adding an SCRwhich will be reset by cycling VCC below the lowerUVLO threshold. At this point the reference turns off, al-lowing the SCR to reset.

UC1842/3/4/5UC2842/3/4/5

OUTPUT SATURATION CHARACTERISTICSERROR AMPLIFIER OPEN-LOOPFREQUENCY RESPONSE

OPEN-LOOP LABORATORY FIXTURE

SHUT DOWN TECHNIQUES

APPLICATION NOTE

UC3842 PROVIDES LOW-COST CURRENT-MODE CONTROL

The fundamental challenge of power supply designis to simultaneously realize two conflicting objecti-ves : good electrical performance and low cost. TheUC3842 is an integrated pulse width modulator(PWM) designed with both these objectives in mind.This IC provides designers an inexpensive control-ler with which they can obtain all the performanceadvantages of current-mode operation. In addition,the UC3842 is optimized for efficient power sequen-cing of off-line converters and for driving increasin-gly popular POWERMOS.

This application note gives a functional descriptionof the UC3842 and suggests how to incorporate theIC into practical power supplies. A review of current-mode control and its benefits is included and me-

thods of avoiding common pitfalls discussed. The fi-nal section presents designs of two power suppliesutilizing UC3842 control.

CURRENT-MODE CONTROLFigure 1 shows the two-loop current-mode controlsystem in a typical buck regulator application. Aclock signal initiates power pulses at a fixed frequen-cy. The termination of each pulse occurs when ananalog of the inductor current reaches a thresholdestablished by the error signal. In this way the errorsignal actually controls peak inductor current. Thiscontrasts with conventional schemes in which theerror signal directly controls pulse width without re-gard to inductor current.

AN246/1188

Figure 1 : Two-loop Current-mode Control System.

1/16

Several performance advantages result from theuse of current-mode control. First, an input voltagefeed-forward characteristic is achieved ; i.e., thecontrol circuit instantaneously corrects for input volt-age variations without using up any of the error am-plifier’s dynamic range. Therefore, line regulation isexcellent and the error amplifier can be dedicated tocorrecting for load variations exclusively.

For converters in which inductor current is conti-nuous, controlling peak current is nearly equivalentto controlling average current. Therefore, whensuch converters employ current-mode control, theinductor can be treated as an error-voltage-control-led-current-source for the purposes of small-signalanalysis. This is illustrated by figure 2. The two-polecontrol-to-output frequency response of these con-verters is reduced to a single pole (filter capacitor inparallel with load) response.

One result is that the error amplifier compensationcan be designed to yield a stable closed-loop con-verter response with greater gain-bandwidth thanwould be possible with pulse-width control, givingthe supply improved small-signal dynamic responseto changing loads. A second result is that the erroramplifier compensation circuit becomes simpler andbetter behaved, as illustrated in figure 3. CapacitorCi and resistor Riz in figure 3a add a low frequencyzero which cancels one of the two control-to-outputpoles of non-current-mode converters. For large-si-

gnal load changes, in which converter response islimited by inductor slew rate, the error amplifier willsaturate while the inductor is catching up with theload. During this time, Ci will charge to an abnormallevel. When the inductor current reaches its requiredlevel, the voltage on Ci causes a corresponding errorin supply output vol-tage. The recovery time is Riz Ci,which may be milleseconds. However, the compen-sation network of figure 3b can be used where cur-rent-mode control has eliminated the inductor pole.Large-signal dynamic response is then greatly im-proved due to the absence of Ci.

Figure 3 : Required Error Amplifier Compensation for Continuous Inductor Current Designs using (a) Duty-cycle Control and (b) Current-mode Control.

Figure 2 : Inductor Looks Like a Current Source toSmall Signals.

(a)

(b)

APPLICATION NOTE

2/16

Figure 4 : UC3842 Block Diagram.

Current limiting is simplified with current-mode con-trol. Pulse-by-pulse limiting is, of course, inherent inthe control scheme. Furthermore, an upper limit onthe peak current can be established by simply clam-ping the error voltage. Accurate current limiting al-lows optimization of magnetic and powersemiconductor elements while ensuring reliablesupply operation.

Finally, current-mode controlled power stages canbe operated in parallel with equal current sharing.This opens the possibility of a modular approach topower supply design.

FUNCTIONAL DESCRIPTION

A block diagram of the UC3842 appears in figure 4.This IC will operate from a low impedance DC sour-ce of 10 V to 30 V. Operation between 10 V and 16V requires a start-up bootstrap to a voltage greaterthan 16 V in order to overcome the undervoltage loc-kout. VCC is internally clamped to 34 V for operationfrom higher voltage current-limited sources(ICC ≤ 30 mA).

UNDER-VOLTAGE LOCKOUT (UVLO)

This circuit insures that VCC is adequate to make theUC3842 fully operational before enabling the output

stage. Figure 5a shows that the UVLO turn-on andturn-off thresholds are fixed internally at 16 V and 10V respectively. The 6 V hysteresis prevents VCCoscillations during power sequencing. Figure 5bshows supply current requirements. Start-up currentis less than 1 mA for efficient bootstrapping from therectified input of an off-line converter, as illustratedby figure 6. During normal circuit operation, VCC isdeveloped from auxiliary winding WAUX with D1 andCIN. At start-up, however, CIN must be charged to 16V through RIN. With a start-up current of 1 mA, RIN

can be as large as 100 kΩ and still charge CIN whenVAC = 90 V RMS (low line). Power dissipation in RINwould then be less than 350 mW even under highline (VAC = 130 V RMS) conditions.

During UVLO, the UC3842 output driver is biased toa high impedance state. However, leakage currents(up to 10 µA), if not shunted to ground, could pullhigh the gate of a POWERMOS. A 100 kΩ shunt, asshowing in figure 6, will hold the gate voltage below1V.

APPLICATION NOTE

3/16

Figure 5 : (a) Under-voltage Lockout and (b) Supply Current Requirements.

(a) (b)

Figure 6 : Providing Power to the UC3842.

OSCILLATOR

The UC3842 oscillator is programmed as shown infigure 7a. Oscillator timing capacitor CT is chargedfrom VREF (5 V) through RT, and discharged by aninternal current source. Charge and discharge timesare given by :

tc ≈ 0.55 RT CT

0.0063 RT – 2.7td ≈ RT CT ln ( )

0.0063 RT – 4.01

frequency, then, is : f =tc + td

For RT > 5 kΩ, td is small compared to tc, and :1 1.8

f ≈ ≈0.55 RT CT RT CT

APPLICATION NOTE

4/16

During the discharge time, the internal clock signalblanks the output to the low state. Therefore, td limitsmaximum duty cycle (DMAX) to :

tc tdDMAX = = 1 –

tc + td τ

where τ = 1/f = switching period.

The timing capacitor discharge current is not tightlycontrolled, so td may vary somewhat over tempera-

ture and from unit to unit. Therefore, when very pre-cise duty cycle limiting is required, the circuit of fig-ure 7b is recommended.

One or more UC3842 oscillators can be synchroni-zed to an external clock as shown in figure 8. Noiseimmunity is enhanced if the free-running oscillatorfrequency (f = 1/(tc + td)) is programmed to be~ 20 % less than the clock frequency.

Figure 7 : (a) Oscillator Timing Connections and (b) Circuit for Limiting Duty Cycle.

(a) (b) tcDMAX =(tH + tL)

tH = 0.693 (RA + RB) CtL = 0.693 RB C

Figure 8 : Synchronization to an External Clock.

ERROR AMPLIFIER

The error amplifier (E/A) configuration is shown infigure 9. The non-inverting input is not brought out

to a pin, but is internally biased to 2.5 V ± 2 %. TheE/A output is available at pin 1 for external compen-sation, allowing the user to control the converter’sclosed-loop frequency response.Figure 10a shows an E/A compensation circuit sui-table for stabilizing any current-mode controlled to-pology except for flyback and boost convertersoperating with continuous inductor current. The fe-edback components add a pole to the loop transferfunction at fp = 1/2 πRf Cf. Rf and Cf are chosen sothat this pole cancels the zero of the output filter ca-pacitor ESR in the power circuit. Ri and Rf fix the low-frequency gain. They are chosen to provide as muchgain as possible while still allowing the pole formedby the output filter capacitor and load to roll off theloop gain to unity (0dB) at f ≈ fswitching/4. This techni-que insures converter stability while providing gooddynamic response.Continuous-inductor-current boost and flyback con-verters each have a right-half-plane zero in theirtransfer function. An additional compensation poleis needed to roll off loop gain at a frequency less thanthat of the RHP zero. Rp and Cp in the circuit of figure10b provide this pole.

APPLICATION NOTE

5/16

The E/A output will source 0.5 mA and sink 2 mA. Alower limit for Rf is given by :

VE/A OUT(max) – 2.5 V 6 V – 2.5 VRf (MIN) ≈ = = 7 kΩ

0.5 mA 0.5 mA

E/A input bias current (2 µA max) flows through Ri,resulting in a DC error in output voltage (Vo) givenby :

∆ Vo(max) = (2 µA) Ri

It is therefore desirable to keep the value of Ri as lowas possible.

Figure 11 shows the open-loop frequency responseof the UC3842 E/A. The gain represent an upper li-mit on the gain of the compensated E/A. Phase lagincreases rapidly as frequency exceeds 1 MHz dueto second-order poles at ∼ 10 MHz and above.

Figure 9 : UC3842 Error Amplifier.

Figure 10 : (a) Error Amplifier Compensation Addi-tion Pole and (b) Needed for Continuous Inductor-current Boost ad Flyback.

(a)

(b)

Figure 11 : Error Amplifier Open-loop FrequencyResponse.

APPLICATION NOTE

6/16

CURRENT SENSING AND LIMITING

The UC3842 current sense input is configured asshown in figure 12. Current-to-voltage conversion isdone externally with ground-referenced resistor RS.Under normal operation the peak voltage across RSis controlled by the E/A according to the following re-lation :

VC – 1.4 VVRS (pk) =

3

where : VC = control voltage = E/A output voltage.

RS can be connected to the power circuit directly orthrough a current transformer, as figure 13 illustra-tes. While a direct connection is simpler, a transfor-mer can reduce power dissipation in RS, reduceerrors caused by the base current, and provide levelshifting to eliminate the restraint of ground-refer-ence sensing. The relation between VC and peakcurrent in the power stage is given by :

VRS(pk) Ni(pk) = N ( ) = (VC – 1.4)

RS 3 RS

where : N = current sense transformer turns ratio.= 1 when transformer not used.

For purposes of small-signal analysis, the control-to-sensed-current gain is :i(pk) N

=VC 3 RS

When sensing current in series with the power tran-sistor, as shown in figure 13, current waveform willoften have a large spike at its leading edge. This isdue to rectifier recovery and/or interwinding capaci-tance in the power transformer. If unattenuated, thistransient can prematurely terminate the output pul-se. As shown, a simple RC filter is usually adequateto suppress this spike. The RC time constant shouldbe approximately equal to the current spike duration(usually a few hundred nanoseconds).

The inverting input to the UC3842 current-sensecomparator is internally clamped to 1 V (figure 12).Current limiting occurs if the voltage at pin 3 reachesthis threshold value, i.e. the current limit is definedby :

N . 1 ViMAX =

RS

Figure 12 : Current Sensing.

APPLICATION NOTE

7/16

Figure 14 : Output Cross-conduction.Figure 13 : Transformer-coupled Current Sensing.

TOTEM-POLE OUTPUT

The UC3842 has a single totem-pole output. Theoutput transistors can be operated to ± 1 A peak cur-rent and ± 200 mA average current. The peak cur-rent is self-limiting, so no series current-limitingresistor is needed when driving a power MOS gate.

Cross-conduction between the output transistors isminimal, as figure 14 shows. The average added po-wer due to cross-conduction with Vi = 30 V is only80 mW at 200 kHz.

Figures 15-17 show suggested circuits for drivingPOWERMOS and bipolar transistors with theUC3842 output. The simple circuit of figure 15 canbe used when the control IC is not electrically isola-ted from the power MOS. Series resistor R1 providesdamping for a parasitic tank circuit formed by the po-wer MOS input capacitance and any series wiring in-ductance. Resistor R2 shunts output leakagecurrents (10 µA maximum) to ground when the un-der-voltage lockout is active. Figure 16 shows anisolated power MOS drive circuit which is appropria-te when the drive signal must be levelshifted or tran-smitted across an isolation boundary. Bipolartransistors can be driven effectively with the circuitof figure 17. Resistors R1 and R2 fix the on-statebase current. Capacitor C1 provides a negative basecurrent pulse to remove stored charge at turn-off.

PWM LATCH

This flip-flop, shown in figure 4, ensures that only asingle pulse appears at the UC3842 output in anyone oscillator period. Excessive power transistordissipation and potential saturation of magnetic ele-ments are thereby averted.

SHUTDOWN TECHNIQUES

Shutdown of the UC3842 can be accomplished bytwo methods ; either raise pin 3 above 1 V or pull pin1 below 1 V. Either method causes the output of thePWM comparator to be high (refer to block diagram,figure 4). The PWM latch is reset dominant so thatthe output will remain low until the first clock pulsefollowing removal of the shutdown signal at pin 1 orpin 3. As shown in figure 18, an externally latchedshutdown can be accomplished by adding an SCRwhich will be reset by cycling VCC below the lowerunder-voltage lockout threshold (10 V). At this pointall internal bias is removed, allowing the SCR to re-set.

Figure 15 : Direct POWERMOS Drive.

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Figure 16 : Isolated POWERMOS Drive.

Figure 17 : Bipolar Drive with Negative Turn-off Bias.

AVOIDING COMMON PITFALLS

Current-mode controlled converters can exhibit per-formance peculiarities under certain operating con-ditions. This section explains these situations andhow to correct them when using the UC3842.

SLOPE COMPENSATION PREVENTS INSTABILI-TIES

It is well documented that current-mode controlledconverters can exhibit subharmonic oscillationswhen operated at duty cycles greater than 50 %.

Fortunately, a simple technique (usually requiringonly a single resistor to implement) exists which cor-rects this problem and at the same time improvesconverter performance in other respects. This "slo-pe compensation" technique is described in detail inReference 6. It should be noted that "duty cycle"here refers to output pulse width divided by oscillatorperiod, even in push-pull designs where the tran-sformer period is twice that of the oscillator. There-fore, push-pull circuits will almost always requireslope compensation to prevent subharmonic oscil-lation.

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Figure 18 : Shutdown Achieved by(a) Pulling Pin 3 High(b) Pulling Pin 1 Low.

(a)

(b)

Figure 19 illustrates the slope compensation techni-que. In figure 19a the uncompensated control volt-age and current sense waveforms are shown as areference. Current is often sensed in series with theswitching transistor for buck-derived topologies. Inthis case, the current sense signal does not track thedecaying inductor current when the transistor is off,so dashed lines indicate this inductor current. Thenegative inductor current slope is fixed by the valuesof output voltage (Vo) and inductance (L) :diL VL – VF – Vo – (VF + Vo)

= = =dt L L L

where : VF = forward voltage drop across the free-wheeling diode. The actual slope (m2) of the dashedlines in figure 19a is given by :

RS diL – RS (VF + Vo)m2 = . =

N dt NL

where : RS and N are defined as the "Current Sen-sing" section of this paper.

In figure 19b, a sawtooth voltage with slope m hasbeen added to the control signal. The sawtooth issynchronized with the PWM clock, and practice is

most easily derived from the control chip oscillatoras shown in figure 20a. The sawtooth slope in figure19b is m = m2/2. This particular slope value is signi-ficant in that it yields "perfect" current-mode control ;i.e. with m2/2 the average inductor current followsthe control signal so that, in the small-signal analy-sis, the inductor acts as a controlled current source.All current-mode controlled converters having con-tinuous inductor current therefore benefit from thisamount of slope compensation, whether or not theyoperate above 50 % duty.

More slope is needed to prevent subharmonic oscil-lations at high duty cycles. With slope m = m2, suchoscillations will not occur if the error amplifier gain(AV(E/A)) at half the switching frequency (fs/2) is keptbelow a threshold value (reference 6) :

π 2 COAV (E/A) <

4 τm = m2f = fs/2

where : Co = sum of filter and load capacitanceτ = 1/fs

Slope compensation can also improve the noise im-munity of a current-mode controlled supply. Whenthe inductor ripple current is small compared to theaverage current (as in figure 19a), a small amountof noise on the current sense or control signals cancause a large pulse-width jitter. The magnitude ofthis jitter varies inversely with the difference in slopeof the two signals. By adding slope as in figure 19b,the jitter is reduced. In noisy environments it is so-metimes necessary to add slope m > m2 in order tocorrect this problem. However, as m increases be-yond m = m2/2, the circuit becomes less perfectlycurrent controlled. A complex trade-off is then requi-red ; for very noisy circuits the optimum amount ofslope compensation is best found empirically.

Once the required slope is determined, the value ofRSLOPE in figure 20a can be calculated :

∆VRAMP 0.7 V RSLOPE 1.4 RSLOPE3 m = . AV(E/A) = ( ) = ( )

∆ tRAMP τ/2 ZF | fs τ ZF | fs

3 m τRSLOPE = (ZF | fs) = 2.1 . m . τ . ZF | fs

1.4

where : ZF| fs is the E/A feedback impedance at theswitching frequency.

For m = mL : ∆τRAMP

Rs (VF + VO)RSLOPE = 1.7 τ ( ) ZF | fs

NL

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Figure 19 : Slope Compensation Waveforms :(a) No Comp.(b) Comp. Added to Control Voltage.(c) Comp. Added to Current Sense.

Note that in order for the error amplifier to accuratelyreplicate the ramp, ZF must be constant over the fre-quency range fs to at least 3 fs.

In order to eliminate this last constraint, an alterna-tive method of slope compensation is shown in figu-res 19c and 20b. Here the artificial slope is addedto the current sense waveform rather than subtrac-ted from the control signal. The magnitude of the ad-ded slope still relates to the downslope of inductorcurrent as described above. The requirement forRSLOPE is now :

∆VRAMP Rf 0.7 Rfm = ( ) = ( )

∆tRAMP Rf + RSLOPE τ/2 Rf + RSLOPE

1.4 Rf 1.4RSLOPE = – Rf = Rf ( – 1)

mτ mτ

For m = m2 :1.4 NL

RSLOPE = Rf ( – 1)RS (VF + VO) τ

RSLOPE loads the UC3842 RT/CT terminal so as tocause a decrease in oscillator frequency. If RSLO-

PE >> RT then the frequency can be corrected by de-creasing RT slightly. However, with RSLOPE ≤ 5 RTthe linearity of the ramp degrades noticeably, cau-sing over-compensation of the supply at low duty cy-cles. This can be avoided by driving RSLOPE with anemitter-follower as shown in figure 21.

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Figure 20 : Slope Compensation Added (a) to Control Signal or (b) to Current Sense Waveform.

(a)

(b)

Figure 21 : Emitter-follower Minimizes Load atRT/CT Terminal.

NOISE

As mentioned earlier, noise on the current sense orcontrol signals can cause significant pulse-width jit-ter, particularly with continuous-inductor-current de-signs. While slope compensation helps alleviate thisproblem, a better solution is to minimize the amountof noise. In general, noise immunity improves as im-pedance decrease at critical points in a circuit.

One such point for a switching supply is the groundline. Small wiring inductances between variousground points on a PC board can support common-mode noise with sufficient amplitude to interfere withcorrect operation of the modulating IC. A copperground plane and separate return lines for high-cur-rent paths greatly reduce common-mode noise.

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Note that the UC3842 has a single ground pin. Highsink currents in the output therefore cannot be retur-ned separately.

Ceramic bypass capacitors (0.1 µF) from VI andVREF to ground will provide low-impedance paths forhigh frequency transients at those points. The inputto the error amplifier, however, is a high-impedancepoint which cannot be bypassed without affectingthe dynamic response of the power supply. There-fore, care should be taken to lay out the board insuch a way that the feedback path is far removedfrom noise generating components such as thepower transistor(s).

Figure 22a illustrates another common noise-indu-ced problem. When the power transistor turns off, anoise spike is coupled to the oscillator RT/CT termi-nal. At high duty cycles the voltage at RT/CT is ap-proaching its threshold level (∼ 2.7 V, established by

the internal oscillator circuit) when this spike occurs.A spike of sufficient amplitude will prematurely tripthe oscillator as shown by the dashed lines. In orderto minimize the noise spike, choose CT as large aspossible, remembering that deadtime increaseswith CT. It is recommended that CT never be lessthan ∼ 1000 pF. Often the noise which causes thisproblem is caused by the output (pin 6) being pulledbelow ground at turn-off by external parasitics. Thisis particularly true when driving POWERMOS. A dio-de clamp from ground to pin 6 will prevent such out-put noise from feeding to the oscillator. If thesemeasures fail to correct the problem, the oscillatorfrequency can always be stabilized with an externalclock. Using the circuit of figure 8 results in an RT/CTwaveform like that of figure 22b. Here the oscillatoris much more immune to noise because the rampvoltage never closely approaches the internal thre-shold.

Figure 22 : (a) Noise on Pin 4 Can Cause Oscillator to Pre-trigger.(b) With External Sync. Noise Does not Approach threshold Level.

MAXIMUM OPERATING FREQUENCY

Since output deadtime varies directly with CT, the re-straint on minimum CT (1000 pF) mentioned aboveresults in a minimum deadtime varies for theUC3842. This minimum deadtime varies with RTand therefore with frequency, as shown in figure 23.Above 100 kHz, the deadtime significantly reducesthe maximum duty cycle obtainable at the UC3842output (also show in figure 23). Circuits not requiringlarge duty cycles, such as the forward converter andflyback topologies, could operate as high as 500kHz. Operation at higher frequencies is not recom-

mended because the deadtime become less pre-dictable.

The speed of the UC3842 current sense sectionposes an additional constraint on maximum operat-ing frequency. A maximum current sense delay of400 ns represents 10 % of the switching period at250 kHz and 20 % at 500 kHz. Magnetic compo-nents must not saturate as the current continues torise during this delay period, and power semicon-ductors must be chosen to handle the resulting peakcurrents. In short, above ∼ 250 kHz, may of the ad-vantages of higher-frequency operation are lost.

(a) (b)

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Figure 23 : Deadtime and Maximum Obtainable Duty-cycle vs. Frequency with Minimum RecommendedCT.

CIRCUIT EXAMPLES

1. OFF-LINE FLYBACKFigure 24 shows a 25 W multiple-output off-line fly-back regulator controlled with the UC3842. This re-gulator is low in cost because it uses only twomagnetic elements, a primary-side voltage sensingtechnique, and an inexpensive control circuit. Spe-cifications are listed below.

SPECIFICATIONS :

Line Isolation : 3750 V

Switching Frequency : 40 kHz

Efficiency @ full load : 70 %

Input Voltage 95 VAC to 130 VAC(50Hz/60Hz)

Output Voltage : A. + 5 V, 5 % : 1 A to 4 A loadRipple voltage : 50 mVP-P Max.

B. + 12 V, 3 % : 0.1 A to 0.3 AloadRipple voltage : 100 mVP-P Max

C. – 12 V, 3 % 0.1 A to 0.3 A loadRipple voltage : 100 mVP-P Max

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