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Resource Catalog 2010

PCI Express®

Solutions

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Welcome to the 2010PCI Express® Solutions

Resource Catalog

Since it’s introduction in 2004 by Intel, IBM, Dell and HP, adoption of the Peripheral Component Interconnect Express®

(PCIe) protocol standard has moved along at a healthy pace, and work continues to allow systems engineers to design the transfer of ever-increasing amounts of data.

PCI Express® 3.0 was expected to be released by this year however the release date will be pushed out to 2010 next year due to additional time and effort needed to testify and ensure its backward compatibility capability with existing PCI-Express based products.

New application areas and new challenges to be addressed with PCIe are the subject of our exclusive article, “PCI Express®

Continues to Push Into New Application Areas,” in which we delve into some key application areas such as wireless, networking and medical from the perspective of key vendors with PCIe solutions. Their insights may surprise you.

With new features and performance possible, it can be a challenge to keep your options straight. Thankfully, you are looking at a valuable resource of data sheets and detailed ads that can help you in deciding which technology path to take. Take your time to peruse these pages -- we hope you will find some information directly useful in your next project.

We welcome your feedback, thoughts and comments at: [email protected]

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2 PCI Express® Solutions Resource Catalog 2010

Contents

PCI Express Continues to Push Into New Application Areas

by Ann Steffora Mutschler .......................................................................................................................................................3

PCI Express – The Quest for More Speed

by Scott Knowlton, Synopsys Inc. ............................................................................................................................................5

PCI Express Roadmap Is More Than Speed Bumps

by Craig Szydlowski..................................................................................................................................................................7

Products and Services

Chip-to-Chip

ICs

Integrated Device Technology, Inc. (IDT)IDT PCI Express® Bridges ..............................................10

IDT® PCI Express® Switching Solutions ........................11

Xilinx, Inc.Xilinx Solutions for PCI Express.....................................12

Protocol Analysis Tools

LeCroy CorporationLeCroy’s PCI Express® Protocol Analysisand Test Tools ................................................................14

Board-to-Board

Boards / Hardware

AMTELCO XDSThe Best Choice for PCI Express! ..................................15

Connect TechPCI Express Solutions ....................................................16

Dynamic EngineeringPCIeBPMCX1 - PCIe [Express] PMCAdapter/Carrier 1, 4 & 16 Lane .....................................17

InterphaseiSPAN® 56MC2 10 GE OCTEON™ Packet Processor.....18

MoxaPCI Express Serial Boards..............................................19

SpectracomTime Code Processor .....................................................20

FPGA Boards

Innovative IntegrationX3 Family PCI Express Cards cPCI, PCI or XMC.............21

X5 Family PCI Express cPCI, PCI, or XMC......................22

IP and Libraries

Innovative IntegrationWireless IP Cores for Software Digital Radio Applications...................................................................23

Protocol Analysis Tools

JDSUBus Doctor™ Protocol Analyzer forPCI Express® V. 2.0.......................................................24


by Ann Steffora Mutschler

Industry Forecast

PCI Express Continues to Push Into New Application Areas

Since it’s introduction in 2004 by Intel, IBM, Dell and HP, adoption

of the Peripheral Component Interconnect Express (PCIe) protocol

standard has moved along at a healthy pace, with the PCI SIG

industry group now working on revision 3.0, which achieves twice

the effective data throughput rate of the current PCIe 2.0 standard

through a combination of increased data bit rate (5 GT/s moving to

8 GT/s) and the elimination of 8b/10b data encoding, which previ-

ously added an overhead of 20 percent to all data transfers.

For your reference, the following table summarizes PCIe 3.0

datarates.

This faster data rate is allowing application of the protocol in new

ways with the wireless market a prime example. Here, a surplus

of new radio frequency (RF) technologies have emerged creating

opportunities for solving old problems in new ways and requiring

techniques such as flexible high-resolution waveform generation,

digitization and analysis subsystems capable of manipulating RF

signals in conjunction with down-conversion and tuning multiple

“regions of interest,” according to Jim Henderson, president of

Simi Valley, CA-based Innovative Integration (www.innovative-

dsp.com). Subsequent, real-time, multi-channel demodulation of

these regions using a variety of schemes is necessary and many

times, the equipment must be portable and operate under harsh

environmental conditions. This creates challenges in packaging,

power consumption and management.

To address this, existing products use arrays of dedicated digital

signal processors (DSPs) working in tandem with an RF digitizer

to provide the computational bandwidth needed to implement

down-conversion and demodulation functions, he explained.

And while it is effective, this approach is complicated and expen-

sive since multi-processor programming requires sophisticated

process management and load balancing while avoiding race

conditions and data bottlenecks.

Further, there are modular devices coming to market that leverage

the industry-standard, commercial-off-the-shelf (COTS) COM-

EXPRESS PC architecture and development tools in conjunction

with PCI Express-based XMC mezzanine modules to create cost-

effective, customizable RF processing block solutions, Henderson

said. Use of advanced PCI Express PMC modules allows high-

performance FPGA-based computational engines to be used that

can be dynamically loaded with customized firmware to address

changing RF processing requirements and markets.

From the test perspective, LeCroy Corporation (www.lecroy.com)

has a line of protocol analyzers that helps engineering teams

understand, monitor and document PCI Express traffic between

root complexes and endpoint devices in a number of ways. LeCroy

product marketing manager John Wiedemeyer has observed the

biggest area for growth currently is in graphics cards with high

speed I/O such as 10Gbps Ethernet, SATA and others.

He noted that while development of PCIe 3.0 is still in the

works, the current revision is often more than enough for many

customers. “As the industry moves away from the PCI standard,

vendors are scrambling to support PCIe, which many times, is

actually overkill for the application,” he said.

Still, since new microprocessors support PCIe, so must the

system. A bridge chip can be used at first to support a new revi-

sion, eventually, the entire system must be upgraded, which

also gives the benefit of a performance boost.

LeCroy serves many markets for embedded applications from

slot machines and airplanes to HPC servers all of which leverage

PCIe, Wiedemeyer said. For these customers, one challenge to

overcome can be utilizing all the performance that the pro-

tocol promises, with a big problem for some users being card

performance. “The PCIe protocol is sufficiently sophisticated

for customers to implement but they may not be getting all the

performance they could,” he offered.

PCI Express Nomenclature for Rev. 3.0

Gen # Raw Datarate Effective Real Throughput

Gen 1 2.5 Gigabits per second

2 Gigabits per second

Gen 2 5 Gigabits per second


Gen 3 8 Gigabits per second



In response to this and recognizing the market need to take apart

the protocol, LeCroy brought its Gen 2 protocol analyzer to market

in 2003, and has very recently introduced its Summit™ T3-16 PCI

Express protocol analyzer to support the PCIe® 3.0 specification

that captures, decodes and analyzes PCI Express bus traffic at

data rates up to 8 GT/s per lane on bus widths up to 16 lanes.

Changes in Server Market Impacting PCIeAlex Goldhammer, strategic marketing manager for PCI Express

at Xilinx Inc. (www.xilinx.com) said changes in the server

market are driving much of what’s happening for PCIe.

One example of this is Cisco entering into the datacenter

market, mostly through the acquisitions of Nuova in April 2008

and Tidal Software, Inc. in April 2009, along with the introduc-

tion of the Nexus 5000 series which contains 8 blades, each of

which is 2-socket server.

“I have a feeling this has a lot to do with what is driving PCI

Express,” Goldhammer said. “In terms of Cisco, the first step

for them was collapsing the network on the storage and LAN.

There is now a single Ethernet network with transport of Fiber

Channel over Ethernet and traditional LAN data.”

“In terms of PCI Express in enterprise equipment, everything

else has been virtualized, the only thing left to virtualize is the

I/O. That’s the next big trend,” he continued.

Intel, for example, has helped extend virtualization technology

by adding Intel Virtualization Technology for Directed I/O (VT-d)

in the latest Nehalem Processors and Tylersburg chipsets. What

this technology effectively does is hardware accelerate the address

translation that used to be done in the virtual machines (VM). This

enables near full-speed I/O for the virtual machines.

Another reaction in the market is the acquisition of Sun Micro-

systems by Oracle. “For a company like Oracle, they haven’t really

had to directly build hardware for their database software. The

Oracle acquisition of Sun appears to be an effort to make sure

Oracle has continuity in their hardware for their customers. Sun

has also opened up their operating system, OpenSolaris, which

will better enable migration to different server hardware such as

the x86 architecture in the mainstream,” Goldhammer noted.

“In the I/O space, Xilinx plays a big role in hardware accelera-

tion. ASSPs are very good for single function. However having

a programmable endpoint allows our customers to do different

kinds of hardware acceleration directly in the PCIe end-point.

In the context of the networking space, you can do packet pro-

cessing, encryption, compression or run various protocols in

that endpoint or even upgrade that endpoint to support new

and emerging applications,” he asserted.

A general trend – albeit a surprising one – is that Intel is giving

companies like Freescale and AMCC a bigger run for their money,

Goldhammer noted. “In the past, there was a much broader set of

processors and now Intel is moving into vertical markets where

they didn’t play before. The cost per performance of Intel is very

attractive in the low/mid end where it is becoming increasingly

challenging for companies like Freescale and AMCC to compete.

With Intel’s multiple core processors it is making it increasingly

easy to offload co-processing to one of these Intel processing cores.

AMCC and Freescale are going to have to move increasingly in to

the high-end to provide high-bandwidth specialized functionality.

Further, in terms of vertical market spaces, the medical market

is also quite dynamic, Goldhammer said. Xilinx plays a big role in

Medical Imaging where two-socket servers are used in conjunction

with specialized PCI Express add-in cards with Xilinx FPGAs.

“It’s a very specialized kind of processing that lends itself well to

something like a Xilinx device. It is a classic case of a customer

using off-the-shelf hardware that has a good cost point and

their putting time and resources into their value-add FPGA to

perform specialized functionality that lends itself well to the

FPGA,” he added.

In a similar fashion, there is a lot of work going on in the video

market, Goldhammer said. “With many different devices on

which to view the same content, content providers have chal-

lenge serving that content. With video being targeted on devices

ranging from iPhones to 1080p HD TVs video processing to

perform specialized functions such as image correction, image

sizing, and security, all lend themselves to FPGA technology.

Goldhammer views the biggest challenge in designing for

PCI Express as dealing with serial technology. Xilinx’s latest

Spartan-6 device contains PCI Express in an integrated block

and also includes transceivers – which is a serial technology.

“What that means is that for a large portion of our customer

base this will be the first time working with serial technology.

With Spartan-6 and PCI Express a where many customers do

not have the expertise on how to build a board with high-speed

serial, how to simulate signal integrity, or how to route the sig-

nals off of the chip, and so forth.”

To account for this, Xilinx developed what it has named the

Targeted Design Platform to provide a framework for customers

to develop around specific applications and technologies, and to

quickly develop with serial technology such as PCI Express.

Ann Steffora Mutschler is Editor of Extension Media’s

EECatalog Resource Catalogs, and is also a Contrib-

uting Editor to Chip Design Magazine’s System-Level

Design and Low-Power Design Communities. Her

previous experience includes a long stint as a Senior

Editor at Reed Business Information for publications

including EDN, Electronic News and Electronic Business. She has

moderated a number of panels in Silicon Valley and has written for

publications worldwide.


by Scott Knowlton, Synopsys Inc.

Industry ForecastPCI Express – The Quest for More Speed

Launched in 2002, the first generation of PCI Express (1.0)

supported 2.5GT/s and transitioned from the existing

parallel data architectures to a serial data technology to

provide a roadmap for continued performance improve-

ments. A number of goals drove the initial development

of the PCI Express specification, including consolidating

the PCI, PCI-X and AGP interfaces; increasing perfor-

mance; overcoming timing and layout issues with PCI; and

improving quality of service (QoS). For the most part, PCI

Express achieved all of these goals and quickly replaced

the AGP and PCI-X inter-

faces in designs. While

PCI has endured a bit

longer, it is only a matter

of time before PCI Express

replaces it as well due to

the inexorable demand for

more speed.

Although the first gen-

eration of PCI Express

supported 2.5GT/s, there

were immediate requests

for additional bandwidth

as products in the enter-

prise computing segment

required performance

beyond what PCI Express 1.0 provided. To meet this

demand, the PCI Express 2.0 specification, which sup-

ported 5.0GT/s (Gen2), was rolled out to designers in

2005 and 2006. Yet again, there were almost immediate

requests by the enterprise computing markets for addi-

tional functionality and, of course, more performance.

The new functionality of the PCI Express specification

included a number of engineering change notices (ECNs)

to improve system-level issues targeting performance,

the software model, the communication model and power

management. In addition to these ECNs, Single-Root I/O

Virtualization (SR-IOV) and Multi-Root I/O Virtualization

(MR-IOV) technologies were built on top of PCI Express

to allow the sharing of I/Os in enterprise computing sys-

tems. I/O virtualization in enterprise computing systems

is migrating from a predominantly software implementa-

tion to incorporate more virtualization functionality into

hardware, improving performance and reducing the costs

in these systems. The PCI Express 3.0 specification (Gen3)

first emerged in 2008 providing further performance

improvements, including support for 8.0 GT/s, with prod-

ucts expected to ship in 2010.

As the PCI Express standard continues to evolve, it will

be interesting to look at the markets it serves and the

effects the updates will have on SoC designs. Industry

reports and market sur-

veys have separated the

markets into traditional

segments, such as PC,

storage, networking,

consumer, automotive

and aerospace. Although

segmenting the markets

this way can be useful,

a simpler way to view

the market is to catego-

rize them based on the

PCI Express features

used. When doing so,

the market divides into

the following segments:

the PC industry (a well

known market limited to chipsets and graphics card pro-

viders), connectivity and enterprise computing.

The connectivity segment contains products that provide

expandability into systems and consists of replacements

for existing PCI and PCI-X interfaces used in PC add-in

cards, basic networking chips (i.e., 10M/100M/1G Eth-

ernet), 1394, embedded systems, multifunction printers,

wireless hubs, etc. This segment uses limited features of

PCI Express and is under constant pricing pressure since

many of the end products target the consumer market. In

this segment, PCI Express designs are generally single-

lane (x1) PCI Express endpoints running at 2.5GT/s.

The enterprise computing segment is made up of products

used in data centers, such as blades, networking, and

“As PCI Express continues to evolve, it is

interesting to note that the PCI Express

markets are still essentially defined by

the original markets served by AGP, PCI

and PCI-X (i.e. the PC industry/graphics,

connectivity and enterprise computing).”


storage devices and servers. These types of products crave

additional bandwidth and are the ones pushing the per-

formance requirements of PCI Express. This segment uses

PCI Express to build endpoints (EP), root complex (RC) and

dual mode (EP/RC) devices, which are usually eight (x8) or

sixteen (x16) lanes and currently support PCI Express 2.0

using 5.0GT/s. Many of the companies in this segment are

already moving to the PCI-SIG SR-IOV technology in their

next designs, and demand increased bandwidth beyond

the PCI Express 2.0 standard.

The industry is currently working on the PCI Express

3.0 standard and looking to achieve another doubling of

bandwidth. Instead of doubling the speed from 5.0GT/s to

10GT/s, PCI Express 3.0 will use 8.0GT/s, which simplifies

the design of the PHY by enabling the use of linear equal-

ization techniques instead of the more complex decision

feedback equalization (DFE). The lower speed also allows

designers to continue to use less expensive, standard FR4

board materials. The other 20 percent improvement comes

through changes to the protocol, including changes to the

composition of the packets and the removal of 8b/10b

encoding. The PCI Express 3.0 interface will, of course, be

backwards compatible to PCI Express 1.0 and 2.0, so the

digital controller will have to support the old definitions

and be able to switch in these new protocol changes when

up shifting to the faster speeds.

As PCI Express continues to evolve, it is interesting to

note that the PCI Express markets are still essentially

defined by the original markets served by AGP, PCI and

PCI-X (i.e. the PC industry/graphics, connectivity and

enterprise computing). Even though the needs for each

of these groups are different, they all have come together

under the PCI Express specification and driven it to wide

adoption. With the connectivity market being fully served

by single-lane, PCI Express 1.0 and the enterprise com-

puting market migrating from PCI Express 2.0 (5.0 GT/s)

to PCI Express 3.0 (8.0 GT/s), it leads one to wonder what

the lifespan is for PCI Express 2.0? Will PCI Express 2.0

be quickly replaced by PCI Express 3.0, or is it possible

that PCI Express 2.0 will develop into a smaller connec-

tivity market for high-end adapters? With the doubling

of performance of PCI Express 3.0 over PCI Express 2.0,

it is expected that designers will quickly incorporate this

latest version to address the high bandwidth needs of their

next-generation enterprise computing products targeted

for 2010.

Incorporating the PCI Express interface into the latest

designs will pose some challenges for product developers

in terms of managing the latest errata, ECNs, I/O virtu-

alization technologies and 3.0 features. Furthermore,

ensuring that the interface is completely validated, com-

pliant and interoperable with other PCI Express devices

will be critical to product success.

Scott Knowlton joined Synopsys in1997, and is

currently a Sr. Product Marketing Manager in

the IP group. Knowlton is responsible for Synop-

sys’ market-leading PCI Express, PCI-X and PCI

IP product families, and was previously respon-

sible for the AMBA and coreTools product lines.

Prior to Synopsys, Knowlton worked in simulation, synthesis

and mixed signal solutions at Cadence Design Systems after

having held several en¬gineering and project management po-

sitions in ASIC development at Encore Com¬puter, Intrinsix

and Raytheon. Scott earned his Bachelor of Science degree in

Electrical Engineering from the University of Michigan.


by Craig Szydlowski

Industry Forecast

PCI Express Roadmap Is More Than Speed Bumps

Not content with just cranking-up the bus speed, the PCI-SIG® is

driving new protocol extensions that should increase the usage and

adoption of PCI Express®. In addition to increasing clock rate by

more than three times, the PCIe® roadmap addresses virtualiza-

tion, latency and power management. These enhancements, which

increase the coupling between I/O and compute subsystems, allow

data from peripherals to be processed faster. Furthermore, PCIe is

becoming more capable to serve other high-performance system

needs, such as links between CPUs and special-function accelera-

tors and backplane applications.

During the Intel® Developer Forum in September, Intel Fellow

Ajay Bhatt provided a chronology of PCI Express, as shown in the

figure. This year PCIe 2.0 and two virtualization specifications were

approved, and early details of PCIe 3.0 extensions were released.

PCIe 2.0 Ready for the HolidaysIt’s a great time to be a PC gamer, as systems supporting PCIe

2.0 are starting to hit retail shelves. Ever since PCIe 1.0 began

replacing AGP back in 2003, high-end graphics cards have been

early adopters of the latest PCIe technology. Dell and ASUS

launched workstation and highperformance desktop PC moth-

erboards with x16 slots of PCIe 2.0 supported by the Intel® X38

Express chipset. Video enthusiasts can add graphics cards based

on the NVIDIA GeForce 8800 GT graphics processing unit (GPU)

or the ATI Radeon HD 3800 Series of GPUs.

The most notable PCIe 2.0 enhancement is the doubling of the

transfer rate, from 2.5 giga-transfers per second (GT/s) to 5 GT/s,

over PCI 1.x. There are other new features including dynamic link

speed management and improved control and alert services.

Virtualization Reduces Cost and ComplexitySeemingly every industry publication is espousing the benefits

from virtualization in data centers. Virtualization deployed on

server clusters – pools of independent servers working together

as a single system to provide high availability of services – facili-

tates load-balancing and reallocating resources to services in

high demand. The PCI-SIG is working on bus enhancements

that address virtualization and other I/O demands of high-per-

formance infrastructure, such as storage and networking.

Seemingly every industry publication is espousing the benefits from

virtualization in data centers. Virtualization deployed on server

clusters – pools of independent servers working together as a single

system to provide high availability of services – facilitates load-bal-

ancing and reallocating resources to services in high demand. The

PCI-SIG is working on bus enhancements that address virtualiza-

tion and other I/O demands of high-performance infrastructure,

such as storage and networking.

The PCI-SIG developed several specifications that provide two levels

of I/O virtualization (IOV). First, the Address Translation Services

(ATS) specification provides a set of transactions for PCI Express

components to exchange and use translated addresses in support

of I/O virtualization. Second, Single Root IOV allows multiple oper-

ating systems running simultaneously within a single computer

– single root topography – to natively share PCIe devices.

Currently under review, the Multi-Root IOV specification extends

virtualization support to multiple root topographies, such as blade

servers. This will simplify the sharing of I/O devices between soft-

ware applications and server boards. Applications will be able to

access I/O and storage devices throughout the network. Network

and storage adapters can reside on switches, not on every server

blade, which reduces component count and system complexity.

Today, most blades with root complexes have their own network

adapters, which adds cost and redundancy as peripherals and ports

are proliferated across the network infrastructure. In the future,

shared network adapters should simplify I/O load balancing and

bandwidth management within a virtualized environment.

PCIe 3.0 on the Drawing BoardIn August, the PCI-SIG released some details on the next genera-

tion PCIe architecture, PCIe 3.0, including its 8 GT/s bit rate and

backwards compatibility to prior generations. Completion of the

specification is expected late 2009, targeting products for 2010 and

beyond. The PCIe 3.0 specification is expected to make significant

improvements in throughput, latency and power management as

well as incorporate the virtualization enhancements discussed

previously. Vendors backing PCIe see opportunities to develop

Figure: PCI Express Chronology


higher performance accelerators that speedup specific tasks such

as video, encryption, XML and data mining functions.

After thorough technical analysis, the PCI-SIG approved 8 GT/s

for the bit rate, ending debate on a 10 GT/s version. The slower

speed offers cost and implementation advantages while simpli-

fying the task of ensuring backward compatibility. Components

can be manufactured in mainstream silicon process technology

and deployed with existing low-cost materials, while main-

taining full mechanical compatibility and imposing negligible

changes to the PCIe protocol stack.

One challenge to preserving backward compatibility will be the

transition away from 8b/10b encoding to a scrambling technique,

where a known binary polynomial is applied to the data stream.

The 8b/10b is a code that maintains DCbalance on differential

signal lines. On average, two bits are added for every eight data

bits, providing enough bus state changes to prevent common-mode

voltage shifts and allow clock recovery. Scrambling introduces

more DC wander than 8b/10b; therefore, the receiver (Rx) circuit

must either tolerate the DC wander as a reduction in signal margin

or implement a DC wander correction capability. The choice for the

scrambling polynomial is currently under study.

By adding non-data bits to the data stream, 8b/10b encoding

imposes a 20 percent overhead on the raw bit rate. By transitioning

to scrambling, PCIe 3.0 supports twice the throughput of PCIe 2.0

even though the bit rate increases by just 60 percent, from 5 GT/s

to 8 GT/s. This is illustrated in the preceding figure, where PCIe 2.0

and 3.0 achieve approximately 16 GB/s and 32 GB/s for a x16 link,

respectively.

The increase in throughput will simplify board designs by reducing

lane count. For example, applications deploying 10 giga-bit Eth-

ernet typically require four PCIe 2.0 lanes; this can be reduced to

two lanes with PCIe 3.0 in the future. This fanout improvement will

ease the design of dense switching boards.

Latency, Software and Power EnhancementsPCIe 3.0 developers are seeking a tighter coupling between I/O

and compute sub-systems. They are investigating multiple pro-

tocol extensions and enhancements that help server CPUs access

priority I/O data faster. There will be mechanisms that provide

“data re-use hints” that improve the caching of reusable data in

system memory, thereby reducing data latency. Another enhance-

ment supports transaction attributes and hints that optimize the

ordering of transactions within the root complex and the memory

subsystem. Also under consideration are Pause and Resume opera-

tions that control the interrupts of low priority transmissions and

allow higher priority transaction to take precedence.

As PCIe evolves beyond standard I/O interconnect to hardware

accelerators, the specification requires enhancements to help

developers maintain memory coherency within a system. Hard-

ware accelerators, unlike most I/O adapters, have their own local

memory that must remain coherent with other memory sub-sys-

tems on the network. PCIe 3.0 is investigating software model

enhancements, such as atomic read-modify-write mechanisms,

that prevent network elements from accessing stale or corrupt

data. These mechanisms help avoid having a CPU access data while

a special-function accelerator is working on it.

Power management features will be added to support dynamic

performance/ power operation modes. System software will be

able to dynamically adjust the power consumption of endpoints in

accordance to I/O throughput requirements.

PCI Express In Backplane Applications?Today, Ethernet is dominant in the backplane space. Its large

installed base, supported by a large software investment, has

proven to be very dependable. Yet, some developers are asking

whether PCI Express may make inroads as bus speeds increase

to 10 gigabit. Like Ethernet, PCI Express is becoming ubiquitous

with many chipsets supporting it natively. It also leverages years of

legacy software dating back to the 1990’s.

PCI Express offers some advantages over Ethernet. It is far more

scalable, with options to utilize links with difference lane sizes,

x1 all the way up to x32. PCI express also has lower latency and

overhead (packet header) than Ethernet, making it faster and

more efficient. These differences are magnified when packet sizes

are small, as in control plane applications. PCI Express also has

several QoS features, such as flow control and guaranteed error-

free packets and delivery, whereas Ethernet is less proactive and

requires receivers to notify the sender of dropped packets.

During the transition from one to ten gigabits, some developers

utilizing smaller payloads with heavy processing requirements may

give PCI Express consideration for the backplane. Applications such

as communications, military and high-end medical equipment may

benefit from greater scalability, lower overhead, lower latency and

the cost efficiency of PCI Express.

PCI Express technology has moved well beyond graphics applica-

tions, expanding into communications, embedded systems and

home entertainment. And with the addition of I/O virtualization

and system level enhancements, those who saw PCIe as a bridging

or transitional technology may have a change of heart. The com-

bination of a large installed base, extensive ecosystem and a long

term view may broaden the adoption of PCIe into emerging appli-

cations and new usage models.

Craig Szydlowski is a writer specializing in

business and technology. He has over 20 years

of engineering and marketing experience with

embedded and communications systems at Intel,

IBM and Siemens.

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CONTACT INFORMATION

10 • Chip-to-Chip PCI Express® Solutions Resource Catalog 2010

Integrated Device Technology, Inc. (IDT)

Integrated Device Technology, Inc. (IDT)6024 Silver Creek Valley RoadSan Jose, CA 95138USAwww.IDT.com/go/PCIExpress

Highest performance: Low latency (170ns for upstream read requests on the TSi384). Innovative features such as short term caching provide signifi-cant performance advantages enabling designers more competitive advantagesPinout compatible: Provides low risk replacement or second sourcing opportunity for existing designs

TECHNICAL SPECS

Superior buffering and queuing architecture for optimal latency and throughputCompliant to the following specifications: PCIe Base Spec (Rev 1.1), PCIe-to-PCI/PCI-X Bridge Spec (Rev 1.0), PCI-to-PCI Bridge Spec (Rev 1.2), PCI Local Bus Spec (Rev 3.0), PCI Bus Power Management Interface Spec (Rev 1.2)Support for four external PCI bus masters through an integrated arbiter and for an external PCI bus arbiterSupport for Masquerade mode (ability to overwrite vendor and device ID from EEPROM)JTAG IEEE 1149.1, 1149.6 support

AVAILABILITY

All IDT PCI Express bridging solutions are available now.

APPLICATION AREAS

PC adapter cards (communications, graphics, imaging and multimedia), motherboards (PC, server SBC, industrial PC), processor boards and modules (COM), multifunction printers, digital video recorders and surveillance systems (DVR, NVR), Storage Area Network (SAN, RAID HBA cards), Network Attached Storage and Direct Attached Storage (NAS, DAS), routers and switches, line cards and NICs.

IDT PCI Express® BridgesSupported PCI Express Standards: PCI Express Base Specifications (Revision 1.1)

The IDT Tsi382 and Tsi381 x1 PCI Express (PCIe®) to PCI Bridges and Tsi384 x4 PCIe to PCI/X Bridge (formerly Tundra Semiconductor® products), are compliant to the latest specifications, including PCI Express Base Specifi-cation 1.1. With only two power supplies required and no power sequencing constraints, IDT PCIe bridges offer sig-nificant advantages in cost, power, board space and ease of design. Due to best-in-class performance, solution cost and quality, these devices are playing a critical role in the roll-out of a wide range of PCIe applications.

The Tsi382 and Tsi381 connect the PCIe protocol to the PCI bus standard. The PCIe interface supports x1 lane PCIe configuration, offering exceptional throughput performance of up to 2.5 Gbps per transmit and receive direction. The Tsi382, available in a 10x20 mm BGA package, coupled with its simple design requirement, makes it the smallest footprint bridge available for appli-cations where space is a premium. A 20x20 mm QFP package is also available for cost sensitive applications.

The Tsi384 connects the PCIe protocol to the PCI/X bus standards. Its PCIe interface supports 1, 2, or 4 lanes, offering exceptional throughput performance of up to 10 Gbps. The device’s PCI/X interface can operate up to 133 MHz in PCI-X mode or up to 66 MHz in PCI mode with typical power consumption of 1W, and incorporates advanced power management to minimize power con-sumption during operation. Unused PCIe lanes can be powered off automatically or by configuration.

IDT PCIe bridges offer extensive flexibility by supporting transparent, opaque and non-transparent addressing modes.

FEATURES & BENEFITS

Most advanced PCIe bridges: Compliant to the latest PCI Express and PCI/X specificationsHighest quality: Proven interoperability and bug-free operation. Lower development risk and design churn to bring products to market fasterSimplest design: No power sequencing restrictions and only two power supply voltages required. Backed by a comprehensive suite of design tools, IDT PCIe bridges minimize design effort and provide an oppor-tunity to save cost

®

ICsICs

www.eecatalog.com/pcie Chip-to-Chip • 11

CONTACT INFORMATION

Integrated Device Technology, Inc. (IDT)

Integrated Device Technology, Inc.6024 Silver Creek Valley RoadSan Jose, CA 95138USAwww.IDT.com/go/PCIExpress

AVAILABILITY

All IDT PCI Express switching solutions are available now.

APPLICATION AREAS

Server, storage, communications, embedded and con-sumer applications.

IDT® PCI Express®

Switching SolutionsSupported PCI Express Standards: PCIe® Revision 1.0a, 1.1, 2.0

OS Support: Windows, Linux, Others

Bus Interface: PCIe

IDT® provides the industry’s broadest and most com-prehensive family of PCI Express® switching solutions. Through extensive collaboration with leading customers, IDT offers solutions optimized to maximize performance per watt for the most demanding server, storage, com-munications, embedded and consumer applications. With switching solutions optimized for system intercon-nect and I/O connectivity, IDT is the right choice!

IDT I/O Connectivity Solutions: The IDT family of I/O con-nectivity switches is the broadest, most targeted set of I/O connectivity solutions aimed at providing high-per-formance “aggregation” or “fan-out” switching to fill the connectivity gap created by north bridge devices with limited high performance I/O connectivity. The family offers the most comprehensive set of solutions, with con-figurations ranging from 3 to 48 lanes and 3 to 12 ports.

IDT System Interconnect Solutions: IDT introduced the industry’s first PCI Express Gen1 and Gen2 system interconnect solutions. Consisting of a broad family of configurations for control, data and services plane traffic, the solutions provide deterministic, non-blocking, line rate performance and advanced support for inter-processor communications and peripheral sharing in bladed and large-scale embedded applications. The family includes solutions ranging from 16 to 64 lanes and 8 to 16 ports.

FEATURES & BENEFITS

Industry’s broadest and most comprehensive PCIe switch family of Gen1 and Gen2 solutions, from 3 ports to 16 ports and 3 lanes to 64 lanes — optimal fit for targeted applications.High-performance, low-latency switch designs — full line rate throughput on all transactions.Industry leading, low-power designs — reduced thermal management, shorter design cyclesPlug-and-play PCIe switches — no proprietary hardware or software development required.Industry’s smallest PCIe switch packaging — reduced board space, increased design flexibility

®

ICsICs

CONTACT INFORMATION


Xilinx, Inc.

Xilinx, Inc.2100 Logic DriveSan Jose, CA 95124-3400USA408-559-7778 [email protected]/connectivity

TECHNICAL SPECS

Virtex-6 FPGA and Spartan-6 FPGA Connectivity KitsVirtex-5 FPGA Development Kit for PCI ExpressSpartan-3 FPGA PCI Express Starter Kit

AVAILABILITY

Virtex-5 FPGA and Spartan-3 FPGA PCI Express kits available now.

For availability of Virtex-6 FPGA and Spartan-6 FPGA Connectivity kits, visit: www.xilinx.com/kits.

APPLICATION AREAS

Automotive, Aerospace and Defense, Broadcast, Consumer Electronics, Wired and Wireless Commu-nications, as well as Industrial, Scientific and Medical Instrumentation

Xilinx Solutions for PCI ExpressSupported PCI Express Standards: Versions 1.1 and 2.0

OS Support: Windows and Linux

Bus Interface: PCI Express

Xilinx® solutions for PCI Express® enable designers to meet the most demanding bandwidth, power, and cost requirements for developing systems compliant with the widely adopted serial interconnect standard.

These solutions are enabled by the Xilinx integrated blocks for PCI Express in both the high performance Virtex® and low-cost Spartan® FPGA series. In the latest generation Virtex-6 and Spartan-6 devices, con-figurable PCIe blocks are implemented with built-in high-speed serial transceivers to save valuable logic resources and power, while delivering cost-effective features, performance, and programmability.

PCI Express designs can be up and running right out-of-the-box with Xilinx connectivity develop-ment kits. As part of the Xilinx Connectivity Targeted Design Platform, these flexible, scalable kits provide hardware, software tools, IP, customizable reference designs, and PCI Express form-factor cards to jump-start development, integration, and debug of system interfaces for a wide range of chip-to-chip, backplane, and box-to-box applications.

FEATURES & BENEFITS

Virtex-6 FPGA PCI Express blocks support x1, x2, x4 and x8 Gen1 (2.5Gbps) and Gen2 (5Gbps) interfacesVirtex-6 FPGA GTX transceivers enable up to 6.5Gbps with industry’s best signal integrity and eight programmable levels of Transmit Pre-emphasis and four programmable levels of Receive EqualizationSpartan-6 FPGA PCI Express block supports x1 Gen1 (2.5Gbps) interfaces with less than half the power of previous generationsSpartan-6 FPGA GTP transceivers enable up to 3.125Gbps with programmable Transmit Pre-emphasis and Receive Equalization

ICsICs

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CONTACT INFORMATION


Protocol Analysis ToolsPr

otoc

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naly

sis

Tool

s

LeCroy Corporation

Zero Time Search provides a fast way to search large traces for specific protocol terms.Config space can be displayed in its entirety so that driver registers can be verified.

TECHNICAL SPECS

Analyzer Lanes supported: X1,x2,x4,x8,x16 Speeds: 2.5GT/s, 5GT/s and 8GTs Probes/Interposers: active and passive PCIe slot,

XMC, AMC, express card, express module, mini-card, MidBus, multi-lead, and others.

Form factor: Card, ChassisExerciser

Lanes supported: X1,x2,x4,x8,x16 Speeds: 2.5GT/s, 5GT/s Emulation: root complex and endpoint emulation

Protocol Test Card Speeds: 2.5GT/s and 5GT/s operation Tests: Add-in-card test BIOS Platform Test Single Root IO Virtualization Test

APPLICATION AREAS

Mezzanine Boards, Add-in Cards, Host Carrier Systems, System Boards, Chips

LeCroy’s PCI Express® Protocol Analysis and Test Tools

Compatible Operating Systems: Windows XP/Vista

Specification Compliance: PCI Express Standards: 1.1, 2.0, and 3.0

Whether you are a test engineer or firmware developer, LeCroy’s Protocol Analyzers will help you quickly iden-tify, troubleshoot and solve all your protocol problems. LeCroy works closely with industry standards groups such as the PCI-SIG®, PICMG, VITA and the Intel Embedded Communication Alliance to help developers rapidly bring to market high performance and reliable PCI Express pro-tocol test solutions.

LeCroy’s products include a wide range of probe connec-tions to support XMC, AMC, ATCA, microTCA, Express Card, MiniCard, Express Module, HP Blade Server Mod-ules, MidBus connectors and flexible mult-lead probes for PCIe® 1.0a, 1.1(“Gen1” at 2.5GT/s) , PCIe 2.0(“Gen 2” at 5 GT/s) and PCIe 3.0(“Gen 3” at 8 GT/s).

The high performance SummitTM T3-16 Protocol Analyzer features the new PCIe virtualization extensions fo SR-IOV and MR-IOV and in-band logic analysis.

LeCroy offers a complete range of protocol test solutions, including analyzers, exercisers, protocol test cards, and physical layer testing tools that are certified by the PCI-SIG for ensuring compliance and compatibility with PCI Express specifications, including PCIe 2.0.

FEATURES & BENEFITS

One button protocol error check. Lists all protocol errors found in a trace. Great starting point for beginning a debug session.Flow control screen that quickly shows credit balances for root complex and endpoint performance bottlenecks. Easily find out why your add-in card is underperforming on its benchmarks.LTSSM state view screen that accurately shows power state transitions with hyperlinks to drill down to more detail. Helps identify issues when endpoints go into and out of low power states.Full power management state tracking with LeCroy’s Interposer technology. Prevents loosing the trace when the system goes into electrical idle.LeCroy’s Data View shows only the necessary protocol handshaking ack/naks so you don’t have to be a protocol expert to understand if root complexes and endpoints are communicating properly.Real Time Statistics puts the analyzer into a monitoring mode showing rates for any user term chosen. Good for showing performance and bus utilization of the DUT.

LeCroy Corporation3385 Scott Blvd.Santa Clara, CA, 95054USA1 800 909-7211 Toll Free1 408 727-6622 [email protected]://www.lecroy.com

www.eecatalog.com/pcie Board-to-Board • 15

CONTACT INFORMATION

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AMTELCO XDS

FEATURES & BENEFITS

The 8-Span XDS PCIe T1/E1/J1 board features:• Eight T1/E1 spans• 256 channels of voice resources with call

analysis capabilities• Two analog inputs for music-on-hold

The 4-Span XDS PCIe T1/E1/J1 board features:• Four T1/E1 spans• 128 ports of conferencing• 128 channels of voice resources with call

analysis capabilities • Two analog inputs for music-on-hold

The Best Choice for PCI Express!

With built-in intelligence, the AMTELCO XDS PCI Express T1/E1/J1 Boards are the best choice for your applications! The XDS PCIe T1/E1/J1 boards are available in four and eight span configurations, and feature Primary Rate ISDN for both T1 and E1, and selectable 75 ohm/120 ohm E1 interface, or 100 ohm T1 interface.

The XDS PCIe T1/E1/J1 boards include D4 and ESF framing for T1, AMI, and B8ZS support for T1, CRC4 and HDB3 support for E1, along with program access to either PRI layer 2 or 3 for port control. Also included is DTMF detection and generation (one per B channel), call progress tone generation, and status LEDs for each port that provide red, yellow, and blue alarm indica-tions. Robbed-bit signaling protocols include ground start, loop start, E&M and Q.421. These boards also support QSIG features for interfacing to PBXs that are QSIG enabled. Currently supported audio playback formats include A-law, μ-law, and ADPCM. The Voice Resource Library is supported in various operating systems.

The AMTELCO XDS PCIe T1/E1/J1 boards are PCIe compliant. Software drivers are available for the most common operating systems, including Microsoft® Windows®, Linux, Debian, Ubuntu, Gentoo Linux 2006.0 (kernel 2.6), and Fedora Core 5 (kernel 2.6). An Asterisk® channel driver is also available.

AMTELCO software driver packages are distributed free of charge to XDS customers, with open source code for the driver and all supporting applications. Complete software driver packages are available for download on the XDS Web site.

Watch for these new XDS boards - coming soon!

• XDS PCIe 8-Port 2/4-Wire E&M Board supporting Type I and Type V signaling protocols, as well as independent control of signaling leads for use with radio interfaces and push-to-talk applications

• XDS PCIe 12 and 24-Port Loop Start Boards with incoming Caller ID support

• XDS PCIe 24-Port High Density Station Port Boardwith support for Caller ID information display, visual Message Waiting Indicators, and on-board ring generation

AMTELCO XDS800.356.9224 or608.838.4194 Phone 608.838.8367 Fax [email protected]

16 • Board-to-Board PCI Express® Solutions Resource Catalog 2010

CONTACT INFORMATION

Connect Tech

Connect Tech Inc42 Arrow RoadGuelph, ON N1K 1S6Canada1-519-836-1291 Telephone1-519-836-4878 [email protected]

TECHNICAL SPECS

PCI Express serial products compatible with x1, x4, x8 and x16 PCIe slotsVarious cabling options, DB-9 and DB-25 cables, external I/O boxesCustom baud rates availableRoHS Compliant

AVAILABILITY

Immediate

APPLICATION AREAS

Industrial Automation, Material Handling, Transporta-tion, Military and Aerospace, Test & Measurement, Point of Sale

PCI Express SolutionsSupported PCI Express Standards: PCI Express x1, x4, x8, x16 compatible, PCI/104-Express, PCIe/104

OS Support: Windows 2000/XP/XPe/Server2003/ CE/Vista, Linux, QNX

Bus Interface: PCI Express

Connect Tech’s PCI Express solutions include a variety of options. Choose from multi-port serial cards, burn-in racks, dump switches and various adapters.

BlueStorm/Express products are available with 2 to 16 serial ports; low profile and standard height designs are available. The BlueStorm/Express line offers RS-232/422/485 connectivity; compatible with any x1, x4, x8 or x16 PCIe slot.

The Xtreme/104-Express serial board is compatible with PCIe/104 and PCI/104-Express stacks. It offers 8 x RS-232/422/485 serial ports and optional isolation.

PCIe Dump Switch is ideal for the software developer. Should a system lock up occur, the push of the dump switch button forces an NMI/SERR triggering a crash dump or drops execution into your operating system’s debugger.

PCIe to PCI/104-Express adapters are an essential tool for the developer that does not have a PCI/104-Express stack on hand. This allows for ongoing development as your PCI/104-Express board can be installed in a stan-dard desktop PCIe slot.

The PCI/104-Express to PCIe adapter allows a PCIe board to reside in a PCI/104-Express stack. This is ideal for those working with hardware not yet available in the PCI/104-Express standard.

PCIe Burn-in Rack allows the burn-in of up to ten cards simultaneously without the need for a dedicated com-puter system.

FEATURES & BENEFITS

PCIe multi port serial cards; choose up to 16 ports, RS-232/422/485, low profile and standard height modelsPCIe Dump Switch, perfect debug tool for Software EngineersPCIe Burn-in Rack, accommodate up to 10 PCIe cardsPCI/104-Express, 8 port serial cards, RS-232/422/485 configurable, optional isolationPCI/104-Express adapters

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CONTACT INFORMATION

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Dynamic Engineering

• Tsi384 bridge - higher Performance than PEX based designs

• Supports DMA & Interrupts• Matched length, differentially routed, Impedance

controlled rear IO from Pn4• Local power supplies using +12V from PCIe

connector. ±12(1A+), 5(10A), 3.3(10A) supplied to PMC

• Zero Slot Fan options using the thickness of the PCB plus special low profile fans to reduce the rear dimension to the legal PCI height.

• Front side clearance is fully compliant with the carrier height requirement on slot 2

• Need more than 64 watts – request the additional power cable

Need customized features? Email your requirements to [email protected]

PCIeBPMCX1 - PCIe [Express] PMC Adapter/Carrier 1, 4 & 16 lane

PCI Express is in more and more new PC’s. Dynamic Engineering’s first module was to support 4 lane slots. With its recent roll out into full production, customers immediately asked for a 1 lane version to support multiple PCIexpress needs within 1 chassis. Within 48 hours we were able to modify our hardware and provide an immediate solution to our customers. The result is the availability of both a 1 (PCIeBPMC) and 4 (PCIeBPMCx1) lane PCI Express module. Let us ship one to you today. We can custom”er”ize our hardware for you too – just let us know what you need. Please pass this along to your engineers and purchasing departments. We highly recommend ordering a PCI Express carrier today to become familiar with the new platform. http://www.dyneng.com/pciebpmcx1.html

Use your PMC with a newer style PC. The new PC’s have PCI Express connectors, many times eliminating PCI Slots. The PCIeBPMCX1 ( PCIe Bridge PMC 1 slot) adapter / carrier converter card provides the ability to install one PMC card into a standard PCIe (Express) 4 lane slot. Suitable for PCI or PCI-X operation with the PMC; 32 bit or 64 bit data and 33, 66, 100 or 133 MHz. clock. Auto selected or switch programmable speeds. The bridge can operate with 1, 2, 3, or 4 lanes active and can be installed into slots with more than 4 lanes if desired. “Dynamic Data Sheet” http://www.dyneng.com/pciebpmcx1.html

1 & 4 lane,

PCI/PCI-X speed,

PCIe / PMC Compliant design

32 or 64 bit operations at 33, 66, 100 or 133 MHz

Status LED’s

DYNAMICENGINEERING

Dynamic Engineering150 DuBois St #CSanta Cruz, CA 95060831-457-4793 Phone831-457-8891 [email protected] http://www.dyneng.com


CONTACT INFORMATION

Interphase

Interphase2901 North Dallas Parkway,Suite 200Plano, Texas 75093USA1 214-654-5000 [email protected]

• GTP-u protocol support• Compression/decompression

TECHNICAL SPECS

Architecture• Processor OCTEON Plus 56xx processors running

at up to 800MHz• 8, 10, or 12 CoreMemory• RAM Up to 4GB of DDR2 SDRAM System memory• 8 MB NOR Flash, Up to 2 GB NAND Flash• Optional 128MB of Persistent MemoryMechanical• Form Factor PCI Express, Standard Height, Full

Length• Length 255 mm (10 in)• Width 98 mm (3.86 in)

AVAILABILITY

December 2009

APPLICATION AREAS

Enterprise, Wireless (3G, WiMax, WLAN, Femtocell), Voice Over IP (VoIP), and IMS network infrastructure

iSPAN® 56MC2 10 GE OCTEON™ Packet ProcessorSupported PCI Express Standards: PCI Express v1

OS Support: Cavium Simple Executive, Cavium Linux, and Wind River PNE Linux with Cavium OCTEON extensions

Bus Interface: 2x 10GE: PCI Express x4 or 1x 10GE: PCI Express x8

The Interphase iSPAN® 56MC2 10 GE OCTEON Packet Pro-cessor Card extends the broad portfolio of communication processing and network processing solutions to address the growing need for 10 GE wire-speed packet processing solutions for the delivery of broadband services in the Enterprise, Wireless (3G, WiMax, WLAN, Femtocell), Voice Over IP (VoIP), and IMS network infrastructure.

With its one or two 10 GE interchangeable SFP+ modules, powerful onboard OCTEON Plus packet processor, dual management interface, and upgradeable memory, the iSPAN 56MC2 is extremely versatile and provides the functionality necessary for migrating to next generation infrastructures and converged networks.

Cavium Simple Executive and Linux®-based ready-to-use application / protocol suites are available to transform the 56MC2 into a specialized communications interface which can be easily integrated into solution platforms. Interphase partners SafeNet and 6WIND offer software toolkits that have been pre-integrated with Interphase OCTEON-based solutions, taking advantage of the on-chip security accel-erator: the SafeNet QuickSec™ 5.0 toolkit and 6WIND 6WINDGate™ toolkit.

FEATURES & BENEFITS

Cavium Networks high performance OCTEON Plus 56xx family of Packet Processors• NSP – Network Services Processor supports

encryption, TCP acceleration, compression/decom-pression, networking and QOS

• CP – Secure Communications Processor supports encryption, networking, TCP acceleration and QOS

Front panel I/O options: • 2x 10 GE SFP+ or 1x 10 GE SFP+• One RS-232 console portApplication Support for 3rd-party Packet Processing Modules:• TCP/IP off load• Wire-speed IPsec acceleration• SRTP Off-load• IPv4/IPv6 L2/L3 wire-speed forwarding• Unicast and multi-cast routing acceleration• Stateful Firewall• Transport Protocols• Mobile-IP

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CONTACT INFORMATION

Moxa

Moxa Americas, Inc.3001 Enterprise StreetBrea, CA 92821USA714-528-6777 Telephone714-528-6778 [email protected]

Drivers provided for Windows (2000, XP/2003/Vista/Windows 7 x86 & x64), Windows CE 5.0, Windows XP Embedded, DOS, Linux 2.4/2.6, FreeBSD 4/5, QNX 6, SCO Open Server 5/6, UnixWare 7128 byte FIFO and on-chip H/W, S/W flow control15KV ESD protection

AVAILABILITY

Now

APPLICATION AREAS

POS / ATM / KIOSK / Laboratory Testing / Data Acquisition

PCI Express Serial BoardsSupported PCI Express Standards: PCI Express x1

OS Support: Drivers provided for Windows (2000, XP/2003/Vista/2008 x86 & x64), Windows CE 5.0, Windows XP Embedded, DOS, Linux 2.4/2.6, FreeBSD 4/5, QNX 6, SCO Open Server 5/6, UnixWare 7

Bus Interface: PCI Express x1

Moxa offers industrial-grade serial communication solutions for PCI Express or PCIe slots. The advanced UART + CPU on one chip ensures high throughput for serial data, and advanced communication functions are available to provide a high degree of control.

Moxa’s PCI Express boards are the best choice for industrial automation engineers and system inte-grators, especially given the comprehensive O/S support under Windows, Unix, and Linux. The Moxa PCI Express product line offers RS-232/422/485 serial ports which support a 921.6 Kbps baud rate and provide full modem control signals to ensure com-patibility with a wide range of serial peripherals. In addition, the board’s PCI Express x1 classification allows it to be installed in any PCI Express slot.

FEATURES & BENEFITS

First in the world to use a PCIe UART + CPU on one chip which offers the highest throughput speeds along with decreased CPU usage1, 2, 4, and 8 port models availableOptical Isolation models availableLow profile form factor availableSupports RS-232/422/485 interfaces

TECHNICAL SPECS

PCI Express x1 compliant921.6Kbps maximum baud rate for high data transmission speeds

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CONTACT INFORMATION

Spectracom

Spectracom95 Methodist Hill DriveRochester, NY 14623USA585-321-5800 Telephone585-321-5219 [email protected]

TECHNICAL SPECS

5 nanosecond resolution+/- 100 nanosecond accuracy to incoming time refer-enceAccurate time in the absence of an internal referenceZero latency time readsNEW FOR 2010: Precision Time Protocol (PTPv2) IEEE-1588 master or slave operation

Time Code ProcessorOS Support: Linux, Solaris, Windows

Bus Interface: PCI express x1 add-in board can be installed in any PCIe slot

The TSync-PCIe offers the utmost flexibility and easy integration of precise timing into a computing appli-cation. It synchronizes to multiple prioritized external time references to ensure accurate time. An onboard precision oscillator locks to the external reference for 5 nS resolution. 4 time tag inputs time stamp mul-tiple events at a max rate over 50 kHz. Other features include 4 programmable alarm signals or periodic outputs such as 10 MHz or 1 pulse-per-second. The card can also generate time codes to synchronize other devices and systems.

Key to the TSync functionality is the ability to generate interrupts. Using a Spectracom driver package for the latest versions of popular operating systems, you may configure your card using interrupt-driven algorithms to support your unique applications.

Most of the card’s functions are developed in firm-ware, so it can adapt for your needs or changes in deployments.

New for 2010 is the ability for the card to act as either a precision time protocol (PTPv2) IEEE-1588 master or slave.

FEATURES & BENEFITS

Multiple prioritized timing input references. When one reference is lost, the unit automatically switches to the next one.Synchronization to variety of time codes: IRIG-A, IRIG-B, IRIG-G, IEEE-1344, NASA36 (AM and DCLS) or GPS signals via onboard or remote receiver.Precision oscillator keeps time in the absence of an external reference. Optional enhanced accuracy for critical applications.Drivers for the latest versions of Linux, Windows and Solaris.Low profile form factor fits any PCI Express card slot: half height (full height bracket included), x1 bus.

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CONTACT INFORMATION

Innovative Integration

Innovative Integration2390 Ward AvenueSimi Valley, CA 93065USA805-578-4260 Telephone805-578-4225 [email protected]

TECHNICAL SPECS

Xilinx Spartan3A-DSP or Spartan 3 1-2M Gate FPGA Two 2MB SRAMsPCI Express with <150 MB/s data rates Analog and digital IO integrated with FPGA core Lower Overall CostIndustry-standard COTS works with any PCI Express system or host card Add DSP and customize features to meet unique requirements Data buffering sup-ports high rates and large data sets for FFTsFastIndustry-standard host bus eliminates custom hardware & achieves higher channel counts Improve performance with real-time signal processingEliminate custom hardware & simplify system design using intelligent IO and PCI ExpressAll cards are also readily installed into Innovative Integration’s eInstrument Embedded PC, SBC-ComEx Single-Board Computer, and Andale Data Loggers.

AVAILABILITY

Now!

APPLICATION AREAS

Aerospace/Defense, Broadcast, Industrial Automation, Medical Imaging, Motor Control, Wireless Communications

X3 Family PCI Express Cards cPCI, PCI or XMCSupported Xilinx FPGA/CPLDs: Spartan-3/3E/3A/3AN, Spartan-3A DSP

The X3 Family PCI Express cards are available on a stan-dard half-height, single slot PCI Express plug-in card with a PCI Express interface or a 3U card with a cPCI interface, or XMC mezzanine module. Intelligent, Customizable I/O, High Performance I/O & FPGA Core. Eliminate custom hardware by harnessing the power of PCI Express & Cus-tomizable FPGA.

All X3 family cards utilize the common bus interface to deliver high data throughput to the Host, along with the flexibility of user-customizable FPGA signal processing. Board specific analog or digital I/O flows directly into the user-configurable Spartan 3 logic device. The supplied stock logic functionality allows the board to be used out-of-the-box as high-speed I/O board in which the large onboard RAM is configured as a virtual FIFO, to increase the instantaneous load-carrying capacity of the board to eliminate data overruns/underruns during real-time streaming.

However, using the VHDL source code or MatLab board support package contained within the optional Framework Logic software package, you can readily customize the functionality of the FPGA to include real-time processing such as independent FIR & IIR filters on each channel, real-time FFT processing, ultra-fast feedback & control loops & much more. Use of MatLab/Simulink in conjunction with the supplied MatLab board support package opens an entirely new range of real-solution possibilities.

FEATURES & BENEFITS

X3-10M - 8 simultaneous channels of 25 MSPS 16-bit A/D, and 1.8M FPGA with DSPX3-25M - (2) 105 MSPS A/Ds, (2) 50 MSPS D/As, Spartan 3A DSP 1.8M FPGAX3-A4D4 (4) 4 MSPS A/Ds, (4) 50 MSPS DACs and 1.8M FPGA with DSPX3-Servo PCI Express XMC Module - (12) 250 KSPS A/Ds, (12) 2MSPS DACs, 1.8M FPGA with DSPX3-DIO - LVDS or LVCMOS Digital IO and 1M FPGA with DSPX3-SD - 16 Channel, 216 KHz, 24-bit Analog InputX3-SDF PCI Express XMC Module, (4) 24-bit, Fast Sigma-Delta A/D <110 dB, 1M FPGA, 4 MB MemoryX3-Servo - (12) 250 KSPS A/Ds, (12) 2MSPS DACs, 1.8M FPGA with DSPX3-Timing Precision Timing for Sample Rate Genera-tion and Triggering Controls with GPS-disciplined and 1 PPM Reference Clocks

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TECHNICAL SPECS

MATLAB and RTL tools in the FrameWork Logic Board Support Packages enable you to customize the X5 modules for your application requirementsCompact IEEE 1386 card format (75x150mm), Inte-grate into any VITA 42.3 PCI Express system, <30 GMACs/s (SX95T) integrated with memory blocks and logic, Real-time memory performance to 4 GB/s for FPGA data buffering and computation<1GB/s transfer rates to host eliminates custom hardware requirementsReal-time signal processing integrated with the IOTight, real-time host card inte-gration with Serial RIO, Aurora & custom protocolsPCI Express, 8 lane interface, Analog and Digital IO integrated with FPGA, <1 GB/s dedicated secondary host interface

AVAILABILITY

Now!

APPLICATION AREAS

Aerospace/Defense, Broadcast, Industrial Automation, Medical Imaging, Wireless Communications

X5 Family PCI Express cPCI, PCI, or XMCSupported Xilinx FPGA/CPLDs: Virtex-5 SXT, Virtex-5 FXT

The X5 family integrates high performance I/O with a Xilinx Virtex5 FPGA computing core. Available on a stan-dard half-height, single slot PCI Express plug-in card with a PCI Express interface or a 3U card with a cPCI interface, or XMC mezzanine module. Intelligent, Customizable I/O, High Performance I/O & FPGA Core.

Innovative’s unique architecture provides high performance data streaming to the host that is flexible & extensible for all types of applications. It’s fast & easy to use – allowing you to concentrate on your application work because it handles all the data flow & routing. You can freely mix high rate data streams with control & status making it easy to adapt to your application, yet still achieve the full GB/s data rate capabili-ties of the PCIe interface.

All X5 cards are architected to deliver high data throughput to the Host, along with the flexibility of user-customizable FPGA signal processing.

Board specific analog or digital I/O flows directly into the user-configurable Xilinx 5 logic device. The supplied stock logic functionality allows the board to be used out-of-the-box as high-speed I/O board in which the large onboard DDR2 DRAM is configured as an enormous virtual FIFO, to dramatically increase the instantaneous load-carrying capacity of the board to eliminate data overruns/underruns during real-time streaming.

FEATURES & BENEFITS

X5-400M - Two 400 MSPS, 14-bit TI ADS5474 ADCs and Two 500 MSPS, 16-bit DACs, Virtex5 FPGA and 512 MB MemoryX5-COM - Four Ethernet/SRIO/Gigabit Serial Ports, Virtex5 SXT or FXT FPGA and 512MB MemoryX5-GSPS - Two 8-bit National ADC08D1500 A/Ds, Virtex5 FPGA and 512 MB MemoryX5-TX - Four 500 MSPS or Dual 1 GSPS, 16-bit DACs, Virtex5 FPGA with 512MB DDR2 DRAM and 4 MB QDR SRAM MemoriesX5-G12 - Dual channel 1 GSPS,12-bit Digitizer, Virtex5 FPGA and 512MB Memory X5-210M - Four 250 MSPS 14-bit A/Ds, Virtex5 FPGA, and DDR2/QDR-II MemoryX5-RX - Four 200 MSPS 16-bit A/Ds, Virtex5 FPGA, 512MB DRAM/ 4MB SRAMModules are also readily installed into Innovative Integration’s eInstrument Embedded PC, SBC-ComEx Single-Board Computer, and Andale Data Loggers.

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TECHNICAL SPECS

Modern PCI Express interface also dramatically improves system data transfer rates, enabling higher channel data rates and new features such as logging raw digitized data at full rate.Receiver IP cores are available in netlist or source form for custom applications Innovative’s X5 FrameWork Logic Tools allow developers using RTL & MATLAB to rapidly integrate the SDR cores into their application logic.Full simulation models for the receiver and hardware IP provide comprehensive support for signal process-ing design and hardware integrationMATLAB Simulink tools support end-to-end simula-tion of the receiver channel & give a complete verification of the signal processing, including the capability to go directly into hardware while using MATLAB for debug & verification.The X5 digitizers are state-of-the-art high perfor-mance front ends for wireless, RADAR, and medical applications on an industry-standard XMC (VITA 42.3) PCI Express module.

AVAILABILITY

Shipping now.

APPLICATION AREAS

Broadcast, Industrial Automation, Medical Imaging, Wireless Communications

Wireless IP Cores for Software Digital Radio ApplicationsSupported Xilinx FPGA/CPLDs: Virtex-5 LXT, Virtex-5 SXT, Virtex-5 FXT

The Wireless IP Cores for Software Digital Radio Application products offer a range of capabilities for both narrowband & wideband receiver applications from 16 to 4096 chan-nels with sampling rates up to 400 MSPS and over 90 dB dynamic range. The 16 & 32 channel cores are more flex-ible & adaptable than the higher channel density cores, providing independently programmable features for tuning, decimation, filtering & gain control making these products ideal for multi-protocol applications. The 256 channel tun-able channelizer and 4096 equi-space channel cores provide a very high number of channels for cellular test equipment, surveillance, & satellite communications applications.

The IP cores are implemented on Innovative’s X5-400M, a PCI Express XMC module with Xilinx Virtex5 SX95T & dual channel 400 MSPS digitizers. System designers can buy the X5-400M card pre-configured with the receiver IP of their choice ready to use. These new products based on Virtex 5 & PCI Express offer system designers a variety of COTS SDR receiver solutions with the latest technologies. They offer a lower overall system cost per channel & reduced development risk, while providing a flexible platform for adopting new & evolving standards for the future. Download data sheets & pricing now at www.innovative-dsp.com

FEATURES & BENEFITS

IP-RI-MDDC16 - 16 ind. ch. of DDC with prog. gain & 121 tap pulse filters IP-RI-MDDC32 - 32 ind. ch. of DDC with prog. gain & 121 tap pulse filtersIP-RI-CHTU128/256 - 128 or 256 channelizer with prog. tuning, gain & ch. filteringIP-RI-CHTU32/4096 - 32 to 4096 channelizer with fixed, equi-spaced channelsIP-PSK-DEMOD - Demodulator for BPSK, QPSK, OQPSK, and 8-PSK data with carrier trackingIP-TINY-DDS - Small footprint Programmable Direct Digital Synthesizer with 90 dB SFDR IP-RI_FRU - High resolution fractional resampler

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CONTACT INFORMATION

JDSU

JDSU430 N McCarthy BlvdMilpitas, CA [email protected]://www.jdsu.com/snt

TECHNICAL SPECS

The only analyzer capable of multi-protocol cor-relation across 13 storage and computing protocol domains simultaneously on a single platform to ensure interoperability between different bus types.Simultaneous PCI Express® logic and protocol analysis ensures bus efficiency and reliability.Extensive display capabilities – including command, state summary, Q-Tag Tree Listing, histogram and statistics views – provide unparalleled visibility.Extremely easy-to-use interface enables developers to test all 13 bus types supported by JDSU Bus Doc-tor Analyzers from a single GUI, including CE-ATA, ATA, SCSI, SATA, Compact Flash, PCMCIA, PCI-X™, and USB.Exports results for off-line analysis, formats reports, and offer tips to accelerate learning of new features.

AVAILABILITY

Available today

Bus Doctor™ Protocol Analyzer for PCI Express® V. 2.0Supported PCI Express Standards: PCI Express® specifications 1.0, 1.0a, 1.1, and 2.0

OS Support: Vista Ultimate, Vista Enterprise, Windows XP Profes-sional, Windows XP Professional (64-bit), Windows 2003 Server, Windows 2003 Server (64-bit)

Bus Interface: ATA/ATAPI, SCSI I-320, SAS, SATA, Memory Card

The Bus Doctor™ Protocol Analyzer for PCI Express® v. 2.0 from JDSU empowers computing, storage, silicon, and design engineers to simplify and accel-erate design and troubleshooting of devices utilizing PCI Express® technology. With line signaling rates reaching up to 5.0 Gb/s, developers need a com-prehensive testing platform capable of providing visibility, flexibility, and advanced trace capture capa-bilities. Built upon a foundation of patented search and analysis logic implemented in hardware, the Bus Doctor brings affordable real-time capture, decode, and analysis capabilities to engineers to ensure the efficiency, reliability, and interoperability of their PCI Express®-based devices, including Host Board Adapters (HBAs), server and storage arrays, and Net-work Interface Cards (NICs).

FEATURES & BENEFITS

Supports PCI Express® Gen 1 (2.5 Gb/s) and 2 (5.0 Gb/s) bus widths of x1, x4 and x8.Industry’s largest trace buffer (16 GBytes) capable of being divided into up to 1024 segments for capture across multiple events.Powerful 12-level trigger sequencer with support for counters and timers.New Traffic Summary View and Q-Tag Tree Listing.

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