Paul Scherrer Institute The PSI DRS4 Integrated Circuit Chip Stefan Ritt.

Paul Scherrer Institute

The PSI DRS4 Integrated Circuit Chip

Stefan Ritt

Stefan Ritt March 15th, 2011DPP Workshop PSI 2

Agenda

• Introduction to Switched Capacitor Array Chips–Comparison with FADCs–Overview of chips on the market

• The DRS4 chip–Design principles–Special features–Some applications

• New ideas for DRS5 chip to be designed in 2011–Increased bandwidth–Zero dead time


Introduction toSwitched Capacitor

ArrayChips


Detectors in Particle Physics

Particles interact with matter and produce light:

Signal: ~ 100’s mV

10-100 ns


Flash ADC Technique

60 MHz12 bit

Q-sensitivePreamplifierPMT/APD

WireShaper

• Shaper is used to optimize signals for “slow” 60 MHz FADC• Shaping stage can only remove information from the signal• Shaping is unnecessary if FADC is “fast” enough• All operations (CFD, optimal filtering, integration) can be done digitally

• Shaper is used to optimize signals for “slow” 60 MHz FADC• Shaping stage can only remove information from the signal• Shaping is unnecessary if FADC is “fast” enough• All operations (CFD, optimal filtering, integration) can be done digitally

FADC

TDC

“Fast”12 bit

TransimpedancePreamplifier FADC

PMT/APDWire

DigitalProcessing

Amplitude

Time

BaselineRestoration


Nyquist-Shannon Theorem

If a function x(t) contains no frequencies higher than F Hertz, it is completely determined by giving its ordinates at a series of points spaced 1/(2F) seconds apart.

If a detector produces frequencies up to 500 MHz (0.6 ns rise time), all information from that detector is recorded if sampled at 1 GSPS with good enough signal-to-noise ratio


How to measure best timing?

Simulation of MCP with realistic noise and different discriminatorsSimulation of MCP with realistic noise and different discriminators

K. Byrum, H. Frisch, J.-F. Genat et al., IEEE Trans.Nucl.Sci.57, 525 (2010)


Currently available fast ADCs

• 8 bits – 3 GS/s – 1.9 W 24 Gbits/s• 10 bits – 3 GS/s – 3.6 W 30 Gbits/s• 12 bits – 3.6 GS/s – 3.9 W 43.2 Gbits/s• 14 bits – 0.4 GS/s – 2.5 W 5.6 Gbits/s

1.8 GHz!

24x1.8 Gbits/s

• Requires high-end FPGA• Complex board design• FPGA power

• Requires high-end FPGA• Complex board design• FPGA power


ADC boards

• PX1500-4: 2 Channel3 GS/s8 bits

• ADC12D1X00RB: 1 Channel 1.8 GS/s 12 bits

1-10 k€ / channel


Switched Capacitor Array

Shift RegisterClock

IN

Out

“Time stretcher” GHz MHz“Time stretcher” GHz MHz

Waveform stored

Inverter “Domino” ring chain0.2-2 ns

FADC 33 MHz


Switched Capacitor Array

• Cons• No continuous acquisition• Limited sampling depth• Nonlinear timing

• Pros• High speed (5 GHz) high resolution (11.5 bit)• High channel density (9 channels on 5x5 mm2)• Low power (10-40 mW / channel)• Low cost (~ 10€ / channel)

t t t t t

Goal: Minimize Limitations

STRAW3 TARGET

LABRADOR3

G. VarnerUniv. of Hawaii

AFTER

MATACQ

SAM

D. BretonE. DelagnesCEA Saclay

DRS1 DRS2

DRS3 DRS4

This talk


The DRS4 Chip


• CMOS process (typically 0.35 … 0.13 m) sampling speed• Number of channels, sampling depth, differential input• PLL for frequency stabilization• Input buffer or passive input• Analog output or (Wilkinson) ADC• Internal trigger• Exact design of sampling cell

Design Options

PLL

ADC

Trigger


DRS History

TemperatureDependence~kT

DRS2DRS2

I

DRS3DRS3

0.2 pF 20 pF

DRS1DRS1

Tiny signal

DRS4DRS4PLL-regulated

Sampling Speed

DSCDSC1995

2002

2004

2007

2008

Roger Schnyder, Christian Brönnimann,

Roberto Dinapoli


DRS4

• Fabricated in 0.25 m 1P5M MMC process(UMC), 5 x 5 mm2, radiation hard

• 8+1 ch. each 1024 bins,4 ch. 2048, …, 1 ch. 8192

• Passive differential inputs/outputs

• Sampling speed 700 MHz … 5 GHz

• On-chip PLL stabilization• Readout speed

30 MHz, multiplexedor in parallel

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

STOP SHIFT REGISTER

READ SHIFT REGISTER

WSROUT

CONFIG REGISTER

RSRLOAD

DENABLE

WSRIN

DWRITE

DSPEED PLLOUT

DOMINO WAVE CIRCUIT

PLL

AGND

DGND

AVDD

DVDD

DTAPREFCLKPLLLCK A0 A1 A2 A3

EN

AB

LE

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8/MUXOUT

BIASO-OFS

ROFSSROUT

RESETSRCLK

SRIN

F U N C T IO N A L B L O C K D IA G R A M

MUX

WR

ITE

SH

IFT

RE

GIS

TE

R

WR

ITE

CO

NF

IG R

EG

IST

ER

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

CHANNEL 5

CHANNEL 6

CHANNEL 7

CHANNEL 8

MUX

LVDS


12 bit resolutionW

AV

EF

OR

M [

V]

TIME [ns]0 20 40 60 80 100 120 140 160 180 200

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

11.5 bits effective resolution <8 bits effective resolution


Bandwidth

Bandwidth is determined by bond wire and internalbus resistance/capacitance:

850 MHz (QFP), 950 MHz (QFN), ??? (flip-chip)

850 MHz (-3dB)

QFP package

finalbus width

SimulationMeasurement

Ueli Hartmann

~2 nH

Bond wire Parasitic ~10 pF


Bump Bonding

Reduce input inductance by usingbump bonding instead of wire bonding

200 m

75 m


How to minimize dead time ?

• Fast analog readout: 30 ns / sample• Parallel readout• Region-of-interest

readout• Simultaneous

write / readIN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

STOP SHIFT REGISTER

READ SHIFT REGISTER

W SRO UT

CO NFIG REGISTER

RSRLO AD

DENABLE

W SRIN

DW RITE

DSPEED PLLO UT

DO MINO WAVE CIRCUIT

PLL

AGND

DG ND

AVDD

DVDD

DTAPREFCLKPLLLCK A0 A1 A2 A3

EN

AB

LE

OU T0

OU T1

OU T2

OU T3

OU T4

OU T5

OU T6

OU T7

OU T8/MUXOUT

BIASO-O FS

RO FSSROUT

RESETSRCLK

SRIN

F U N C T IO N A L B L O C K D IA G R A M

MUX

WR

ITE

SH

IFT

RE

GIS

TE

R

WR

ITE

CO

NF

IG R

EG

IST

ER

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

CHANNEL 5

CHANNEL 6

CHANNEL 7

CHANNEL 8

MUX

LVDS

AD922212 bit

8 channels


ROI readout mode

readout shift register

Triggerstop

normal trigger stop after latency

Delay

delayed trigger stop

Patent pending!

33 MHz

e.g. 100 samples @ 33 MHz 3 us dead time

300,000 events / sec.

e.g. 100 samples @ 33 MHz 3 us dead time

300,000 events / sec.


Daisy-chaining of channels

Channel 0

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

Domino Wave

1

clock

0

1

0

1

0

1

0

enableinput

enableinput

Channel 0

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

Domino Wave

1

clock

0

1

0

1

0

1

0

enableinput

enableinput

DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cellsChip daisy-chaining possible to reach virtually unlimited sampling

depth

DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cellsChip daisy-chaining possible to reach virtually unlimited sampling

depth


Simultaneous Write/Read

Channel 0

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

0

FPGA

0

0

0

0

0

0

0

1 Channel 0

Channel 11

Channel 0 readout

8-foldanalog multi-event

buffer

Channel 21

Channel 10

Expected crosstalk ~few mVExpected crosstalk ~few mV


DRS4 around the world

Shipped (-Jan 2011):2200 Chips120 Evaluation Boards

Shipped (-Jan 2011):2200 Chips120 Evaluation Boards


• MEG experiment @ PSI searches for e decay

• After ~10 years of chip design, DAQ setup, firmware programming, MEG runs with 3000 channels as designed

• 40 ps timing resolutions between all channels, running at 1.6 GS/s

• “Double buffer” readout mode increases life time to 99.7 % at 10 Hz event rate (3 MB/event)

• Took 400 TB in 2010

MEG Experiment


DRS4 @ MEG

4 x DRS4LMK03000

32 c

hann

els

3000 Channels


On-line waveform display

click

templatefit

pedestalhisto

848PMTs

“virtual oscilloscope”“virtual oscilloscope”


Crosstalk elimination

Crosstalk removal by subtracting empty channelCrosstalk removal by subtracting empty channel

Hit Hit

subtract


Template Fit

• Determine “standard” PMT pulse by averaging over many events “Template”

• Find hit in waveform• Shift (“TDC”) and scale (“ADC”)

template to hit• Minimize 2

• Compare fit with waveform• Repeat if above threshold

• Store ADC & TDC values

Experiment500 MHz sampling


Trigger and DAQ on same board

• SCA can only sample a limited (1024-bin window) many application require a wider window, trigger capability would require continuous digitization

• Using a multiplexer in DRS4, input signals can simultaneously digitized at 120 MHz and sampled in the DRS

• FPGA can make local trigger(or global one) and stop DRSupon a trigger

• DRS readout (5 GSPS)though same 8-channel FADCs

an

alo

g fro

nt e

nd

DRSFADC12 bit

65 MHz

MU

X FPGA

trigger

LVDS

SRAM

DRS4

glo

bal tr

igger

bu

s


“Slow” waveform and “Fast” window

Continuous Waveform 120 MSPS (8 ns bins)

Continuous Waveform 120 MSPS (8 ns bins)

TriggeredDRS Waveform 1 GSPS (1 ns bins)up to 5 GSPS

TriggeredDRS Waveform 1 GSPS (1 ns bins)up to 5 GSPS

Window only limited by RAM


Sine Curve Fit Method

S. Lehner, B. Keil, PSI

i

j

500

0

1024

0

22 min)))2

sin(((j i

jijj

jji of

iay

yji : i-th sample of measurement jaj fj j oj : sine wave parametersi : phase error fixed jitter

“Iterative global fit”:

•Determine rough sine wave parameters for each measurement by fit

•Determine i using all measurements where sample “i” is near zero crossing

•Make several iterations

“Iterative global fit”:

•Determine rough sine wave parameters for each measurement by fit

•Determine i using all measurements where sample “i” is near zero crossing

•Make several iterations


Fixed Pattern Jitter Results

• TDi typically ~50 ps RMS @ 5 GHz

• TIi goes up to ~600 ps

• Jitter is mostly constant over time, measured and corrected

• Residual random jitter 3-4 ps RMS

• Achievable resolution exceeds best CFD + HPTDC


Time-of-Flight PET

• Conventional electronics:CFD – TDC: 500 ps RMS

• TOF needs:•100-200 ps•>1 MHz rate

• Conventional electronics:CFD – TDC: 500 ps RMS

• TOF needs:•100-200 ps•>1 MHz rate

C. Levin, Stanford University


• Started fall 2010 after NSS/MIC in Knoxville (Siemens PET R&D home)• New project started to replace current PET electronics with DRS4 (5)• PCB ready summer 2011, firmware by Univ. Tübingen• Simulations show that SCA technique can achieve 100 ps easily

ToF-PET Project

Channel 0

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

1

FPGA

0

0

0

0

0

0

0

Channel 0

Channel 1 ROI

20 samples(10 ns @ 2 GS/s)* 30 ns / sample

= 600 ns+ 40 ns overhead

= 640 ns 1 MHz rate

20 samples(10 ns @ 2 GS/s)* 30 ns / sample

= 600 ns+ 40 ns overhead

= 640 ns 1 MHz rate

“Ping-Pong Scheme”


DRS5 Chip Ideas


Plans for DRS5

• Increase analog bandwidth ~5 GHz• Smaller input capacitance

• Increase sampling speed ~10 GS/s• Switch to 110 nm technology

• Deeper sampling depth• 8 x 4096 / chip

• Minimize readout time (“dead time free”) for muSR & ToF-PET

• (minor) reduction in analogreadout speed (30 ns 20 ns)

• Implement FIFO technology

J. Milnes, J. Howoth, Photek

~MHz event rateCTA

SR


Next Generation SCA

• Low parasitic input capacitance High bandwidth

• Large area low resistance bus, lowresistance analog switches high bandwidth

Short sampling depth

• Digitize long waveforms

• Accommodate long trigger delay

• Faster sampling speed for a given trigger latency

Deep sampling depth

How to combinebest of both worlds?

How to combinebest of both worlds?


Cascaded Switched Capacitor Arrays

shift registerinput

fast sampling stage secondary sampling stage

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

• 32 fast sampling cells (10 GSPS/110nm CMOS)

• 100 ps sample time, 3.1 ns hold time

• Hold time long enough to transfer voltage to secondary sampling stage with moderately fast buffer (300 MHz)

• Shift register gets clocked by inverter chain from fast sampling stage

• 32 fast sampling cells (10 GSPS/110nm CMOS)

• 100 ps sample time, 3.1 ns hold time

• Hold time long enough to transfer voltage to secondary sampling stage with moderately fast buffer (300 MHz)

• Shift register gets clocked by inverter chain from fast sampling stage


How noise affects timing

voltage noiseband of signal

timing jitter arising from voltage noise

timing jitter is much smallerfor fasterrise-time

voltage noise u

timing uncertainty tsignal height U

rise time tr

s

r

sr

rrr

f

t

U

u

ft

t

U

ut

nU

ut

U

ut

number of samples on slope

SNR

1


TDC vs. Waveform Digitizing

Q-sensitivePreamplifierPMT/APD

WireShaper

TDC

ConstantFraction

Discriminator

• CFD and TDC on same board crosstalk

• CFD depends on noise on single point,while waveform digitizing can average over several points

• Inverter chain is same both in TDCs and SCAs

• Can we replace TDCs by SCAs? yes if the readout rate is sufficient

• CFD and TDC on same board crosstalk

• CFD depends on noise on single point,while waveform digitizing can average over several points

• Inverter chain is same both in TDCs and SCAs

• Can we replace TDCs by SCAs? yes if the readout rate is sufficient


Typical Waveform

Only short segments of waveform need high speed readoutOnly short segments of waveform need high speed readout


Dead-time free acquisition

• Self-trigger writing of short 32-bin segments

• Simultaneous reading ofsegments

• Quasi dead time-free• Data driven readout

• Ext. ADC runs continuously• ASIC tells FPGA when there is new data

• Coarse timing from300 MHz counter

• Fine timing by waveformdigitizing and analysis in FPGA

• 20 * 20 ns = 0.4 s readout time 2 MHz sustained event rate

• Attractive replacement for CFD+TDC

coun

ter

latc

hla

tch

latc

hwrite

pointer

readpointer

digital readout

analog readout

trigger

FPGA

DRS5


Plug & Play Firmware

• Emphasis shift from dedicated hardware to firmware• Pre-designed modules for CFD, TDC, peak sensing ADC, …• Modules can be configured by user and downloaded

ADCReadout FIFO

CFD TDC

SCALER FIFO

ADC FIFO

Interface

FIFO

Data bus

Parameter bus


Conclusions

• DRS4 chip successfully used in many areas, true potential of SCA technology is just now discovered

• Planned DRS5 chip will increase BW and decrease readout dead time

• SCA technology should be able to replace most traditional electronics in particle detection


Thanks to …

• Roland Horisberger: Original Idea

• Roberto Dinapoli: Analog Design of DRS3+4

• Ueli Hartmann: DRS4 Evaluation Boards

• PSI chip design core team

Paul Scherrer Institute The PSI DRS4 Integrated Circuit Chip Stefan Ritt.

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