1

Pattern-Directed Circuit Virtual Partitioning for Test Power Reduction

Qiang Xu

The Chinese University of

Hong Kong

Dianwei Hu and Dong Xiang

Tsinghua University

Beijing, China

2

Outline

Background

Pattern-Directed Virtual Partitioning

Routing-Aware Virtual Partitioning

Experimental Results

Conclusion

3

Test Power

Toggle rate in test mode may be significantly

higher than that in functional modeExcessive accumulated power -> permanent damageExcessive instantaneous power -> test yield loss

Excessive test power is a major concern!

4

Prior Work on Test Power Reduction

Scan chain manipulation: Scan chain partitioning (e.g., Whetsel ITC’02) Scan chain reordering (e.g., Bonhomme ITC’02)

Test vector manipulation: Power-aware ATPG (e.g., Wang TCAD’98) Low-power X-filling (e.g., Butler ITC’04, Wen ITC’05)

Test vector reordering (e.g., Dabholkar TCAD’98)

Test scheduling

Circuit modification

5

Circuit Partitioning for Test Power Reduction

Tester

Data

SETCK

Glue Logic

Circuit under Testwrapper

Scan chain

Scan chain

Scan chain

P1

wrapper

Scan chain

Scan chain

P2

6

Observations and Motivation

Test patterns’ power consumptions vary significantly

Only a few “care-bits” necessary for a test pattern to

detect all the faults covered by it

Applying high-power patterns at a partitioned

subcircuit containing all their care-bits reduces test

power without fault coverage loss

7

Virtual Circuit Partitioning

High-power Patterns

Glue Logic

Circuit under Test

Scan chain

Scan chain

Scan chain

P1

Scan chain

Scan chain

P2

Low-power Patterns

8

Problem Definition

How to partition the circuit such that the

“care-bits” of as many as possible high-power

patterns belong to a single partition?

9

Design Flow

Start(with given specified patterns)

Rank test patterns based on capture power

Fault simulation

Identify care-bits for the high-power patterns

Iteratively partition the circuit

Meet constraints

End

Yes

No

10

Care-Bits Identification

Let low-power patterns detect as many faults as possible

Response care-bits: fault simulation

Stimulus care-bits: limited implication

Cost function, depends on:Care-bits selected by previous patternsComparison between different response care-

bits

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Care-Bits Identification

sa-0

11

0

1

0

1(0)

1(0)

0(1)

Response Carebits

12

Care-Bits Identification

sa-0

11

0

1

0

1(0)

1(0)

0(1)Stimuli Carebits

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Care-Bits Identification

sa-0

11

0

1

0

1(0)

1(0)

0(1)

Stimuli Carebits

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Iterative Partitioning

P1

F1

P2

F2

P3

F3

F4

High power

Lowpower

Patterns

Faults

Fault simulation

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Iterative Partitioning

P2

F2

P3

F3

F4

I1 I1, I2

R1

R2

I1R1

Patterns

Faults

High power

Lowpower

P1

F1

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Iterative Partitioning

R4

I3, I4

I1,

R1 I3, I4,R4

Patterns

Faults

P2

F2

P3

F3

F4

P1

F1

High power

Lowpower

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Iterative Partitioning

R1

I2

Patterns

Faults

P2

F2

P3

F3

F4

P1

F1

High power

Lowpower

I1,

R1 I3, I4,R4

I1,

R1,

I2

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Iterative Partitioning

R1

R1

R3

I3, I4 I2 I1, I2

Patterns

Faults

P2

F2

P3

F3

F4

P1

F1

High power

Lowpower

I3, I4,R4

I1,

R1,

I2

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Routing-Aware Partitioning

Partitioning significantly affects scan chain

routing cost

Solution: constraint-driven partitioningModel the spreadness of the scan FFsDivide the circuit layout into sub-regionsRouting either horizontally or vertically in a snake-like way

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RA-Partitioning Design Flow

Start(with given specified patterns)

Rank test patterns based on capture power

Fault simulation

Identify care-bits for the high-power patterns

Iteratively partition the circuit

Meet constraints

End

Yes

No

Iteratively partition the circuit with routing consideration

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Routing-Aware Partitioning – Cont.

(150,180)

(130,100)(80,100)

(40,40)

(0,220) (250,220)

(0,0) (250,0)

H

V

d

b c

a

5

25

+=30

45

85

+=130

CUT

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Routing-Aware Partitioning – Cont.

(150,180)

(130,100)(80,100)

(40,40)

(0,220) (250,220)

(0,0) (250,0)

H

V

d

b c

a

70

+=90

10

70

CUT

10

23

Iterative Partitioning Routing-Aware Partitioning

Experimental Result – s38417 (stuck-at)

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Experimental Result – s38584 (broadside)

Iterative Partitioning Routing-Aware Partitioning

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Power comparison for stuck-at

0

20

40

60

80

100

120

PeakVPPeakRANormal

Average power with VP: 49.13%

Average power with RA-VP: 57.67%

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Wire length comparison for stuck-at

020406080

100120140160180200

s9234 s13207 s15850 s35932 s38417 s38584 b17 b18

wi reVPwi reRANormal

Average wire length with VP: 142.52%

Average wire length with RA-VP: 109.62%

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Power comparison for broad-side

0

20

40

60

80

100

120

s9234 s13207 s15850 s35932 s38417 s38584 b17 b18

PeakVPPeakRANormal

Average power with VP: 63.59%

Average power with RA-VP: 68.28%

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Wire length comparison for broad-side

020406080

100120140160180

s9234 s13207 s15850 s35932 s38417 s38584 b17 b18

Wi reVPWi reRANormal

Average wire length with VP: 141.68%

Average wire length with RA-VP: 112.57%

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Conclusion

Excessive test power is a major concern today

We propose routing-aware circuit virtual

partitioning technique for test power reductionwithout adding test wrapperswithout fault coverage losswith small scan chain routing cost