Path to co-packaged photonic I/O for large- scale Chip-to ...

Path to co-packaged photonic I/O for large-scale Chip-to-Chip interconnect

SEMICON West 2020July 20-23, 2020

Thomas Liljeberg

Intel - Silicon Photonics Products Division

Intel silicon photonics

>3M 100G transceivers shipped -- 2M/yr run-rate

20172016 2018Launched First Product

100G PSM4 100G CWDM4 10km

100G CWDM4-OCP

100G CWDM4 2kmAward WinningFirst High Volume IntegratedSilicon Photonics Transceiver

Ramped Hyper-scale Cloud Customers

Demonstrated 400G

New 100G Transceiver for 5G Wireless Infrastructure

Expanded Portfolio

3

photonics At Silicon ScaleLaser Fabrication Silicon Integration Silicon Scale

Capable of multiple optical wavelengths and integration of multiple optical components

Advanced CMOS manufacturing at Intel fabs on 300mm wafers

Comprehensive, automated on-wafer optical, electrical, and

high-speed test capabilities

Plasma activation and bonding: InP die are bonded & transferred

in parallel to device wafer

InP substrate removal: only active epi layers remain on device wafer

Hybrid laser >90% coupling efficiency

Optical

Electrical

RF

Silicon (device) wafer Indiumphosphide

die

InP

Silicon

3

Silicon Photonics Product Division

Growth of switch bandwidth

4

12.8T

25T

50T

100T

2019 2025

Switch bandwidth 12.8TI/O 50G (x256)

Pluggable solution 32x 400G

Form factor 1RU

25.6T100G (x256)

32x 800G1RU

51.2T100G (x512)

64x 800G2RU

102.4T100G, 200G?

??

2x bandwidth / 2yrsIncreasing power overhead

Increasing SI complexity

Directional, based on Intel estimates


25.6T switch

Co-packaged optics switch

Optical switch I/O: key to network growth Problem Solution

Years for BW to double

Data centertraffic

Switch ICthroughput

SerDes I/Ospeed

2 2 3

Network BW must match data center traffic growth, but growth rates are mismatched

Impact of increasing switch I/O

Systempower

Systemdensity

Systemcost

High BW optics move close to the switch to eliminate need for retimers and reduce power

Optical switch with external laser

Conventional switch

Lasers 25.6T switch

Increasing SerDes I/O count and speed increase power and signal routing difficulty

▪ Lowest system power▪ Highly integrated lasers deliver

best density at lowest cost

▪ Front panel optical modules▪ Standardization

▪ Power savings▪ Density and serviceability

25.6T switch

Frontpanel

Opticalmodules

Retimers

5


Silicon Photonics Co-Packaged Switch

Integration for Power and Performance scaling• Lower-loss channel → lower-power I/O• No on-board retimers → lower system power and cost• Higher density• Reduced cost of photonics ($/Gbps) through integration• Reduced cost (system) through simpler systems and deployment

→ Enable bandwidth scalability: break constraint of copper and front-plate pluggable

Optical Interface

Photonic Engine

Silicon Photonics Optical

Components

Switch package

6


Enabling Technologies – Hybrid Laser

• On-chip laser vs. external “optical power supply”- Total power

- Cost

- Thermal solution

- Reliability

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LaserLaser Power Dissipation

Cost ThermalReliability /

Serviceability

On-chip 1Lowest

(wafer-scale mfg)~+10% power in

package

Requires low laserFIT

(or redundancy)

External~1.7x

Coupling loss(+5% system)

High(Laser packaging)

LowerHigher FIT, but

field serviceableIntel estimates


Enabling technologies - Silicon Photonics hybrid Laser Platform

8

MQW gain

0

5

10

15

20

25

0 20 40 60 80 100 120 140 160 180

Ou

tpu

t P

ow

er

(mW

)

Drive Current (mA)

150°C

140°C

130°C

120°C

110°C

100°C20°C 90°C80°C

1310nm

Pierre Doussiere, GROUP IV PHOTONICS, 2017

Advanced CMOS manufacturing process in Intel fabs on 300mm wafers

Hybrid laser supports wafer scale fabrication with extra flexibility for design optimization

Silicon Photonics Product Division 9

ReliabilIty of HYBRID III-V/Si wafer bonded laser

23,500 hours at 80C and 2x typical operating current

▪ Excellent long-term stability (average drift ~1%), over 2.7 years (>15 yrs @ 65C laser)

Process Qual: 231 devices / 10khrs

Accelerated test: 3000hrs corresponds to 15 yrsat 70C case temperature

Field data (laser): ~2 FIT

-50

-40

-30

-20

-10

0

10

20

30

40

50

0 5 10 15 20 25

Ibia

s ch

an

ge

(%

)

Aging time (khrs)

III-V / Si Hybrid Laser, 80C HTOL

Sample size = 30 lasers

-50-40-30-20-10

01020304050

0 2000 4000 6000 8000 10000

Ch

an

ge

in I

bia

s (%

)

Aging time (hrs)

Process qual 80C HTOL

Sample size = 231 lasers

1310nm 1310nm

R. Herrick, OFC 2019 invited talk

-30

-20

-10

0

10

20

30

40

50

0 500 1000 1500 2000 2500 3000

No

rm I

bia

s (%

)

Aging time (hrs)

Bias Increase vs. Aging Time for 150C, 150mA aging test

Silicon Photonics Product Division 10

Intel Silicon Photonics Ring Modulators

Carrier depletion ring modulators• 10um ring radius• Integrated silicon heaters for bias-point control• <20mW/pi tuning efficiency• >50GHz bandwidth• 6dB ER @ 2Vpp• Stable performance over temperature – tested error free over 80C

range and 45C/min temperature change

ER = 4.6 dBTDECQ = 1.2 dB

With FIR


16ch Integrated Silicon photonics Transmitter• Test-chip: 16-channel (1.6Tbps) PSM

transmitter PIC

• On-die integrated lasers

• 112G ring-resonator modulators

• Mode-converters and V-grooves for cost-effective HVM packaging

• Fully integrated Tx optics enables wafer-level test → KGD

• Supports redundant lasers

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• 16x channels

• 32x lasers

• 16x MZIs

• 16x Ring Modulators

• 48x GeMPDs and Heaters

• 16 mode-converters with integrated V-groove

• >30cm of WG routing

• >500 bumped pads

• 4x Temperature sensors

Key Components (DR4)

• 4x (4:1) Muxes

• 4x (1:4) Demuxes

• Multi-wavelength laser array

Additional for WDM (FR4)

2x 16-laser array16x

MRR16x2x1

Modeconv

V-groove


Enabling technologies – Packaging• On-chip spot-size converter• 0.5dB coupling loss +/-0.2dB over O-band

• 0.3dB penalty for +/- 1um alignment

• Passive alignment in etched V-grooves• Demonstrated average coupling loss ~1.1dB

• High-speed, low-loss LGA socket• Compatible with XSR channel

• Future point of standardization

• Enables testability

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integrated photonics performance

• Compact, fully integrated optical network interfaces through advanced packaging technology

• Design targets and performance compliant with applicable optical interface standards

• Photonic Integrated Circuits realized as 16-channel by 100Gbps in Intel Silicon Photonics high-volume manufacturing platform

• Scalable to 3.2Tbs and beyond

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Optical eye diagram of 8-channels of 106Gbs integrated Silicon Photonics transmitter

Integrated receiver performance at 106Gbps

1.6T photonic engine

100G pluggable module


Co-packaged Silicon Photonics + 12.8Tbps Tofino 2 Ethernet switch• Barefoot Tofino 2 12.8T P4-

programmable Ethernet switch

• Co-packaged with integrated photonic engines • Compliant with applicable

standards for I/O interfaces• Designed for 25.6T and 51.2T

switch generations• Technology platform developed

for volume manufacturability

• Live 400G Ethernet traffic enabled by fully functional switch platform with co-packaged optics ports in single switch package

• Demonstrated compliant interop with commercial ToR switch + QSFP-DD DR4 module

Switch ASIC heatsink removed to show details

Bare fiber to MTP ribbon connector panel

MTP front faceplate connectors

Electrical fly-over cables for half the ports


Market adoption

15

12.8T

25T

50T

100T

2019 2025

Switch bandwidth 12.8TI/O 50G (x256)

Pluggable solution 32x 400G

Form factor 1RU

25.6T100G (x256)

32x 800G1RU

51.2T100G (x512)

64x 800G2RU

102.4T100G or 200G?

??

Re-timers for larger systemsPower density of 800GCost and system power savings with co-packaging

Re-timers for all ports?Power: Module and total systemSignificant value of co-package ($,W)

Pluggable model brokenScale enabled by co-packaging

Pilot at 25T – learn and refineFull scale deployment at 50TUbiquitous, enabling at 100T

Directional, based on Intel estimates


summary• Ethernet switches facing scalability challenge from I/O constraints

- Increasing power overhead

- I/O port count and package escape

• Pluggable solutions can enable the next 2 generations of switches, but…- at increasing cost in terms of power and density

- Co-packaged optics at lower cost with volume

• Co-packaging of optical I/O addresses challenge with improved power, density, and cost- Core technologies required for co-packaging exist now:

Technology demonstration of Co-packaged optics + Tofino-2 Ethernet Switch- Ethernet traffic and interop with commercial switch-system and 400G-DR4 pluggable

modules

16

DCG Connectivity Group

Thank you!Intel.com/siliconphotonics

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Path to co-packaged photonic I/O for large- scale Chip-to ...

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