Path-Based Edge Activation for Dynamic Run-Time...
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Path-Based Edge Activation for Dynamic Run-Time Scheduling
Vincent J. Mooney IIIVincent J. Mooney III
Assistant ProfessorElectrical and Computer Engineering
Georgia Institute of TechnologyAtlanta, GA USA
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Outline
nn MotivationMotivationnn Previous WorkPrevious Worknn PathPath--Based Edge ActivationBased Edge Activationnn ExampleExamplenn Synthesis FlowSynthesis Flownn Experimental ResultsExperimental Resultsnn Future WorkFuture Work
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Motivation
nn Dynamic HardDynamic Hard--RealReal--Time SystemsTime Systemsnn Previous work by author limited to Previous work by author limited to DAGsDAGsnn Application examples have control flowApplication examples have control flownn Extend runExtend run--time system to handle CDFGtime system to handle CDFG
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Robotics Example: Concurrent Control Laws
singular
OholdLaw
oh3
oh2
saturatevelocity
findjacobian
matrixvectormultiply
1
10
0
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Previous Work
nn “Scheduling of Conditional Process Graphs “Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems,” for the Synthesis of Embedded Systems,” ElesEles, et. al., DATE, 1998., et. al., DATE, 1998.
nn “Hardware/Software Co“Hardware/Software Co--Design of RunDesign of Run--Time Systems,” Time Systems,” PhPh.D. thesis, Stanford, .D. thesis, Stanford, 1998.1998.
nn “Hardware/Software Co“Hardware/Software Co--Design of RunDesign of Run--Time Schedulers for RealTime Schedulers for Real--Time Systems,” Time Systems,” to appear in Design Automation of to appear in Design Automation of Embedded Systems.Embedded Systems.
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Conditional Process Graphs: Figure 4 (page 136), Processor pe2
P17P14P11P3
a) Optimal schedule of the path corresponding to D^C^K
P17P15
b) Optimal schedule of the path corresponding to D^C^K’
P17P14P3
c) Adjusted schedule of the path corresponding to D^C^K
P11
P3P11
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Conditional Process Graphs
nn Conditionals (e.g., D, C, K) are broadcast to Conditionals (e.g., D, C, K) are broadcast to all processing elementsall processing elements
nn Activation times (start times) for tasks fixed Activation times (start times) for tasks fixed based on values of conditionals (or subset of based on values of conditionals (or subset of conditionals)conditionals)
nn Focus on handling late arriving conditionalsFocus on handling late arriving conditionalsnn In case where all conditionals are ready at In case where all conditionals are ready at
the beginning, the beginning, schedule mergingschedule merging may result may result in known in known suboptimal suboptimal solutionsolution
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Previous Work (author)
RTS.v
donestart
V1donestart
RAM
CPU core1
memory controller
CPU Interfaceint64
startdone Vn
donestart
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Task Control
nnAssociate Associate startstart and and done done event with each taskevent with each tasknnControl of hardware tasksControl of hardware tasksuu startstart signal (bit)signal (bit)uudonedone signal (bit)signal (bit)
nnControl of software tasksControl of software tasksuu startstart vector encapsulates allvector encapsulates all swsw start start eventseventsuudonedone vector encapsulates allvector encapsulates all swsw donedone eventsevents
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Run Time Scheduler ImplementationnnStart with control flow ofStart with control flow of hwhw-- andand swsw--taskstasksnnHardware implementation:Hardware implementation:uu put FSM corresponding to the control flowput FSM corresponding to the control flowtt cycle based semanticscycle based semanticstt can predictably satisfy hard realcan predictably satisfy hard real--time constraintstime constraints
nnSoftware implementation:Software implementation:uu preemptive static priority schedulerpreemptive static priority schedulertt can execute different threadscan execute different threadstt keeps track of which threads are suspendedkeeps track of which threads are suspended
uudirect execution of software tasks by ISRdirect execution of software tasks by ISRtt all all sw sw tasks run to completion (no suspension)tasks run to completion (no suspension)
nnMixed implementation can leverage advantage of Mixed implementation can leverage advantage of hardware and softwarehardware and software
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src
oh0
mvm2
cjd
cg
snk
oh1fk
mvm3
mvm4
mvm1
x3k f3(t3,x3k)
t3 oh1,snk cjd,snk f3*(t3,x3k) x3k*
oh0 24,020 24,020 oh1,snk
oh1 43,812 43,812 cjd,snk
cjd 35,012 35,012 oh1,snk
∞∞
∞
X2* = {(oh0,oh1,snk),(oh1,cjd,snk),(cjd,oh1,snk)}
Constructive Heuristic on DAG
NEVER = {oh0,oh1,cjd}
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src
oh0
mvm2
cjd
cg
snk
oh1fk
mvm3
mvm4
mvm1
Final Result:--------------------oh0 -- priority 1cjd -- priority 2oh1 -- priority 3
WCET: 39,012
Constructive Heuristic Scheduling Algorithm:
Result
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Path-Based Edge Activation
nn Extend scheduling to handle CDFG, not just DAGExtend scheduling to handle CDFG, not just DAGnn Conditional edgesConditional edgesuu active only if a particular path chosenactive only if a particular path chosenuu a path is defined by a set of values of conditional a path is defined by a set of values of conditional
choices in the CDFGchoices in the CDFGnn For each path, insert conditional edges to minimize For each path, insert conditional edges to minimize
WCETWCETuu assumption: conditional values evaluated early assumption: conditional values evaluated early
enough for all conditional edge insertionsenough for all conditional edge insertions
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src
oh0
cg
cjd
mvm
snk
oh1
fk
task hw/sw wcet(cycles)----- ---------- ---------------cg hw 11,000 oh0 sw 2,554 oh1 sw 20,581 fk hw 11,500cjd sw 14,878 mvm hw 4,400
NEVER = {oh0, oh1, cjd}
c=1c=1 c=0
c=0
No static order can achieve better than a WCET of 49,013
Example
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Centralized Control
nn Done signals arrive to hardware runDone signals arrive to hardware run--time time scheduler (no broadcast)scheduler (no broadcast)
nn Dynamic ordering of software tasks must be Dynamic ordering of software tasks must be done by hardware rundone by hardware run--time schedulertime scheduler
nn Use Use hardwarehardware--driven software executiondriven software executionnn ISR executes a software taskISR executes a software taskuu advadv.: fast.: fastuudisadvdisadv.: software tasks not .: software tasks not interruptableinterruptable
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Scheduling AssumptionsnnA CDFG represents the set of tasksA CDFG represents the set of tasksuu limited number of pathslimited number of paths
nnOne rate constraint for the graphOne rate constraint for the graphnnA NEVER set specifies mutually exclusiveA NEVER set specifies mutually exclusive swsw--taskstasksnnEachEach swsw--task, once started, runs to completiontask, once started, runs to completionuu limits solution spacelimits solution space
nnHwHw--swsw communication accounted forcommunication accounted foruu in task WCETin task WCETuu as a separate taskas a separate task
nn Interrupts come only from theInterrupts come only from the hwhw runrun--timetime schedsched..
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src
oh0
cg
cjd
mvm
snk
oh1
fk
c=1c=1 c=0
c=0
c=0c=1
c=1
CDFG
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src
oh0
cg
cjd
mvm
snk
oh1
fk
c=1c=1 c=0
c=0
c=0c=1
c=1
src
oh0
cjd
mvm
snk
oh1
fk
c=1c=1
c=1
c=1
case: c=1 CDFG
WCET = 38,013
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src
oh0
cg
cjd
mvm
snk
oh1
fk
c=1c=1 c=0
c=0
c=0c=1
c=1
src
oh0
cg
cjd
mvm
snk
oh1 c=0c=0
c=0
CDFG case: c=0
WCET = 39,859
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src
oh0
cg
cjd
mvm
snk
oh1
fk
c=1c=1 c=0
c=0
c=0c=1
c=1
WCET of 39,859 achievable with dynamic order
case: c=1 CDFG case: c=0
src
oh0
cjd
mvm
snk
oh1
fk
c=1c=1
c=1
c=1
src
oh0
cg
cjd
mvm
snk
oh1 c=0c=0
c=0
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Algorithm
Solve_order(CDFG,NEVER)beginmoduleforeach path determined by a unique set of conditional valuesbeginDAG = subset of CDFG determined by pathSchedule DAG using constructive heuristic schedulingAdd conditional edges to enforce DAG schedule
endendmodule
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Tool Flow
behavioral VerilogC
constraints
Fifos,RAM,etc.
Mp core,RAM size,
etc.
RTS.c *.c
RAMRTS.vV1
behavioral Verilog RTL Verilog
BC DCBC
System Specification
Interface Generation Serra2 Run-TimeScheduler Synthesis
InterfaceVn
wcet
Cinderella-Mwcet
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SERRA2 Run-Time Scheduler Synthesis Tool
constraints behavioral Verilog C
relocatable assembly
RTS assembly code
cfe
cdfg
RTS control FSMin RTL Verilog
sw-tasksassembly code
Thalia2
DiegoGCC
linker
dataflow analysis
Key:= data= tool= tool
Clara2ISR template
Cind-Mwcet
BC
wcet
System Specification
conditionaledges
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Example and Experimental Results
nnHwHw--tasks tasks written inwritten inVerilogVerilog for for BC, use LSI BC, use LSI 10K library10K librarynnVerilogVerilog model model
of MIPS core of MIPS core with interruptswith interruptsnn19% decrease 19% decrease
in WCET: in WCET: 39859 (49013)39859 (49013)nnUsed VCSUsed VCSTMTM
to verify resultto verify result
Softwa reTask
# Line sof C
# Line sAsmbly
WCET
cjd 286 1177 14878oh0 90 237 2554oh1 693 3263 20581int-se r-rtn N/A 26 20
Hw-task # Lines V Area WCETmvm 629 33645 4400fk 2362 42168 11500cg 2897 59587 11000rtsched-hw 484 413 99701
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Future Work
nn Extend to handle late arriving conditionalsExtend to handle late arriving conditionalsnn Extend to allow Extend to allow interruptable interruptable software taskssoftware tasks