Partha Kundu
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Partha Kundu Sr. Distinguished Engineer, Office of the CTO at Juniper Networks [email protected] Summary Partha Kundu is currently working on next generation data center architectures. Previously, Partha was a senior architect within Intel Labs in California working on Tera-Scale technologies related to many core CPUs. He joined Intel in 1990 and was a designer of the first super-scalar x86 processor, the Pentium chip. Partha contributed to the development of the Intel Itanium instruction-set architecture (ISA) in 1993-94 and thereafter served as an architect and design manager of the first Itanium based machine (1994 - 96). He was a Principal Architect of the DEC/Alpha EV8 microprocessor (1996-2001), and developed the memory system architecture. He is recognized as one of the earliest contributors to the field of on-chip interconnects in multi-core CPUs, giving an invited talk at the first 2006 NSF workshop on chip interconnects at Stanford University. Partha served as General Chair of the 3rd IEEE/ACM Networks on Chip Symposium, held at San Diego in May 2009. He was co-editor of the September/October 2007 IEEE Micro special edition on interconnects. He has participated in numerous panels, tutorials and workshops at ESWEEK, DATE, DAC and the Intel Developers Forum. Specialties: Large scale interconnection fabric design & architecture On Chip Interconnects for multi-core processors Transaction Memory & architecture support for parallel programming on multi-core CPUs Multi-Processor cache design Database and server/Parallel workload characterization Performance modeling High performance CPU and logic design Experience Sr. Distinguished Engineer, Architect at Juniper Networks February 2010 - Present (4 years 10 months) Switch and fabric architecture for next generation data centers Architect/Researcher at Intel Corp 2002 - March 2010 (8 years) * Developed high performance, low power on-chip interconnection network for many core high performance CPUs * Developed (earliest published) hardware support to accelerate Transaction Memory (Hybrid TM) * Cache and memory bandwidth management scheme for many core CPUs Page1
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Transcript of Partha Kundu
Partha KunduSr. Distinguished Engineer, Office of the CTO at Juniper Networks
SummaryPartha Kundu is currently working on next generation data center architectures.
Previously, Partha was a senior architect within Intel Labs in California working on Tera-Scale technologies
related to many core CPUs. He joined Intel in 1990 and was a designer of the first super-scalar x86 processor,
the Pentium chip. Partha contributed to the development of the Intel Itanium instruction-set architecture (ISA)
in 1993-94 and thereafter served as an architect and design manager of the first Itanium based machine (1994 -
96). He was a Principal Architect of the DEC/Alpha EV8 microprocessor (1996-2001), and developed the
memory system architecture.
He is recognized as one of the earliest contributors to the field of on-chip interconnects in multi-core CPUs,
giving an invited talk at the first 2006 NSF workshop on chip interconnects at Stanford University. Partha
served as General Chair of the 3rd IEEE/ACM Networks on Chip Symposium, held at San Diego in May 2009.
He was co-editor of the September/October 2007 IEEE Micro special edition on interconnects.
He has participated in numerous panels, tutorials and workshops at ESWEEK, DATE, DAC and the Intel
Developers Forum.
Specialties:
Large scale interconnection fabric design & architecture
On Chip Interconnects for multi-core processors
Transaction Memory & architecture support for parallel programming on multi-core CPUs
Multi-Processor cache design
Database and server/Parallel workload characterization
Performance modeling
High performance CPU and logic design
ExperienceSr. Distinguished Engineer, Architect at Juniper NetworksFebruary 2010 - Present (4 years 10 months)
Switch and fabric architecture for next generation data centers
Architect/Researcher at Intel Corp2002 - March 2010 (8 years)
* Developed high performance, low power on-chip interconnection network for many core high performance
CPUs
* Developed (earliest published) hardware support to accelerate Transaction Memory (Hybrid TM)
* Cache and memory bandwidth management scheme for many core CPUs
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* Database workload characterization
Consulting Engineer, Architect at Digital Equipment Corporation/Compaq1996 - 2001 (5 years)
Principal Architect (memory system) of (EV8) Alpha micro-processor
Architect & Design Engineering manager at Intel Corp1990 - 1996 (6 years)
* Design manager for first Itanium microprocessor
* Architect of Itanium Instruction Set Architecture (ISA)
* Principal micro-architect (Bus system) of Itanium microprocessor
* Design engineer on first Pentium(tm) microprocessor
Hardware Engineer at AMI1987 - 1990 (3 years)
ASIC designer
PublicationsCurbing energy cravings in networks: A cross-sectional view across the micro-macro boundaryNOCS 2011: 241-246 May 2011
Authors: Amlan Ganguly, Partha Kundu, Pradip Bose
Toward Ideal On-Chip Communication Using Express Virtual ChannelsIEEE Micro January 2008
Authors: Amit Kumar, Li-Shiuan Peh, Partha Kundu, Niraj Jha
A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOSICCD 2007
Authors: Amit Kumar, Partha Kundu, Arvind Pratap Singh, Li-Shiuan Peh, Niraj Jha
Express virtual channels: towards the ideal interconnection fabricISCA 2007
Authors: Amit Kumar, Li-Shiuan Peh, Partha Kundu, Niraj Jha
Hybrid transactional memoryPPOPP 2006
Authors: Sanjeev Kumar, Michael Chu, Christopher Hughes, Partha Kundu, Anthony Nguyen
A case for shared instruction cache on chip multiprocessors running OLTPSIGARCH Computer Architecture News 2004
Authors: Partha Kundu, Murali Annavaram, Trung Diep, John Shen
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Skills & ExpertisePerformance EngineeringInterconnectComputer ArchitectureMicroprocessorsMicroarchitectureProcessorsSoCLogic DesignASICVerilogRTL designVLSIEmbedded SystemsHigh Performance ComputingHardware ArchitectureLow-power DesignSemiconductorsEDAX86Digital Signal ProcessorsICSoftware IndustryIntegrated Circuit DesignCircuit DesignSystem ArchitectureIntelHardwareFPGASystemVerilogDebuggingParallel Programming
PatentsMethod and apparatus for register stack implementation using micro-operationsUnited States Patent Application 20050102494
Inventors: Partha Kundu
Method and apparatus to reduce spill and fill overhead in a processor with a register backing storeUnited States Patent Application 20050138340
Inventors: Partha Kundu
Method and system to provide user-level multithreadingUnited States Patent 20050223199
Inventors: Partha Kundu
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Express Virtual Channels in a packet switched on-chip interconnection networkUnited States Patent 8,223,650
Inventors: Partha Kundu, Amit Kumar
Technique to improve network switch throughputUnited States Patent 7,773,626
Inventors: Partha Kundu, Amit Kumar
Hybrid hardware and software implementation of transactional memory accessUnited States Patent 7,856,537
Inventors: Partha Kundu, Sanjeev Kumar, Chris Hughes
Scatter-gather intelligent memory architecture for unstructured streaming data on multiprocessorsystemsUnited States Patent 8,578,097
Inventors: Partha Kundu, Daehyun Kim, Chris Hughes, Yen-Kuang Chen
EducationState University of New York at Stony BrookMS, Electrical Engineering, 1985 - 1987
Birla Institute of Technology and Science, Pilani, IndiaBachelor of Engineering (BE), EEE
St Columba's High School, N Delhi, India
Honors and AwardsGeneral Chair of IEEE/ACM NOCS 2009 http://circuit.ucsd.edu/~nocs2009/
co-Guest Editor (with Peh (MIT)) IEEE Micro, Special Issue on Interconnects for
Multi-Core Chips, September/October 2007 (Editor-in-Chief: Albonesi (Cornell)
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Partha KunduSr. Distinguished Engineer, Office of the CTO at Juniper Networks
Contact Partha on LinkedIn
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