part2-2.ppt

Section 2: Processing UnitSection 2: Processing Unit

Embedded Real-Time Systems 2

OverviewOverview

• Microprocessor/Microcontrollers

• Digital Signal Processing Processor

• DSP Cores

• Time Processing Units


Good System in General?Good System in General?

• Fast Inexpensive Reliable Low Power (Portable)• Quiet• Light (Portable) Durable Small• Expandable• Software compatibility


Today’s Embedded ProcessorsToday’s Embedded Processors

[Retargetable Compilers for Embedded Core Processor by C. Liem]


Microprocessors & MicrocontrollerMicroprocessors & Microcontroller

• Originally designed for general purpose computing• Microcontroller = One-chip solution

– CPU– RAM– EPROM/ROM– Serial & parallel I/O– Timers and various controllers

• Advantage– Flexible, verified, off-the-shelf

• Popular microcontroller/microprocessors– Motorola 6800/68000 series (6805, 68hc11, 683xx)– Intel 80xx/80x86 series (8051, 80?86, i960)– TMS370 (TI), COP series (Nat’l Semiconductor) etc.


Instruction ArchitectureInstruction Architecture

• RISC (e.g. MIPS)– simple instruction format

• e.g. MIPS: I,J,R type

– small instruction set

– regular instruction timing• easy for pipelining

– large register file

– load/store architecture

– overall simple architecture

• VLIW

• Superscaler

• CISC (e.g. 68000)– variable instruction format

– various instruction size

– data dependent decoding

– irregular instruction timing

– many addressing modes

• SISC (ASIP)– Specific Instruction Set

computer

• Harvard Architecture– separate data/instruction

bus


DSP ProcessorDSP Processor

[DSP Processor Fundamentals by Lapsley etc.]


DSP Processors: Typical ApplicationDSP Processors: Typical Application



Common Features of DSP ProcessorsCommon Features of DSP Processors



Commercial DSP ProcessorsCommercial DSP Processors



DSP Cores (ASICs)DSP Cores (ASICs)



Common Features of DSP coresCommon Features of DSP cores

• Performs dedicated function• Very strict real-time requirement• Correctness is essential due to the impact on the

surrounding environment


Commercial DSP CoresCommercial DSP Cores


Timer Application in Embedded SystemsTimer Application in Embedded Systems

• Real-Time clock– generates an interrupt at periodic intervals– used by OS to switch between tasks– update a record of the time of day

• Square-Wave Generator

• Interrupt after Timeout– watchdog timer

• Elapsed Time Measurement


68332 Time Processing Unit68332 Time Processing Unit

• An intelligent, semi-autonomous micro-controller designed for timing control

• Functions– Schedules tasks (Scheduler, 3 priorities)

– Processes ROM instructions (Control Store for built-in functions)– Accesses shared data w/ the CPU (Control Reg, and Para. Ram)

– Performs input and output

• Features– 16 independent, programmable, orthogonal channels

– Interchannel communication– 2 prescaler registers (System-clock or external clock time base)– Many factory programmed time functions

– Programmable channel priority– Emulation support


TPU Block DiagramTPU Block Diagram

prescaler

Select/Initialize channel/function

Priority-based (H/M/L) schedule

Microprogram for built-in function

Inte

rmod

ule

Bus


Built-in Functions Built-in Functions

• Period/Pulse-Width Accumulator• Output Compare• Input Capture/Input Transition Count• Discrete Input/Output (16 bit)• Pulse Width Modulation• Period Measurement • Stepper Motor Control• and more...

Section 3: MemorySection 3: Memory


OverviewOverview

• Taxonomy

• SRAM vs. DRAM

• ROM, EPROM, EEPROM, and FLASH Memory


Memory TaxonomyMemory Taxonomy

• RAM vs. ROM– READ/WRITE Random Access Memory: SRAM, DRAM– (Programmable) Read Only Memory: ROM, EPROM,

EEPROM

• Static vs. Dynamic– Static: SRAM, PROM– Dynamic: DRAM

• Synchronous vs. Asynchronous– SRAM: Writeback vs. Pipeline Burst or Synchronous Burst– DRAM: FPM or EDO vs. SDRAM

• Volatile vs. Nonvolatile– Volatile: Normal RAMs– Nonvolatile: ROM, EPROM, Battery-backed CMOS


SRAM - 6T designSRAM - 6T design

Read: Data/Data* precharged to Vcc

Assert Row Address

Write: Place data on Data/Data* Assert Row Address

Complimentary design: very little static power consumption

6 transistor for 1 bit ofinformation

Flip/Flop


Static RAMStatic RAM

• 6T design (vs. 4T design)– Pros

• high speed• low Power• better noise immunity

– Cons• larger area

• Synchronous (vs. Async)– high performance

– synchronous burst

– pipeline burst

• Nonvolatile– battery backed-up

– CMOS (BIOS) memory


SRAM vs. DRAMSRAM vs. DRAM

• SRAM– <10ns– cache/CMOS – 4T/6T– 4 x larger than DRAM– volatile or nonvolatile– asynchronous or synchronous

• Async: WB, WT• Sync: Sync. Burst, PB

– Packaging• On-Chip or DIP

– Typical (cache) size• Internal: 16KB+16KB (or 32K)• External: 256-512KB

– Simple interface (easier to use)– 10 x more expensive than

DRAM

• DRAM– 60ns-80ns

– main memory

– 1T & 1C/3T

– requires refresh logic

– row/column multiplexed access

– volatile

– asynchronous or synchronous• Async: EDO, FPM, BEDO• Sync: SDRAM

– Packaging• SIMM, SIPP, DIMM

– Typical size• 32-64MB• upto 1GB

– Very complex interface


RAM ConfigurationRAM Configuration

NxM (N: # of locations, M: # of bits per location)

1Mx16-bit memory organization w/ 1Mx8-bit chips


RAM Configuration (cont’d)RAM Configuration (cont’d)

4M

-wo

rdsx

16

-bits

w/ 4

Mx1

ch

ips

4M

-wo

rdsx

16

-bits

w/ 5

12

Kx8

ch

ips


CMOS MemoryCMOS Memory

• CMOS (Complementary MOS)– Normal implementation technology of today’s memory– Main advantage: low power (very small static power

dissipation)– Most power consumption: dynamic power consumption

• dynamic power: (C: capacitance, f:switching, V: power supply)

– Small static power consumption makes it possible to operate CMOS memory from small batteries when the main power is off.

• Standby mode– Power consumption: 0.1 mW (200mW for active R/W)– Vcc is reduced (from 5V) to no less than 2.0V & proper CS

control

1

22CV f


EPROM (Erasable & Programmable EPROM (Erasable & Programmable ROM)ROM)

• Non-volatile• Can be programmed and reprogrammed by user• Invariably byte-organized (Nx8)• Mainly found in

– embedded system where firmware is held.– palmtop where OS and system software are held– bootstrap loader

floating gate


EPROM (cont’d)EPROM (cont’d)

• Characteristics– floating gate: enables non-volatility– UV-light exposure for erasing (several min)– Re-programming takes about 5-10 sec/word (EPROM

programmer) w/ Vpp=10-20V

– Access time: about 100ns– Low cost and small cell size (20 m2 at the 1-Mbit)– Low endurance: maximum of 1000 erase/program cycle– Reliability Issue: device thresholds might vary w/ repeated

reprogramming– In summary, extremely simple, and dense. making it

possible to fabricate large memory at a low cost (but w/o regular reprogramming)

G

D

S


EEPROMEEPROM

• Electrical Erasure procedure

• FLOTOX (Floating-gate tunneling oxide): a modified FG– Reduced gap between floating gate and channel/drain from 100nm

(EPROM) to 10-20nm

• Fowler-Nordheim tunneling– When a voltage of approximately 10V is applied over the thin

insulator, electrons travel to and from the floating gate by a mechanism called Fowler-Nordheim tunneling.

• Reversible process– Erasing is simply achieved by reversing the voltage applied during

the writing process.

– may pose the problem of threshold control

• Cons: Larger, high expense, difficult fabrication than EPROM

• Pros: Versatile (105 erase/write cycles)


Flash EEPROMFlash EEPROM

• Technically, a combination of EPROM & EEPROM– Programming: avalanche hot-electron-injection– Erasure: Fowler-Nordheim tunneling– Difference

• erasure is performed in bulk for the complete chip, or for a subsection of the memory - removal of extra transistor in EEPROM

• Simpler cell structure, smaller cell size, high integration density

• Programming & Erasure: 12V internally generated


EPROM vs. EEPROM vs. Flash EEPROMEPROM vs. EEPROM vs. Flash EEPROM

[Jan Rabaey: Digital Integrated Circuits]

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