Low cost VLSI design of the LDPC decoder in Advanced Broadcasting

System for Satellite

Jianing Su1*, Zhenghao Lu

2

1Advanced Circuit and System Lab, Suzhou Institute of Nano-tech and Nano-Bionics, Chinese Academy of

Sciences, Suzhou, Jiangsu, 215123, China 2 Department of Electronics and Information Science, Soochow University, Suzhou, Jiangsu, 215006, China

* Email: jnsu2011@sinano.ac.cn

Abstract

In this paper, a low cost VLSI implementation of an

LDPC decoder for the Advanced Broadcasting System of

Satellite (ABS-S) is presented. The decoder is fully

compatible with all the 8 code rates in ABS-S standard.

The layered decoding with sorted scheduling architecture is employed and the scaled min-sum belief propagation

method is used for check node update. The CRC check is

embedded into the decoding process to gain the best

early stopping effect in decoding iterations. The decoder

is implemented in Altera FPGA and results show that the

proposed decoder is suitable for satellite broadcasting

application ABS-S and its scheme can be generalized in

other quasi-cyclic structured LDPC codes.

Index terms

Advanced Broadcasting System of Satellite (ABS-S),

layered decoding with sorted scheduling, early stopping

criteria

1. Introduction

The error correction codes play a major role in wireless communications to increase the transmission reliability

and achieve a better performance with less SNR. The

LDPC codes have been proved to be an outstanding type

of error correction code and received much attention due

to its superior performance. Many applications and

standards (wired, wireless, broadcasting) have adopted

LDPC as forward error correction codes.

In wireless applications, both wimax-802.16e [1] and WIFI-802.11n [2] adopt LDPC as an optional coding

scheme, featuring a medium code length and throughput

in the range 40Mbps-340Mbps.

LDPC codes are also used in the second generation of

digital video broadcasting standards, first by satellite in

2003 (DVB-S2), recently by terrestrial (DVB-T2) and

cable (DVB-C2), featuring a long code length of 64800

bits and a throughput of about 20Mbps~135Mbps. China releases its own Advanced Broadcasting System

of Satellite (ABS-S) [3] in 2008. The ABS-S standard

uses the LDPC codes with a fixed length of 15360 bits

and up to 8 different code rates. The LDPC codeword

structure and code rate information are listed in figure 1

and Table 1.

PayloadCRC

32bits

LDPC

Check bits

Kldpc_bits

Nldpc_bits = 15360

Figure 1. LDPC codeword structure in ABS-S

Table 1. Code rates of LDPC in ABS-S

Code-rate Kldpc_bits Nldpc_bits

1/2 7680 15360

3/5 9216 15360

2/3 10240 15360

3/4 11520 15360

4/5 12288 15360

5/6 12800 15360

13/15 13312 15360

9/10 13824 15360

The paper presents an efficient architecture of the LDPC

decoder in ABS-S standard, the remainder parts are

arranged as follows: section 2 describes the layered decoding algorithm and the proposed sorted scheduling;

section 3 describes the early stopping criteria with CRC

check; section 4 is the implementation results and the

conclusion is drawn in section 5.

2. Normalized Min-Sum Layered Decoding and the

Sorted Scheduling

The LDPC codes in ABS-S are a kind of typical quasi –cyclic (QC) LDPC, which is suitable for supporting

multi- code rates and hardware implementation.

2.1 LDPC Code structure in ABS-S

The LDPC codes in ABS-S are QC-LDPC codes with a

parity check matrix composed of basic sub-matrices of

size 32×32, each sub-matrix is cyclic-shift identity

matrix. The diagram of parity matrix for rate-3/4 code is

shown in figure 2. The QC structure is fitted for compact

memory storage and the layered decoding procedure.

2.2 Normalized min-sum layered decoding

The essence of layered decoding [4-6] is using the most

updated bit LLR for check node evaluation in next layer.

978-1-4673-2475-5/12/$31.00 ©2012 IEEE

32

32

32×480

32

×1

20

layer1

layer2

layer120

Figure 2. Sketch diagram of Rate-3/4 LDPC codes

Let )(

,

n

imjLr denote the message passing from check

node j to bit node i after mth layer’s operation in the nth

iteration; )(

,

n

jmiLq denote the message passing from

bit node i to check node j after mth layer’s operation in

the nth iteration; )(

,

n

miLq denote the posterior LLR of bit

node i after mth layer’s operation in the nth iteration. The

layered decoding algorithm goes as follows:

(1) Initialization: )(

,

n

miLq = intrinsic message, m=1, n=1

(2) bit node update before the mth layer’s operation: )1(

,

)(

,

)(

,

n

imj

n

mi

n

jmi LrLqLq

(3) check node update in the mth layer:

kLqLqsignLr n

jmiRi

n

jmiRi

n

imjijij

|)(|min)( )(

,''

)(

,''

)(

,\\

(4) bit node update after the mth layer’s operation: )(

,

)(

,

)(

1,

n

jmi

n

imj

n

mi LqLrLq

)( )1(

,

)(

,

)(

,

n

imj

n

imj

n

mi LrLrLq

(5) Hard decision if all the layers are processed:

1:0?)0( )(

, iiLq n

mi

(6) Terminate if n exceeds limit or all the checks are

satisfied, otherwise goto (2) and n=n+1

Figure 3 gives an example of how the LLR message

updates between layers in a decode iteration.

i

j0

j1

j2

a:

b:

a:

b:

a:

b:

)1(

0,

)(

0,

)(

0,

n

ij

n

i

n

ji LrLqLq

)( )1(

0,

)(

0,

)(

0,

)(

1,

n

ij

n

ij

n

i

n

i LrLrLqLq

)1(

1,

)(

1,

)(

1,

n

ij

n

i

n

ji LrLqLq

)( )1(

1,

)(

1,

)(

1,

)(

2,

n

ij

n

ij

n

i

n

i LrLrLqLq

)1(

2,

)(

2,

)(

2,

n

ij

n

i

n

ji LrLqLq

)( )1(

2,

)(

2,

)(

2,

)(

3,

n

ij

n

ij

n

i

n

i LrLrLqLq

m=m+1

m=m+1

Figure 3. Example of LLR updates between layers

The check node processer used in layered decoding is a

kind of Soft-In-Soft-Out (SISO) structure as in figure 4.

Min-sum*k

Π: C→V

Π: V→ C

─)(

,

n

miLq

)1(

,

n

imjLr

)(

,

n

jmiLq )(

1,

n

miLq

)(

,

n

imjLr

Figure 4. Structure of the SISO check node processer

2.3 The Sorted Scheduling

The normal layered decoding goes through the layers in

the parity matrix from top to bottom without special

treatment. Here a sorted scheduling method is proposed:

(1) Process the layers from top to bottom in the 1st

iteration, (layer 1, layer 2, …, layer n).

(2) Calculate number of failed check equations in each

layer, sort them from most to least.

(3) Process firstly the layer with least failed check

equations, then the 2nd least, and so on, process the

layer with most failed checks lastly.

This sorted scheduling method ensures that the most

uncertain bits always get the most updated extrinsic

information. It averagely reduces the iteration number by

0.5~1.

3. CRC aided iteration stopping criteria

The LDPC codes in ABS-S are irregular, and the bits in

the parity check part are less protected than the payload

ones, which leads to one consequence that in the last few

iterations, most of the errors are located in the parity

parts and only a few errors are in the payload section.

This reminds us that in the last few iterations, the CRC

check can be activated and once the payload bits pass the CRC check, decoding process can be stopped even if

there are still failed parity checks.

Calculate Failed

parity check

Nfail_check

Normal decoding

iteration

Nfail_check < T

Activate

Payload bits

CRC

CRC pass?

Decoding

Iteration

Ends

Y

N

Y

N

Figure 5. The decoding Process with CRC check

The decoding with CRC aided stopping process is shown

in figure 5. Please be noted that the CRC check should be activated only when number of failed checks is lower

Min-sum*k)(

,

n

miLq

)1(

,

n

imjLr )(

,

n

jmiLq )(

1,

n

miLq

)(

,

n

imjLr

Extrinsic

Memory

check-node

Π:

V→C

Π:

C→VMin-sum*k)(

,

n

miLq

)1(

,

n

imjLr )(

,

n

jmiLq )(

1,

n

miLq

)(

,

n

imjLr

Extrinsic

Memory

check-node

Π:

V→C

Π:

C→VMin-sum*k)(

,

n

miLq

)1(

,

n

imjLr )(

,

n

jmiLq )(

1,

n

miLq

)(

,

n

imjLr

Posterior LLR

Memory

bit-node

Extrinsic

Memory

check-node

Π:

V→C

Π:

C→V

main

control

Address

rom

Figure 6. Proposed LDPC decoder architecture

than a certain threshold. When threshold T is 50, some

simulation results are listed in Table 2.

Table 2 The iterations in AWGN simulation

Modu Code

rate

Eb/No

(db)

LDPC

Frames

(15600)

Total Iterations Without

Special

treat

Sorted

scheduling

+ CRC aided

stopping

QPSK 3/4 4.2 1000 10271 9267

QPSK 3/4 4.3 1000 8558 7881

8PSK 3/4 8.2 1000 9658 8914

8PSK 3/4 8.3 1000 8022 7287

It can be seen from Table 2 that the proposed technique

sorted scheduling and CRC aided stopping can reduce

the whole number of iterations by 8%-10% which is

helpful to reduce the power dissipation.

4. Implementation results

The whole LDPC decoder is implemented in Altera

FPGA with target device Stratix III EP3SL340F1760. The decoder structure is shown in figure 6, which

supports all 8 code rates in ABS-S. The main clock of

the LDPC is 135 Mhz and there are 32 SISO check node

processing units work in parallel. There are mainly two

banks of memories, one for storing the LLR messages of

each bit and the other stores the extrinsic information of

every check node in iteration. The proposed sorted

scheduling and the CRC aided stopping criteria are handled in the main controller unit. The FPGA resources

usage is listed in Table 3.

Table 3. FPGA resource usage

Quartus Ver. 11.0 Build Full Version

Family Stratix III

Device EP3SL340F1760

Timing Model Preliminary

Total ALUs 54538/143520 (38%)

Total registers 10379

Total Pins 62/1171 (5.3%)

Total memorys 2009424/9383040 (22%)

DSP Blocks 0/768 (0%)

5. Conclusions An LDPC decoder scheme full compatible with ABS-S

standard is presented and the scheme is implemented on

Altera FPGA. Layered decoding structure is employed

and the scaled min-sum algorithm is used for check node

update. The sorted scheduling and the CRC aided

stopping criteria is proposed and integrated into the main

controller, which can reduce total number of iterations

by 8%-10%.

Acknowledgments

This work is supported by National Natural Science

Foundation of China under Grant Number: 6090617

References

[1] IEEE 802.16e. Air interface for fixed and mobile

broadband wireless access systems, draft, oct 2005

[2] IEEE 802.11n. Wireless LAN MAC and physical

layer specifications: P802.11n/d3.07, March 2008.

[3] Framing Structure, Channel Coding and Modulation

for Advanced Broadcasting System-Satellite(ABS-S),

draft, 2008

[4] Jeongseok Ha, “Layered BP decoding for rate

compatible punctured LDPC codes”, IEEE Comm.

Letters, Vol.11, No.5, pp 440-442, May 2007

[5] Zhiqiang Cui, “High Throughput Layered LDPC

decoding Architecture”, IEEE Trans on VLSI,

Vol.17, No.4, pp 582-587

[6] Kai Zhang, “A High Throughput LDPC Decoder

Architecture with Rate Compatibility”, IEEE Trans

on Circuits & Systems, Vol.58, No.4, pp 839-847.