Paper-2 High-Speed 64-Bit Binary Comparator using Different Logic Styles

7/28/2019 Paper-2 High-Speed 64-Bit Binary Comparator using Different Logic Styles

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International Journal of Computational Intelligence and Information Security, March 2013, Vol. 4 No. 3,ISSN: 1837-7823

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High-Speed 64-Bit Binary Comparator using Different Logic Styles

Anjuli (Student Member IEEE) and Satyajit AnandE&CE Department, FET-MITS, Lakshmangarh, Sikar, Rajasthan (India)

AbstractHigh-speed 64-bit binary comparator using different logic styles is proposed in this brief. Comparison is most

basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number.Comparator is most fundamental component that performs comparison operation. This brief presents comparisonof modified and existing 64-bit binary comparator designs concentrating on delay. Means some modificationshave been done in existing 64-bit binary comparator design to improve the speed of the circuit. Comparisonbetween modified and existing 64-bit binary comparator designs is calculated by simulation that is performed at90nm technology in Tanner EDA Tool.Keywords:Binary comparator, digital arithmetic, high-speed.

1. Introduction

In digital system, comparison of two numbers is an arithmetic operation that determines if one number isgreater than, equal to, or less than the other number [1]. So comparator is used for this purpose. Magnitudecomparator is a combinational circuit that compares two numbers, A and B, and determines their relativemagnitudes (Fig.1). The outcome of comparison is specified by three binary variables that indicate whether A>B,A=B, or A


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3. Existing 64-Bit Binary Comparator Design64-bit comparator in reference [8], [9], [10] represents tree-based structure which is inspired by fact that G

(generate) and P (propagate) signal can be defined for binary comparisons, similar to G (generate) and P(propagate) signals for binary additions.Two number (each having 2-bits: A1, A0 & B1, B0) comparison can be realized by:

For AB, BBig, EQ is 0,0. Where BBigis defined as output A less than B (A_LT_B). A closer look at equation (1) reveals that it is analogous to the carrysignal generated in binary additions. Consider the following carry generation:

Where A & B are binary inputs Cin is carry input, Cout is carry output, and G & P are generate & propagatesignals, respectively.After comparing equations (1) & (3):

Cin can be considered as G0. Since for static logic, equation (1) requires tall transistor stack height, hence, anencoding scheme is employed to solve this problem. For this, encoding equation is given as:

Where i =0..63.Put these two values from equations (7) & (8) in equations (1) & (2).

Where j =0..31.G & P signals can be further combined to form group G & P signals.

Similarly, for 64-bit comparator, BBig& EQ can be computed as:


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Fig. 2 shows 8-bit version of existing tree-based comparator structure and Fig. 3 -Fig. 5 shows correspondingcircuit schematics for each logic block of each stage. Pre-encoding circuitry is aimed to minimize the number oftransistors. Hence, modified pass transistor logic style is employed to reduce the number of transistors up to 9. Inabove 8-bit example circuitry, the first stage comparison circuit implements equations (9 & 10) forj =0. . . 3,whereas the second stage generates BBig[3:0], BBig[7:4] and EQ[3:0], EQ[7:4] according to equations (11 & 12). Finally,BBig[7:0] and EQ[7:0] are computed in third stage according to equations (13 & 14).

Figure 2: Tree-Diagram of 8-Bit Binary Comparator

Stage 0th is implemented using modified pass transistor logic style giving output in actual form, Stage 1st isimplemented using CMOS logic style giving output in inverse form, Stage 2nd is also implemented using CMOSlogic style but giving output in actual form.

64-bit comparator is here designed by using 7 stages (from 0th to 6th). In stage 0th, modified pass transistorlogic style circuitry (as in Fig. 3) is employed to produce less than & equal to outputs. Output of stage 0th actas input of stage 1st. In stage 1st, CMOS circuitry (as in Fig. 4) is employed to produce inverse inputs for stage 2nd.In stage 2nd, again CMOS circuitry (as in Fig. 5) is employed to produce actual inputs for stage 3rd. Now,according to tree structure given in Fig. 2, again circuitry of stage 1st is used for stage 3rd. Similarly, for stage 4th,circuitry of stage 2nd is employed. For stage 5thcircuitry of stage 1st is employed. For stage 6thcircuitry of stage 2ndis employed. Description of this design is given in tabular form in Table 1.

Figure 3: Schematic of Stage 0th of Existing 64-Bit Binary Comparator


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Figure 4: Schematic of Stage 1st of Existing 64-Bit Binary Comparator

Figure 5: Schematic of Stage 2nd of Existing 64-Bit Binary Comparator

Figure 6: Schematic of NOR gate

According to [8] existing design is having two outputs (A less than B & A equal to B). This research workalso represents here two outputs but they are A less than B and A greater than B. Means A greater than Boutput is here calculated in place of A equal to B output. For this arrangement, an extra circuitry of NOR gate(which is shown in Fig. 6) is included at the end of schematic of existing 64-bit binary comparator design. Outputsof A less than B & A equal to B are given to two inputs of NOR gate that produces A greater than B output.Existing design requires 1210 transistor count for 64-bit binary comparator. Accordingly schematic of Existing64-bit binary comparator is drawn and shown in Fig. 7.


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Figure 7: Schematic of Existing 64-Bit Binary Comparator

Figure 8: Waveforms of Existing 64-Bit Binary Comparator

According to input bit stream, waveforms of existing 64-bit binary comparator are obtained and shown in Fig.8. Waveforms show that only one output is high (1) at a time. When both the outputs less than & greaterthan (A_LT_B & A_GT_B) are low (0), then waveforms represent that equal to output is high (A_EQU_B is

1) at that time. Simulation results for this design are given in Table 4 Table 6 for conclusion.

4. Modified 64-Bit Binary Comparator DesignSome modifications have been done in existing 64-bit binary comparator design [8] to improve the speed of

the circuit. Existing 64-bit binary comparator design [8] follows tree-based structure from 2-bit to 64-bitcircuitry. But modified design follows tree-based structure from 2-bit to 8-bit circuitry only. After 8-bit to 64-bitcircuitry, modified design follow simple logic structure having two stages (Stage A and Stage B) in place of tree-based structure. In modified design, both the outputs of eight (from 0th to 7th) 8-bit comparators of stage A aregiven to 8th 8-bit comparator of stage B to produce final outputs (less than and greater than). A less than Boutputs of 0th to 7th8-bit comparators are given to A0:7 inputs of 8

th8-bit comparator. A equal to B outputs of 0thto 7th8-bit comparators are given to B0:7 inputs of 8

th 8-bit comparator that produces final outputs.For this design, In stage A, basic stage 0th is same as existing 64-bit comparator design & implemented using

modified pass transistor logic style (Fig. 3) giving output in actual manner. Stage 1st

is also same as existing 64-bit comparator design and implemented using CMOS logic style giving output in inverse manner as in Fig. 4.


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Main idea behind PTL (pass transistor logic) is to use purely NMOS pass transistors network for logic operation[5]. The basic difference of pass-transistor logic style compared to the CMOS logic style is that the source side ofthe logic transistor networks is connected to some input signals instead of the power lines. In this design style,transistors act as switch to pass logic levels from input to output [4]. But purely NMOS pass transistors networkdoes not provide full output voltage swing. Due to this reason modified pass transistor logic style (MPTL) have

been used for stage 0th

. MPTL means extra PMOS circuitry is used in pass transistor logic style circuitry to passlogic high (1) from input to output. Stage 2nd has been implemented using GDI (Gate Diffusion Input) logicstyle giving output in actual manner as in Fig. 9. The GDI cell contains four terminals G (the common gateinput of the NMOS and PMOS transistors), P (the outer diffusion node of the PMOS transistor), N (the outerdiffusion node of the NMOS transistor) and the D node (the common diffusion of both transistors).By usingdifferent inputs at P, N and G terminal of GDI cell, the logic gates (AND, OR) can be implemented only withtwo transistors. Most of these functions require 612 transistors in CMOS and other logic styles, but GDI designmethodology requires only two transistors per function. GDI enables lower transistor count. Multiple-input gatescan be implemented by combining several GDI cells [11],[12]. Description of this design is given in tabular formin Table 2. In stage B, all three basic stages are exactly same as in stage A and Description is given in Table 3.

Figure 9: Schematic of Stage 2nd of Stage A of Modified 64-Bit Binary Comparator

Figure 10: Schematic of Inverter of Modified 64-Bit Binary Comparator

Since output of 8-bit comparators are obtained in inverse form. So, at the end of schematic design ofmodified 64-bit comparator two inverters (Fig. 10) are required to produce actual form of output waveform. Thisdesign requires 1282 transistor count for 64-bit comparator. Schematic (using instances of each section) ofmodified 64-bit binary comparator design is drawn and shown in Fig. 11.


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Figure 11: Schematic of Modified 64-Bit Binary Comparator

Figure 12: Waveforms of Modified 64-Bit Binary Comparator

According to input bit stream, waveforms of modified 64-bit binary comparator are obtained and shown inFig. 12. Input bit stream for modified design is same as in existing design of 64-bit comparator. Outputwaveforms of modified design produce same position of 1,s and 0,s as in waveforms of existing design for eachinput bits. Waveforms show that only one output is high (1) at a time. When both the outputs less than &greater than (A_LT_B & A_GT_B) are low (0), then waveforms represent that equal to output is high(A_EQU_B is 1) at that time. Simulation results for modified 64-bit binary comparator design are given intabular form in Table 4 Table 6.

5. Simulation and ComparisonAfter simulation of both the designs final results are obtained for delay and power consumption and are

shown in Table 4 Table 6. Simulations have been carried out at 90nm technology in Tanner EDA Tool.


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Table 1: Description of Existing 64-Bit Binary Comparator design

Detail Stage 0th Stage 1st Stage 2nd Transistor Count

Design Using MPTL Style Using CMOS Style Using CMOS Style1210

Nature of output Actual Inverse Actual

Table 2: Description of Stage A of Modified 64-Bit Binary Comparator DesignDetail Stage 0th Stage 1st Stage 2nd Transistor Count

Design Same as Existing Same as Existing Using GDI style1136


Table 3: Description of Stage B of Modified 64-Bit Binary Comparator Design

Detail Stage 0th Stage 1st Stage 2nd Transistor Count

Design Same as Existing Same as Existing Using GDI style146


Table 4: Simulation Data with 1volt Input Voltage

Design Power Consumption (watt) Delay Time (second)t A LT B t A GT BExisting 9.0675e-6 4.4240e-9 1.6028e-8Modified 1.2265e-5 4.2102e-9 1.5719e-8

Table 5: Simulation Data with 30oC Temperature

Design Power Consumption (watt)Delay Time (second)

t A LT B t A GT BExisting 9.2485e-6 4.4187e-9 1.6033e-8Modified 1.2319e-5 4.1961e-9 1.5722e-8

Table 6: Simulation Data with 50MHz Frequency

Design Power Consumption (watt)Delay Time (second)

t A LT B t A GT BExisting 9.2765e-6 4.4240e-9 1.6020e-8Modified 1.2232e-5 4.2103e-9 1.5718e-8

After simulation of both the designs final results are obtained for delay and power consumption with 1 voltinput voltage. Delay comparison of modified and existing 64-bit comparator designs is shown in Fig. 13 & Fig.14. Simulated data for these graphs is given in Table 4.

Figure 13: Delay (tA_LT_B) with Input Voltage Figure 14: Delay (tA_GT_B) with Input Voltage

The graphs shown in Fig. 13 & Fig. 14 reveal that delay of modified 64-bit comparator design at 1 volt inputvoltage is remarkably reduced than existing 64-bit comparator design. In Fig. 13, delay is reduced 4.8 %. In Fig.14, delay is reduced 1.9 %.

After simulation of both the designs final results are obtained for delay and power consumption with 30oCtemperature. Simulation with temperature has been done at 1 volt input voltage. Delay comparison of modifiedand existing 64-bit comparator designs is shown in Fig. 15 & Fig. 16. Simulated data for these graphs is given inTable 5.


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Figure 15: Delay (tA_LT_B) with Temperature Figure 16: Delay (tA_GT_B) with Temperature

The graphs shown in Fig. 15 & Fig. 16 reveal that delay of modified 64-bit comparator design at 30oCtemperature is remarkably reduced than existing 64-bit comparator design. In Fig. 15, delay is reduced 5.0 %. InFig. 16, delay is reduced 1.9 %.

After simulation of both the designs final results are obtained for delay and power consumption with 50MHzfrequency. Simulation with frequency has been done at 1 volt input voltage. Delay comparison of modified andexisting 64-bit comparator designs is shown in Fig. 17 & Fig. 18. Simulated data for these graphs is given inTable 6.

Figure 17: Delay (tA_LT_B) with Frequency Figure 18: Delay (tA_GT_B) with Frequency

The graphs shown in Fig. 17 & Fig. 18 reveal that delay of modified 64-bit comparator design at 50MHzfrequency is remarkably reduced than existing 64-bit comparator design. In Fig. 17, delay is reduced 4.8 %. InFig. 18, delay is reduced 1.9 %.

6. ConclusionIn modified design, at 1 volt input voltage delay for output A less than B (tA_LT_B) is reduced 4.8 % and

delay for output A greater than B (tA_GT_B) is reduced 1.9 % in comparison to existing design. Similarly, at30oC temperature delay for output A less than B (tA_LT_B) is reduced 5.0 % and delay for output A greaterthan B (tA_GT_B) is reduced 1.9 %. And also at 50MHz frequency delay for output A less than B (tA_LT_B) isreduced 4.8 % and delay for output A greater than B (tA_GT_B) is reduced 1.9 % in comparison to existingdesign. Hence, superiority of modified design is maintained for temperature and frequency also. All of thereduction in delay is obtained after sacrificing power consumption and transistor count. But still modified designgives better result (for delay) than existing design. Therefore, modified 64-bit binary comparator design can bebetter option for high-speed applications.

References[1] M. Morris Mano Digital Design Pearson Education Asia, 3rdEd, 2002.[2] R. Zimmermann and W. Fichtner, Low Power Logic Styles: CMOS Versus Pass Transistor Logic IEEE

Journal of Solid State Circuits, Vol.32, No.7, pp.1079-1090,July 1997.[3] S. Kang and Y. Leblebici CMOS Digital Integrated Circuit, Analysis and Design Tata McGraw-Hill, 3rd

Ed, 2003.[4] A. Bellaouar and Mohamed I. Elmasry, Low Power Digital VLSI Design: Circuits and Systems Kluwer

Academic Publishers, 2nd Ed, 1995.[5] C.-H. Huang and J.-S. Wang, High-performance and power-efficient CMOS comparators, IEEE J . Solid-

State Circuits, vol. 38, no.2, pp. 254262, Feb. 2003.[6] H.-M. Lam and C.-Y . Tsui, High-performance single clock cycle CMOS comparator, Electron. Lett.,

vol. 42, no. 2, pp. 7577, Jan. 2006.


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Paper-2 High-Speed 64-Bit Binary Comparator using Different Logic Styles

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