Paging and Virtual Memory
description
Transcript of Paging and Virtual Memory
OS Spring ‘04
Paging and Virtual MemoryOperating Systems Spring 2004
OS Spring ‘04
The memory of a program Source-code is compiled into linkable
object modulesMemory addresses given as relative offsetsLibraries contain object modules
Object modules are linked together into a loadable module
Leave unresolved references to dynamic libraries
Loadable modules are loaded into memory and execute in a process
The OS + hardware map from logical address space to physical memory
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Physical to logical address mapping Every memory access is handled by the
memory management unit (MMU)Example: C = A+B four memory accesses (why?)
Simple scheme: Physical addr = base register + logical addr
Logical addressing allowsMultiple programs to co-exist in memoryUse overlays to increase the available address space beyond physical limitationUse shared libraries and dynamic library loading
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Swapping Use secondary storage to store running
processesSwap-out: suspend a process, copy its memory from main memory to diskSwap-in: copy a stored process from disk to main memory and resume running state
Logical addressing: allow swapping back to a different location in memory
Caution: DMA and asynchronous I/O to swapped processes must take care
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Memory management: Review Fixed partitioning, dynamic
partitioning Problems
Internal/external fragmentationA process can be loaded only if a contiguous memory chunk is available to accommodate the processProcess size is limited by the main memory size
Advantage: simplicity
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Paging Process memory is divided into fixed
size chunks of the same size, called pages
Pages are mapped onto frames in the main memory
Process pages can be scattered all over the main memory
No external fragmentation
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Paging example01
23456789
1011121314
A.0 A.1 A.2 A.3
C.0 C.1 C.2 C.3
D.0D.1D.2
D.3D.4
0
123
Process A
0123
0
12
Process B
---------
01234
0
123
Process C
789
10
456
1112
Process D
Free Frame List
1314
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Paging support Page table maintains mapping of
process pages onto frames Hardware support is needed to
support translation of relative addresses within a program (logical addresses) into the memory addresses
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Address translation Page (frame) size is
a power of 2with page size = 2r, a logical address of l+r bits is interpreted as a tuple (l,r)l = page number, r = offset within the page
Page number is used as an index into the page table
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Hardware support
Program Paging Main Memory
Logical address
Register
Page Table
PageFrame
Offset
P#
Frame #
Page Table Ptr
Page # Offset Frame # Offset
+
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Virtual Memory Paging makes virtual memory
possibleLogical to physical address mapping is dynamic
=> It is not necessary that all of the process pages be in main memory during execution
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Benefits More processes may be maintained in
the main memoryBetter system utilization and throughput
The process size is not restricted by the physical memory size: the process memory is virtual
But what is the limit anyway? Less disk I/O to swap/load programs
OS Spring ‘04
How does this work? CPU can execute a process as long as
some portion of its address space is mapped onto the physical memory
E.g., next instruction and data addresses are mapped
Once a reference to an unmapped page is generated (page fault):
Page fault interrupt transfers control to the OS handler
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Page Fault Handler Put the process into blocking state Program disk controller to read the
page from disk into the memory Later on: I/O interrupt signals
completion Resume the process
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Why is this practical? Observation: Program branching and
data access patterns are not random Principle of locality: program and data
references tend to cluster=> Only a fraction of the process
virtual address space need to be resident to allow the process to execute for sufficiently long
OS Spring ‘04
Virtual memory implementation Efficient run-time address translation
Hardware support, control data structures Fetch policy
Demand paging: page is brought into the memory only when page-fault occursPre-paging: pages are brought in advance
Page replacement policyWhich page to evict when a page fault occurs?
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Thrashing A condition when the system is
engaged in moving pages back and forth between memory and disk most of the time
Bad page replacement policy may result in thrashing
Programs with non-local behavior
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Address translation Virtual address is divided into page
number and offset
Mapping of virtual pages onto physical frames are facilitated by page table(s)
Forward-mapped page tables (FMPT)Inverted page tables (IPT)
Virtual Address
Page Number Offset
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Forward-mapped page tables (FMPT)
Page table entry (PTE) structure
Page table is an array of the above
Index is the virtual page number
P M Frame NumberOther Control Bits
Page Table
Frame #
Page #
P: present (valid) bitM: modified bit
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Address Translation using FMPT
Program Paging Main Memory
Virtual address
Register
Page Table
PageFrame
Offset
P#
Frame #
Page Table Ptr
Page # Offset Frame # Offset
+
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Handling large address spaces One level FMPT is not suitable for
large virtual address spaces32 bit addresses, 4K (212) page size, 232 / 212 = 220 entries ~4 bytes each =>
4Mbytes resident page table per process!What about 64 bit architectures??
Solutions: multi-level FMPTInverted page tables (IPT)
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Multilevel FMPT Use bits of the virtual address to
index a hierarchy of page tables The leaf is a regular PTE Only the root is required to stay
resident in main memoryOther portions of the hierarchy are subject to paging as regular process pages
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Two-level FMPTpage number page offset
pi p2 d10 10 12
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Two-level FMPT
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Inverted page table (IPT) A single table with one entry per
physical page Each entry contains the virtual
address currently mapped to a physical page (plus control bits)
Different processes may reference the same virtual address values
Address space identifier (ASID) uniquely identifies the process address space
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Address translation with IPT Virtual address is first indexed into
the hash anchor table (HAT) The HAT provides a pointer to a linked
list of potential page table entries The list is searched sequentially for
the virtual address (and ASID) match If no match is found -> page fault
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Address translation with IPT
Virtual addresspage number offset
hash
+
HAT baseregister
ASIDregister
page numberASID
Frame#
IPT
+
IPT baseregister
frame number
HAT
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Translation Lookaside Buffer (TLB) With VM accessing a memory
location involves at least two intermediate memory accesses
Page table access + memory access TLB caches recent virtual to physical
address mappingsASID or TLB flash is used to enforce protection
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TLB internals TLB is associative, high speed memory
Each entry is a pair (tag,value)When presented with an item it is compared to all keys simultaneouslyIf found, the value is returned; otherwise, it is a TLB missExpensive: number of typical TLB entries: 64-1024Do not confuse with memory cache!
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Address translation with TLB
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Bits in the PTE: Present (valid) Present (valid) bit
Indicates whether the page is assigned to frame or notA reference to an invalid page generates page fault which is handled by the operating system
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Bits in PTE: modified, used Modified (dirty) bit
Indicates whether the page has been modifiedUnmodified pages need not be written back to the disk when evicted
Used bitIndicates whether the page has been accessed recentlyUsed by the page replacement algorithm
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Bits in PTE Access permissions bit
indicates whether the page is read-only or read-write
UNIX copy-on-write bitSet whether more than one process shares a pageIf one of the processes writes into the page, a separate copy must first be made for all other processes sharing the pageUseful for optimizing fork()
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Protection with VM Preventing processes from
accessing other process pages Simple with FMPT
Load the process page table base address into a register upon context switch
ASID with IPT
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Page size considerations Small page size
better approximates localitylarge page tablesinefficient disk transfer
Large page sizeinternal fragmentation
Most modern architectures support a number of different page sizes
a configurable system parameter