P9 addressing signal_integrity_ in_ew_2015_final

Addressing Signal Integrity in Radar and Electronic Warfare Systems2015 Aerospace Defense Symposium

[ Speaker Name ] Keysight Technologies

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Paper Summary

Increasing data bus rates in today’s Radar and EW systems can lead to electrical impairments, affecting the signal integrity of the transmitted signals. Signal Integrity can be measured and characterized to help design engineers avoid potential problems.

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Agenda2015 AD Symposium

– What is Signal Integrity?

– What challenges can occur at high data rates?

– Where are the high data rates occurring in Radar/EW applications?

– How do we address those with our solutions?

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What is Signal Integrity?

Even digital signals, 0’s and 1’s, are represented by a voltage waveform.

Those digital signals implemented into real systems with PC board traces, connectors, and cables will be subject to analog parametric issues.

Short distances, low bit rates… no problem.

High bit rates, longer distances? Various effects will degrade the signal.

Think Signal Quality…

• Set of measures of the quality of an electrical signal

Signal Integrity (SI)

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Channel ResponseSource Signal

Received signal

Signal Integrity is Critical…

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Transmitter(TX)

Receiver(RX)Channel

0 1 0 1 1 0 0

All transmitted signals shall be received correctly

Beyond some speed everything affects signal integrity

High Speed Drives Signal Integrity

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Receiver(RX)Channel

0 1 0 1 1 0 0




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Transmitter(TX)

Receiver(RX)Channel

0 1 0 1 1 0 0




Channel responses of two backplane topologies(1)

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Transmitter(TX)

Receiver(RX)Channel

0 1 0 1 1 0 0





S-Parameter of PCIe channel

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Transmitter(TX)

Receiver(RX)Channel

0 1 0 1 1 0 0




S-Parameter of PCIe channel


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Agenda2015 AD Symposium 11





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Effects That Can Degrade the Signal

System Performance Power Supply Noise

Material Loss vs Frequency EMI/ Crosstalk

InterconnectionsImpedance TDR

PackageConnector Cable

PCB

ConnectorPackage

PCB

ICIC

PassiveTx ActiveRx

Active

ImpedanceMatching

Channel Skin Effect


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Sample Scenario

#1) Radar Guided Missile Capture and Playback

X-band Radar10 GHz

Target


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– Time of Arrival (TOA)

– Angle of Arrival (AOA)

– Frequency (RF)

– Amplitude (PA)

– Pulse Width (PW)

#2) Radar Warning Receiver (PDWs)

AOA

RFPA

PWTOA

Sample Scenario


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RF Converter ADCs Spectrum

EstimatorPara

EncoderDigital

Processor

#2) Radar Warning Receiver (PDWs) cont’d

Digital EW Receiver

Digital WordsIF Freq

Sample Scenario


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Digital Commercial Off the Shelf (COTS )

• Double data rate DRAM• Class of memory used in computer systems and

embedded systems• ie: Store incoming waveform data for playback

DDR Memory

• Serial high-speed interconnect/link• ie: Interface to stream data from receiving

antenna to processing PC.PCIe

• Serial high-speed interconnect/link• ie: Many applications, wherever you see Ethernet

now.

10 Gb Ethernet


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SI Measurement Needs

Upward trend of bus rates calls for special kind of design engineer.

High-speed interconnects are critical elements of differential channels that must be designed using today’s most powerful analysis and characterization tools.

Both simulation and measurements must be done on DUT and resulting data needs to correlate with each other.


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High Speed Digital Design-Flow

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ComplianceTest

System Design

InterconnectDesign

Analysis Debug

• Build accurate models

• Accurate Simulation

• Refine models & simulations

• Accurate Design Analysis

• Correlation

• Accurate Design Analysis

• Measurement Automation

• Debug• Correlation

• Stress test• Protocol test• Measurement

Automation• Compliance


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Channel Simulation with Keysight ADS

– Extremely Fast and Accurate

– Waveforms/BER/Eye Diagrams.

– Electrical & Optical S-parameters from EM/VNA/TDR/LCA

System

Design


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TDR/TDT

Time Domain Reflectometry (TDR)

– Example measurements:• Impedance - locate the position and nature

of each discontinuity• Propagation/Time delay• Excess Reactance

(Capacitance or Inductance)


Incident wave

Reflected wave

DUT- PCB- Connector- Cable- Interconnect

Step Generator

Sampler

TDR (impedance Profile)S11 (Return Loss)

TDR Module


Incident wave

Reflected wave


Step Generator

Sampler

TDR (impedance Profile)TDR Module

Time Domain Transmission (TDT)

Incident wave

Reflected wave


Step Generator

Sampler

TDR S11

TDR Module

Transmitted wave

Step Generator

Sampler

TDR or RX onlyModule

TDT (Step Response)

Time Domain Transmission (TDT)

Example Measurements:• Step Response• Propagation/Time delay• Rise time degradation • Near-end crosstalk (NEXT)• Far-end crosstalk (FEXT)• Skew

Interconnect

Design


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Physical Layer Test System

Industry Standard for High Speed Digital Interconnect Analysis• Calibrate, measure and characterize

backplanes, PCBs, cables, connectors and IC packages

• Leverage multi-domain analysis to use one test system for all time domain, frequency domain, eye diagram, and RLCG analysis

• Extract full 4-port s-parameters of fixtures from a simple reflection measurement

• Commonly used for multi-port/channel. (Up to 32)

Interconnect

Design


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Together, TDR/TDT and S-Parameters Provide Tremendous Insight

TDR and S21 are most intuitive, insightful.

TDRZ profile

TDTStep Response

S11Return Loss

S21Insertion Loss

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Four-port single-ended device(or 2-port Differential)

Port 1

Port 3

Port 2

Port 4

Complementeach other

Most SI labs have both solutions.

VNA

TDR

Interconnect

Design


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Eye Diagram

• The easiest way to get an overall idea of the quality of the serial signal

• Measurement commonly made on an Oscilloscope

• Eye Diagram is the superposition of all combination of bit sequences

• Multiple cases combined form the Eye

• Trigger on Clock signal (if available) as the rough first pass to build Eye Diagram

101 Sequence 011 Sequence Overlay of all combinations

Analysis

Debug

Infiniium 90000 X-Series


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What Closes the Eye

• Eye “closing” indicates variations in both voltage levels of bits and timing issues.

• Various SI issues can cause the eye to close.

- Attenuation due to Material Loss or Channel Skin Effect

- Noise from power supply

- Glitches from reflections or other data lines (Impedance mismatches, EMI/X-talk)

- System Bandwidth limitations

Analysis

Debug


Analysis

Debug

Eye Diagrams – Simulation vs. Measurement

5 Gb/s 10 Gb/s

5 Gb/s 10 Gb/s

Simulation Simulation

MeasurementMeasurement

- Simulation using saved .s4p file

SIMULATION

MEASUREMENT

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- Good correlation between simulation and measurement- As expected, edge speeds at 10 Gbps are much slower (lack of 3rd harmonic content)

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Bit Error Ratio Tester (BERT)

J-BERT M8020A

Analysis

Debug

• Primary quality metric of a transmission link.

• Measures number of failed bits at receiver compared to total number of transmitted bits.

• Common BER level is 10-12

Pattern Generator

Error Detector


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Keysight’s solution set for high-speed digital test is a combination of instrumentation and broad expertise built on our ongoing involvement with industry experts. By sharing our latest experiences, we can help anticipate challenges and accelerate your ability to create products you’ll be proud of.

Advanced Design System

(ADS) and EMPro

N1930B Physical Layer Test

System (PLTS)

Bit Error Ratio Testers (BERTs)

ENA-TDR

Infiniium 90000 X-Series

AXIe-based Logic

Analyzer Module86100D Infiniium

DCA-X

Insights For Your Best Design With Keysight


http://cp.home.agilent.com/agilent7/s7viewers/flash/genericzoom.swf?logo2=false&serverUrl=/agilent7/is/image/&contentRoot=/agilent7/skins/&locale=en&config=Agilent/AGILENT-IMGSET&image=Agilent/PROD-1970950-IS

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Top 3 Take-Aways

At high data rates, there are various effects that can distort the integrity of a signal that you are trying to transmit.

These high data rates can be found in many Radar and EW applications and

will only continue to grow.

Keysight has the solutions and expertise to address these Signal Integrity

challenges from beginning to end.


Questions?

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Back Up (Resources)


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– Signal Integrity Keysight Homepage

– Signal Integrity YouTube Videos

– Signal Integrity

• Basic Principles of Signal Integrity and how to combat those issues

• Signal Integrity Characterization techniques (Book)

• New Calibration Method Simplifies Measurements of Fixtured Devices


Resources (Presentations, Application Notes, Web links)

http://www.keysight.com/main/application.jspx?nid=-33803.0.00&pageMode=OVW&lc=eng&cc=US

https://www.youtube.com/results?search_query=Keysight+Signal+Integrity

http://www.altera.com/literature/wp/wp_sgnlntgry.pdf

https://www.keysight.com/main/editorial.jspx?cc=US&lc=eng&ckey=2234865&id=2234865&cmpid=zzfindhsd-achieve

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– Design/Simulation(EEsof)

• SI Q&A collections using Keysight ADS

• Tutorials in SI Webcasts library

• EEsof High Speed Digital Internal site

• Signal Integrity Blog

• Presentations

- TDR/TDT Simulation skills (June, 2014)

- EMI/EMC Analysis for HSD Designs (July, 2014)

- How to optimize your SerDes design during pre-layout phase (Sept, 2014)


http://www.keysight.com/main/eventDetail.jspx?cc=US&lc=eng&ckey=2383711&nid=-34360.0&pid=1475688

http://fieldcom.cos.keysight.com/blog/cwarwick

http://signal-integrity.blogs.keysight.com/

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– TDR/PLTS

• Breakthrough Developments in TDR/TDT Measurement Technology (June, 2014)

• PLTS 2015 Software Technical Overview

– Oscilloscopes

• Measure your Signal, not your Measurement System

• How Understanding and Characterizing an Oscilloscope Impacts Signal Integrity

• Perform Deep Real-Time Eye Analysis

• Practical Guide to Making Advanced Jitter Measurements

• Evaluating Oscilloscope Signal Integrity (Application Note)


http://literature.cdn.keysight.com/litweb/pdf/5989-6841EN.pdf



P9 addressing signal_integrity_ in_ew_2015_final

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Transcript of P9 addressing signal_integrity_ in_ew_2015_final