Overview Three-State Devices, Comparators · Magnitude Comparators : 28 A Comparator A=B? B A...

EE260: Digital Design, Spring 2018 28-Feb-18

Chapter 7: Three-State Devices, Comparators 1

EE 260: Introduction toDigital Design

Three-State Devices, Comparators

Yao ZhengDepartment of Electrical Engineering

University of Hawaiʻi at Mānoa

Overviewn Buffersn Three-state Buffersn Bi-directional Pinsn Applications of Tri-State Circuitsn XOR Reviewn Parity Circuitsn Comparators

Buffersn The number of circuit inputs that can be driven

by a single output is limitedn If a circuit output must drive many inputs, we

use buffers to increase the driving capabilityn The buffer below (having the output F) is a

noninverting buffer: it does not perform any logic function, i.e. its logic equation is F=C.

n It only increases the driving capability

Non-inverting buffer

Fig 9-6. Circuit with added buffers [RothKinney]

Three-state buffersn Normally the outputs of two circuits cannot be

connected togethern If they were connected, and if one output is 0 and the

other output is 1n the resulted voltage can be between LOW (logic 0) and HIGH

(logic 1)n Hence, an undecided logic valuen Or even the circuits can be damaged

n Sometimes it is necessary to connect two outputs, under the condition that they will not be simultaneously active

n The de-activation of an output can be realized using three-state buffers

n The figure below shows a three-state buffer and its logical equivalent

Three-state buffers

n Output = LOW, HIGH, or Hi-Z.

lCan tie multiple outputs together, if at most one at a time is driven.



Three State Buffers/Drivers

n A buffer/inverter with enable input

n

Buffer Buffer Inverter InverterActive High Enable Active Low Enable Active High Enable Active Low Enable

n The device behaves like an ordinary buffer/inverter when the enable input is asserted.

n The output is floating ( High Impedance, Hi-Z ) when the enable input is deasserted ( The input is isolated from the output, behaves as if it did not exist)

n Application: Controlling the access of a single line/bus by multiple devices

Three-state buffersn Normally, there is a path between the output of a circuit and

n either GND (ground) => Vout=LOW, or VCC (+5V) => Vout=HIGHn There are circuits (buffers) for which the paths to GND and

VCC are both blockedn The output of the buffer is then in a high-impedance state,

called Hi-Z (the third state)n No current can flow in the buffer’s output, the buffer has a

very high resistance (impedance)n Logically, it is as if the output of the buffer is disconnectedn The three state buffers have an enable input that determines

if the buffer functions as a normal buffer, or its output is in Hi-Z

n The command and the output can be inverting or non-inverting

Three-state buffers in CMOS Tri-state buffers for data selection

Data selection using three state buffers and the logically equivalent circuit

Logic values for buses signals

S2X 0 1 Z

S1

X X X X X0 X 0 X 01 X X 1 1Z X 0 1 Z

Table 1: Logic values for bus signals and the resulting value when they are connected together

Circuit with tri-state buffers

Four sources for one operand

Circuit with bi-directional input-output pins

Bi-directional pins



8 sources share a three-state party line

Timing considerations

Standard SSI/MSI 3-state buffers

SSI: 74x125, 74x126 (independent enable inputs)

MSI: 74x541 and varieties such as 74x540, 74x240, 74x241 Hysteresis

Octal non-inverting 3-state buffer

Fig 6-54 [Wakerly]: The 74x541 octal tristate buffer: (a) logical diagram; (b) logical symbol

The circuit is used in microprocessor systems for connecting peripheral devices (they have 8 data bits)

Inputs G1_L and G2_L: enable inputs.

Symbol on gates means hysteresis: improved noise immunity

Fig 6-56

[Wakerly]

74x245 octal

tri-state

transceiver: (a)

logic diagram;

(b) logic symbol

Bus transceiver: contains pairs of

tri-state buffers connected in

opposite directions: from A to B if

DIR=1, or from B to A if DIR=0

Buffers are enabled only if G_L=0

The circuit is used typically

between two busses.



Driver application Transceiver application

Bidirectional buses

Overviewn Buffersn Three-state Buffersn Bi-directional Pinsn Applications of Tri-State Circuitsn XOR Gatesn Parity Circuitsn Comparators

Exclusive OR and Exclusive NOR Gates

n XOR :

n XNOR :

n Truth Table :XOR

X Y XOR XNOR 0 0 0 10 1 1 01 0 1 01 1 0 1

XOR

X

Y

F

X

Y

F

'' YXYXYX ×+×=Å

'')'( YXYXYX ×+×=Å

XOR and XNOR Symbols

n Equivalent Symbols of XOR gate

n Equivalent Symbols of XNOR gate

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Any 2 signals (inputs or outputs) may be complemented without changing the resulting logic function

SSI XOR and XNOR

n 74x86 : 4 XOR gates

n 74x266: 4 XNOR gates with “open collector” or “open drain” output

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XOR Application: Parity Circuitn Odd Parity Circuit : The output is 1 if odd number of inputs are 1n Even Parity Circuit : The output is 1 if even number of inputs are 1n Example : 4-bit Parity Circuit

Daisy-Chain Structure Tree structure

Input : 1101 Odd Parity output : 1Even Parity output : 0

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I0

I1

I2

I3ODD

EVEN I0

I1

I2

I3

ODD

EVEN

MSI Parity Circuit : 74x280

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Parity-Checking Application: memory

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Comparators

n Compares Two binary words and indicate if they are equal

Magnitude Comparators :

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AComparator A=B?

B

AComparator

A=B

BA>B A<B

Equality Comparators

n 1-bit comparator

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l4-bit comparator

EQ_L

Iterative Comparator

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Multi-bit Iterative Comparator

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MSI Comparator : 74x85

n 4 bit comparatorn 3 outputs : A=B, A<B, A>Bn 3 Cascading inputs n Functional Output equations :

(A>B OUT)= (A>B)+(A=B).(A>B IN)(A<B OUT)= (A<B)+(A=B).(A<B IN)(A=B OUT)= (A=B).(A=B IN)

n Cascading inputs initial values : (A=B IN) =1(A>B IN) =0(A<B IN) =0

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B0

A1

B1

A2

B2

A3

A0

B3

74x85

A<BIN

A=BIN

A>BIN

A<BOUT

A=B OUT

A>BOUT

MSI Comparator : 74x85 8 bit Comparator

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B0

A1

B1

A2

B2

A3

A0

B3

74x85

A<BIN

A=BIN

A>BIN

A<BOUT

A=B OUT

A>BOUT

B0

A1

B1

A2

B2

A3

A0

B3

74x85

A<BIN

A=BIN

A>BIN

A<BOUT

A=B OUT

A>BOUT

B0

A1

B1

A2

B2

A3

A0

B3

B4

A5

B5

A6

B6

A7

A4

B7

+5V

A<B

A=B

A>B

Most Significant bitsLeast Significant bits

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Other conditions

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