Overview of PSL/Sugar support by EDA vendors

PSL/Sugar Consortium Meeting DATE 04

Adriana Maggiore

Usage of PSL/Sugar in Functional Verification Simulation

Constraint inputs for test generation Monitors for observability, coverage and error localisation

Formal Verification Assumptions about input constraints Assertions to prove about the design

Hybrid Flows Combined simulation and formal verification

Others Assertion development, protocol libraries, synthesis, training

PSL/Sugar support by EDA vendorsSimulation Formal Hybrid + Others@HDL

0-in

Cadence

Esterel

FTL

IBM

Mentor Graphics

Novas

Safelogic

Summit

SynaptiCAD

TransEDA

Verisity

@HDL

0-in

IBM

Real Intent

Safelogic

TransEDA

Veritable

@HDL

0-in

Doulos

IBM

Safelogic

TransEDA

@HDL – Feb 2004 – www.atHDL.com

PSL Sugar Support

Model Checking for assertions written in PSL• Full BDD based and bounded model checking• Hierarchical model checking• Incremental and Distributed model checking• Complex constraint specification and state reduction

Automatic extraction of complex properties into PSL :

• FSM Deadlock, Multi-cycle path, False path, FIFO’s• Reset logic and clock synchronization

Simulation support for automatic PSL assertions into industry standard simulators (NC, VCS, MTI, Finsim)

Integrated debugging environment for PSL through @Designer for formal and simulation results

@HDL – Feb 2004 – www.atHDL.com

Assertion StudioTM

Technology[ Patent-pending ]

@HDLPSL

AssertionStudioUnified

Simulation & FormalABV

Interpreter

WaveformDB / VCD • Verifying correct

behavior of assertions without simulating• Modifying and Testing faulty assertions

STEP 2

Explorer

• Detailed assertion execution analysis• Tracing the causes of failing/passing assertions• Use Interpreter for modified assertions

STEP 4

Assessor

• Statistical Analysis• Regression Analysis

STEP 5

Verification

STEP 3

• Pass / Fail• @HDL PSL Engine for Sim• @Verifier, DP, ZX for Formal

SimEngines

FormalEngines

Visualizer

PSL

SVA

TimingDiagrams

STEP 1UserWritten

0-In Design Automation Copyright 2004 6

0-In® Assertion-BasedVerification Suite

0-In CheckerWare® library» Verification IP with structural coverage» Pre-verified, encapsulated assertions macros focused on RTL

functionality, e.g. arbiter, fifo, etc.» Built on standard design and assertion languages

0-In CheckerWare monitors» Verification IP for standard protocols, e.g. PCI Express, SPI-4,

Hypertransport, AMBA, DDR SDRAM, etc.» Simple to use assertions capturing complex behaviors

Archer Verification™ System» Dynamic formal verification to automatically, exhaustively

exercise corner-cases» Static formal verification (model checking) to find deep bugs

PSL Assertions

Verify PSL Assertions

CADENCE CONFIDENTIAL

Cadence PSL/Sugar Support

Cadence Language Position

• Cadence is committed to ensure unified standards for advanced design and verification

• Cadence provides current and continuing support for the VHDL, Verilog (incl. SystemVerilog extensions), PSL/OVL, SystemC, Verilog-AMS, and VHDL-AMS standards

PSL/Sugar in the Cadence Incisive Verification Platform

• Native compilation and execution of PSL/Sugar assertions

• Optimizes PSL/Sugar assertions into Incisive single kernel engine

• PSL/Sugar assertions are treated as verification objects

• Interactive simulation & debugging: breakpoints, interrogation, probing

CADENCE CONFIDENTIAL

Incisive Debug Environment

Goto-cause on failure event brings up the assertion sourceAssertion activity

is recorded as a transaction

Double-clicking on Assertion name brings up the assertion source

Assertion failures shows up as events on a probe.

Independent Language & Methodology Training

Doulos have announced trainingand reference support for

PSL/Sugar

• Expert VHDL & Verilog courses upgraded to include PSL coverage

• Assertion-based Verification using PSL (1-day course)

• Tool specific PSL training

• PSL Golden Reference Guide

Esterel Technologies Confidential

Esterel Technologies is committed to support interoperability between Esterel Studio and the assertion standard PSL/Sugar

Esterel Technologies is currently implementing support of a PSL + Esterel simulation flow for its customers

Esterel technologies is planning to support static verification of PSL properties with Esterel Studio designs Definition of PSL subset and PSL flavor

supported within Esterel Studio is planned for 2005, as a result of current customer interactions.

Esterel Technologies Support of PSL / Sugar

EsterelIP design

PSL / EDLassertions

Esterel Compiler

FoCs

VHDL / VerilogVHDL / Verilog

HDL Simulator

Simulation FlowEsterel IP design + PSL/EDL asserts

Property Specification Language (PSL) Version 1.01 Support in Release 9

Auriga Highly Parallel Verification Environment uses PSL verificationdirectives to validate designer intent

Merlin Behavioral SynthesisEnvironment uses PSL toimplement designer intent

Auriga and Merlin are trademarks of FTL Systems Inc. & FTL Systems UK Ltd. For further information seehttp://www.ftlsystems.com or write info@ftlsystems.com. For further information on analog/mixed signal

and asynchronous extensions, please contact John Willis at FTL Systems, jwillis@ftlsys.com

Ongoing, funded work coordinated by FTL Systems provides foranalog/mixed signal and asynchronous extensions to PSL

PSL/Sugar Support in IBM’s Verification Tools

PAssertions

FormalFormal

SimulationSimulation

Assertions

IBM RuleBase Parallel Edition:Static Property Checking via Parallel FV• PSL support :

– Fully supports the simple subset, which can be checked "on-the-fly“

– Supports advanced constructs, e.g. sequence operators, abort, named sequences, named properties, forall

• Powerful formal model checking platform– Optimized for PSL/Sugar– Capable of handling very large design models– Automatic state-space reduction leaves only parts

relevant to verified properties– Optimized for 3 modes of operation

• exhaustive search, partial search and adaptive search

The RuleBase Parallel Edition Platform: Two Tiers of Parallel FV

• Coarse-Grain Parallel FV– Central engine dispatch point – Distribution of multiple verification tasks

• Fine-Grain Parallel FV– Decomposition of a large verification tasks into smaller, tractable subtasks

Engine

Dispatcher

slaveslave

slave

slaveslave

slave

formal

engine

formal

engine

RTL

+ PSL

FoCs (Formal Checkers)

• Function - Runtime (“dynamic") checking of PSL assertions

during simulation

• Features - Generates Verilog/VHDL/C++ monitors from PSL

properties– functional checking + coverage tracking

- Optimized for RTL simulation - Synthesizable RTL produced - applicable for emulation - Independent of simulator and methodology - User-friendly self-explanatory GUI

VHDL

System Verilog

Verilog 2001

C/C++SystemC

Mathworks

AMS

HW/SW

DebugCoverage

PSLAssertions

Mentor Graphics PSL Support

Initial Tool Support: ModelSim 5.8— Announced on Oct 27, 2003

Built-in assertion engine — PSL available now— Supports both embedded and file-

based assertions

Integrated into ModelSim debug environment

— New Assertion Browser— Cross referenced to all windows to

speed up debugging Wave, Source, Dataflow

ModelSim5.8

Novas Software, Inc. • • Way Beyond Waveforms

Novas PSL and SVA Assertion-Driven Debug

Load and view assertion source and results

View assertion/design association

Waveform shows assertion pass/fail

Trace assertion “drivers” and “loads” across design

Cause-and-effect details

Automatically trace assertion failures

Verdi engine quickly finds root cause

Post-process captured signal data (FSDB) to check assertions

Check new assertions without re-running simulation

Other supported assertion languages

OVA

PSL Source Code - can be traced

Pass/Fail Waveform

Verdi Automatic Tracing

Verix from Real Intent:A Complete Formal Assertion Verification System

• Automatic Formal Assertions• User-specified Assertions in PSL• Formal Asynchronous Clock

Domain Checking• Automatic, Scalable Hierarchical

Formal Analysis• Verilog, VHDL, and Mixed

Language Support

www.safelogic.se

Safelogic property verification methodology

1. Run Safelogic Monitor for design/property sanity check

2. Run Safelogic Verifier to select strategy per design block or property

3B. Run Safelogic Verifier on

blocks/properties that are

’appropriate’ or of certain interest

3A. Run Safelogic Monitor on anyproblem to boost simulation results

Visual Elite™ PSL Flow

Visual Elite provides a seamless assertion-based design flow

The PSL source resides as a side object in the browser and is seamlessly processed through IBM’s FoCs

Assertions generated during simulation

Design PSL/Sugar

Simulate

Assertions

FoCs

SynaptiCAD TestBencher Pro Generates test benches for VHDL, Verilog, TestBuilder, & SystemC

Verification systems need to model different protocols.

With TestBencher, users describe protocols using graphical timing diagrams.

TestBencher generates entire verification system including Sugar assertions. Generated Sugar

assertions used to verify protocol compliance.

SynaptiCAD Transaction TrackerAnalyze transaction data during and after simulation

Transaction Tracker locates transactions using Sugar expressions.

Transactions are displayed as extra signals in the waveform window.

Users enter temporal expressions using Transaction Tracker Sugar Wizard.

Transaction Tracker can identify transactions during and after simulation.

TransEDA support for PSLTransEDA support for PSL

imPROVE-HDL: Formal Property Checker• Includes Hardware Protocol Kits (HPKs) for Automatic

and Exhaustive Protocol Formal Verification• Use PSL to add design-specific properties

VN-Property: Simulation-based Property Checker• Links property coverage to code-coverage with VN-Cover• Includes HPKs for Automatic Protocol Verification• Use PSL to add design-specific properties

PSL as Part of a Total Verification SolutionPSL as Part of a Total Verification Solution

Specman Elite® : Testbench Automation Automates verification process with directed-random test

generation, data/assertion checking, functional coverage analysis PSL assertions embedded in HDL and/or testbenches

Used as runtime checkers Provides additional coverage metrics

– Total coverage: Functional, Code, and Assertion Coverage Links to formal verification

PSL assertions embedded in e verification language Enables code sharing between simulation and formal Enables reuse of HDL assertion in more powerful testbenches

Specman Elite® : Testbench Automation Automates verification process with directed-random test

generation, data/assertion checking, functional coverage analysis PSL assertions embedded in HDL and/or testbenches

Used as runtime checkers Provides additional coverage metrics

– Total coverage: Functional, Code, and Assertion Coverage Links to formal verification

PSL assertions embedded in e verification language Enables code sharing between simulation and formal Enables reuse of HDL assertion in more powerful testbenches

Coverage and Assertion InterfaceCoverage and Assertion Interface

Coverage

Checking

Specman Elite

CAICoverage samples

DUT errors

SureCov™

…

Sugar/PSL

External coverage & assertion sources

OVL

Verity-Check ExpertVerity-Check Expert

Formally checks user specified temporal properties Automatic state space reduction without user guidance More than order of magnitude faster than model checkers Multi-million gate capacity allows full chip verification

Properties can be specified using Accellera PSL/Sugar Supports Verilog flavor of PSL

Property violations result in generation of test sequences Counter-examples displayed as waveforms or testbench generated

Easy to use, robust tool Used in production flows since 2001