CMOS IC Design Process:CMOS IC Design Process:OVERVIEW OF OVERVIEW OF

VLSI DESIGN METHODOLOGIESVLSI DESIGN METHODOLOGIES

Overall flow of design activities

Important design concepts

Various VLSI design styles

Quality of design and CAD technology

CMOS IC Design Process:

Structural complexity (no. of transistors per chip) of digital integrated circuits is increasing exponentially over last 40 years. It is supported by

-- Constant advances in manufacturing technology

-- Need for complex functional integration on chip

For development of economically viable VLSI products, in a timely manner; efficient organization of

--development of technology,

--CAD tools,

--chip design,

--fabrication,

--packaging,

--testing and

--reliability qualification

Is needed.

Design cycle time: From start of the chip development until mask tape delivery time.

The design complexity of logic chips increases exponentially with no. of transistors to be integrated. This complexity reflects into the design cycle time.

For ex: Design complexity of logic chips is much higher to that of a memory chip.

Performance: Processing speed, Power dissipation, Area, Cost

Tape-out or Tapeout :The final stage of the design cycle of integrated circuits or printed circuit boards, the point at which the description of a circuit is sent for manufacture

VLSI design

Full custom (geometry &

placement of every transistor

can be optimized individually)

Semi custom (such as std cell design or FPGA)

For economic success of any competitive commercial product, majority of the design cycle time is devoted to achieve a certain desired performance of the chip at an acceptable cost.

Impact of different VLSI design styles on design cycle time and achievable circuit performance:

Inference:Full custom design:

Requires longer time till design maturity

Adjustment flexibility of almost every aspect improves the circuit performance

High performance but large cost in terms of design cycle time.

Semi custom design:

Requires less time till design maturity

In early stage, performance is better to full custom design because, some components are optimized. But, less opportunity for improvement in the circuit performance.

Lesser performance but shorter design cycle time.

Impact of different VLSI technology generations on design cycle time and achievable circuit performance:

Every 2 years, a new generation of technology is evolved to give:

Smaller dimensions;

Greater integrating capacity and

Higher performance.

Inference:

To make best use of current technology, chip development time should be short enough so as to give timely delivery of the product to customers.

In reality, design cycle of next generation chips usually overlaps with the production cycle of current generation chips, thereby assuring the continuity.

Design HierarchyDesign Hierarchy Systems, Subsystems, Systems, Subsystems,

Modules, Submodules :- Modules, Submodules :- Until the complexity of Until the complexity of the smaller part the smaller part becomes manageable.becomes manageable.

Hierarchy structure can Hierarchy structure can be represented in all be represented in all the three domains the three domains separately.separately.

It is important that It is important that hierarchy of different hierarchy of different domains should match domains should match into each other easily.into each other easily.

Consider the Consider the Structural Structural hierarchical hierarchical decomposition decomposition of a 16-bit of a 16-bit adder in adder in physical physical description description domain.domain.

4 bit adder

add1 add1 add1 add1

Sum

Carry

Sum Sum Sum

CarryCarry Carry

AND ORBehavioural and physical hierarchies can similarly be shown and they can be interrelated with the structural decomposition.

Regularity, Modularity and Regularity, Modularity and LocalityLocality

Regularity : Hierarchical Regularity : Hierarchical decomposition of a large system into decomposition of a large system into simple and similar blocks.simple and similar blocks.

Modularity : Well-defined Modularity : Well-defined functionality and signal interface.functionality and signal interface.

Locality : Avoids long interconnect Locality : Avoids long interconnect delays.delays.

RegularityRegularity

(a)(a) Regular design of 2:1 Regular design of 2:1 MUXMUX

(b)(b) Regular design ofRegular design of D-D-FFFF

Regularity usually Regularity usually reduces no. of reduces no. of different modules different modules that need to be that need to be designed and verified designed and verified at all levels of at all levels of abstraction.abstraction.

5. VLSI Design Styles5. VLSI Design Styles

Field Programmable Gate Array Field Programmable Gate Array (FPGA)(FPGA)

Gate Array DesignGate Array Design Standard-Cells Based DesignStandard-Cells Based Design Full Custom designFull Custom design

Field Programmable Gate ArrayField Programmable Gate Array (FPGA)(FPGA)

FPGA…FPGA… The complexity of an FPGA chip is typically The complexity of an FPGA chip is typically

determined by the no. of CLBs it contains.determined by the no. of CLBs it contains. The size of CLB varies from 8x8 (64) to The size of CLB varies from 8x8 (64) to

32x32 (1024).32x32 (1024). FPGA can support clock frequencies upto FPGA can support clock frequencies upto

100s of MHz.100s of MHz. No physical manufacturing.No physical manufacturing. Very short turn around time.(start of Very short turn around time.(start of

design process to functional chip design process to functional chip availability)availability)

Higher priceHigher price Preferred for small volume ASIC chips or Preferred for small volume ASIC chips or

for fast prototyping.for fast prototyping.

FPGA Design CycleFPGA Design Cycle

1.1. Behavioural description of functionality (HDL)Behavioural description of functionality (HDL)2.2. Generation of synthesized architectureGeneration of synthesized architecture3.3. Technology mapping into circuits or logic cellsTechnology mapping into circuits or logic cells4.4. Assignment of various logic cells to FPGA sites Assignment of various logic cells to FPGA sites

(CLBs) by placement and routing(CLBs) by placement and routing5.5. Determining routing patterns according to Determining routing patterns according to

netlist.netlist.6.6. Simulation and verification of on chip Simulation and verification of on chip

performance performance 7.7. Downloading design for programming of FPGA Downloading design for programming of FPGA

chip. (Remains valid till reprogrammed or power chip. (Remains valid till reprogrammed or power off)off)

Gate ArrayGate Array Higher turn around time as compared to FPGAs.Higher turn around time as compared to FPGAs. Requires metal mask design and processing for design implementation.Requires metal mask design and processing for design implementation. Generic (std) masks result in arrays (rows) of uncommitted transistors.Generic (std) masks result in arrays (rows) of uncommitted transistors. These uncommitted chips are stored for later optimization / These uncommitted chips are stored for later optimization /

customization.customization. Defining metal interconnects between the transistors of the array to Defining metal interconnects between the transistors of the array to

realize the logic function.realize the logic function. There are dedicated There are dedicated channels and multiple channels and multiple metal layers for metal layers for intercell routing intercell routing between rows or between rows or columns.columns.

Interconnection Interconnection patterns that perform patterns that perform basic logic gates can basic logic gates can be stored in a library.be stored in a library.

Some GA platforms Some GA platforms contain dedicated contain dedicated memory arrays to memory arrays to allow high density.allow high density.

Utilization factor: used Utilization factor: used chip area by total chip chip area by total chip area: higher than FPGA area: higher than FPGA

More scope for More scope for customization.customization.

Standard-Cells Based DesignStandard-Cells Based Design Requires development of full Requires development of full

custom mask set.custom mask set.

Also k/a polycell.Also k/a polycell.

Std cell library contains Std cell library contains designed, characterized and designed, characterized and customizd std logic cells in customizd std logic cells in different versions (difference different versions (difference in size, capabilities, fanouts in size, capabilities, fanouts etc)etc)

Different characterization categories include delay time Vs load Different characterization categories include delay time Vs load capacitance, Circuit / timing / fault simulation model, cell data, capacitance, Circuit / timing / fault simulation model, cell data, mask data etc.mask data etc.

For automated cell placement and intercell connections, each cell For automated cell placement and intercell connections, each cell layout has fixed height. layout has fixed height.

Power and gnd rails run along the periphery Power and gnd rails run along the periphery

i/p-o/p pins are located at boundaries of the cells.i/p-o/p pins are located at boundaries of the cells.

Chip logic design Chip logic design using std cells from using std cells from librarylibrary

Placement of cells Placement of cells and and interconnections interconnections

Extraction of Extraction of circuit models from circuit models from chip layout.chip layout.

Timing simulation Timing simulation and analysisfor and analysisfor identifying critical identifying critical paths .paths .

Resizing of gates Resizing of gates for meeting the for meeting the timing timing requirements.requirements.

Full Custom DesignFull Custom Design No use of any libraryNo use of any library

Geometry, orientation and Geometry, orientation and placement of transistor is to be placement of transistor is to be done by the designer.done by the designer.

Less design productivityLess design productivity

High design cycle timeHigh design cycle time

High labor costHigh labor cost

Rarely used Rarely used

Memory design is very rigorous Memory design is very rigorous with very less options for with very less options for improvement in chip densityimprovement in chip density

For design of high volume For design of high volume products like memory chips, products like memory chips, high performing high performing microprocessors, FPGA masters microprocessors, FPGA masters etc.etc.

Concept of design reuse is Concept of design reuse is becoming popular to reduce becoming popular to reduce design cycle time and design cycle time and development cost.development cost.

Design QualityDesign Quality Testability:Testability:Fabricated chips should be fully testable to ensure that all the Fabricated chips should be fully testable to ensure that all the

chips can be inserted into the system without causing chips can be inserted into the system without causing failures.failures.

With increase in the complexity of the system, additional With increase in the complexity of the system, additional circuit for self testing is to be fabricated on the chip. This circuit for self testing is to be fabricated on the chip. This increases area and offers some speed penalty.increases area and offers some speed penalty.

YieldYield::Yield is the ratio of good tested chips to total tested chips, Yield is the ratio of good tested chips to total tested chips,

assuming test procedure is flawless. But this does not really assuming test procedure is flawless. But this does not really reflect the correct quality of design or processing. So, Yield reflect the correct quality of design or processing. So, Yield is defined as the ratio of good tested chips to total chip is defined as the ratio of good tested chips to total chip sites available at the start of the wafer processing.sites available at the start of the wafer processing.

Chip Yield:-Chip Yield:-1)1) Functional Chip Yield:Functional Chip Yield: Obtained by testing the Obtained by testing the

functionality of chip at a speed less than chip speed. Points functionality of chip at a speed less than chip speed. Points the problems related to shorts, opens, leakage currents, the problems related to shorts, opens, leakage currents, logic and circuit design faults.logic and circuit design faults.

2)2) Parametric Yield:Parametric Yield: Performed at chip speed on the chips Performed at chip speed on the chips that passed functionality test.. Delay testing is performed at that passed functionality test.. Delay testing is performed at this stage.this stage.

Reliability:Reliability:Major causes for chip reliability problems are:Major causes for chip reliability problems are:

1.1. Electrostatic discharges and electrical overstressElectrostatic discharges and electrical overstress

2.2. ElectromigrationElectromigration

3.3. Latch up in CMOS I/O and internal circuitsLatch up in CMOS I/O and internal circuits

4.4. Hot-carrier induced agingHot-carrier induced aging

5.5. Oxide breakdownOxide breakdown

6.6. Single event upsetSingle event upset

7.7. Power and ground bouncingPower and ground bouncing

8.8. On chip noise and cross talkOn chip noise and cross talk

Good manufacturer should weed out such potential failures Good manufacturer should weed out such potential failures during the accelerated reliability test.during the accelerated reliability test.

Technology UpdatabilityTechnology Updatability::

Due to rapid progression in process technology, chip products Due to rapid progression in process technology, chip products often have to be updated to new design rules.often have to be updated to new design rules.

Design style should be chosen so as to update the functional Design style should be chosen so as to update the functional modules for quick design reuse with minimum cost.modules for quick design reuse with minimum cost.

CAD TechnologyCAD Technology Essential for timely development of ICs.Essential for timely development of ICs.

Time consuming and computation intensive Time consuming and computation intensive parts of the design can be executed by CAD parts of the design can be executed by CAD tools.tools.

Lack of creative and inventive parts of the Lack of creative and inventive parts of the design activities.design activities.

Types of CAD tools:Types of CAD tools:1.1. High level synthesisHigh level synthesis2.2. Logic synthesisLogic synthesis3.3. Circuit optimizationCircuit optimization4.4. LayoutLayout5.5. SimulationSimulation6.6. Design rules CheckingDesign rules Checking7.7. Formal verificationFormal verification

Synthesis tools: Synthesis tools: Address the automation of design phase in Address the automation of design phase in

the top level of design hierarchy. Ex: HDLsthe top level of design hierarchy. Ex: HDLs Logic synthesis and optimization tools are Logic synthesis and optimization tools are

developed and customized for a particular developed and customized for a particular design requirement.design requirement.

Layout tools:Layout tools: The layout CAD tools include floorplanning, The layout CAD tools include floorplanning,

place and route and module generation.place and route and module generation.

DRC checking CAD:DRC checking CAD: This category includes tools for layout This category includes tools for layout

rules checking, electrical rules checking rules checking, electrical rules checking and reliability rules checking.and reliability rules checking.

Simulation and Verification tools:Simulation and Verification tools: Include circuit level, timing level, logic level, Include circuit level, timing level, logic level,

behavioral level, device level and process level behavioral level, device level and process level simulation tools.simulation tools.

Aim to determine if the designed circuit meets Aim to determine if the designed circuit meets required specifications at all stages of the required specifications at all stages of the design process.design process.

Logic simulation is performed to verify Logic simulation is performed to verify functionality of the circuit. (at gate level of functionality of the circuit. (at gate level of abstraction)abstraction)

Circuit level or electrical simulation tools Circuit level or electrical simulation tools determine the nominal and worst case delays, determine the nominal and worst case delays, critical delay paths, and to predict the influence critical delay paths, and to predict the influence of parasitic effects on the circuit behavior.of parasitic effects on the circuit behavior.

Exercise:Exercise:

1.1. Technical note on Packaging Technical note on Packaging TechnologyTechnology

2.2. Study article no. 1.3 from Kang’s Study article no. 1.3 from Kang’s bookbook