IFST 200519-21 June 2005, Yokohama, Japan

Overview of Future Memory Devices - from Stacked Memory, Gain Memory,

SEM to Molecular Memory

Kazuo Nakazato

Nagoya University

SRAM DRAM FLASHhigh-speed low cost

high-densitylow cost

high-density

server, CPUcache memory

computermain memory replacement of hard disk

ROMmobile equipment

high-speed

Memory

Feature

Application

Memory Cell

low power

Semiconductor Memories

6 - 8 F2 4 - 10 F2130 F2

10 ns 40 ns 10 μs

Cell Size

Access Time

Source/Drain

substrate MOSFET

Gate

Stacked Vertical

MOSFET

insulator

Via

Stacked Vertical MOSFET

Stacked Vertical MOSFET

substrate MOSFET

no PWELL-NWELL isolation

pMOSFET

nMOSFETStacked Vertical

MOSFET

polycrystalline silicon channel

performance degradation when carriers transport across grain boundaries

columnar or disc-shaped grains

vertical carrier flow mainly without crossing any grain boundaries

stacked

Why Stacked Vertical ?

グレイン

バンダリ

グレイン

バンダリ

伝導帯

価電子帯

深い準位

ΨB= 8εs pqNST

2

ΨB : barrier height of grain boundaryNST : trap density at grain boundaryεs : silicon permittivityp : carrier density

3-d Memory Cell

grain boundary

EC

EV

deep level

gate oxide

source

drain

gate

gate

SiO2

polycrystalline silicon

channel

ON current [μA]0 50 100

3μm

3σ

2σ

σ

0

-σ

-2σ

-3σCum

ulat

ive

Pro

babi

lity

Example of Distribution of Grain-boundaries

measuredanalysis from the distribution of grain boundaries

Distribution of ON currents of SV-MOSFET

transistor size(0.2μmx0.2μm)

plan view

cross sectional view

300n

m

pMOS 1.2VW=2μm

show very similar to single-crystal MOSFET

1.E-15

1.E-14

1.E-13

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

-4 -3 -2 -1 0 1 2 30.E+00

1.E-04

2.E-04

3.E-04

4.E-04

5.E-04

0 1 2 3

1V0.1V

VDS=2V

VGS [V]

I DS

[A/μ

m]

VDS [V]I D

S[A

/μm

]

3V

2V

1V

VGS=

measureddevice simulation with 300 cm2/Vs

Idealsubthreshold slope~ 60 mV/dec.

Low OFF current

High ON current ~300μA/μm

Characteristics of SV-MOSFET

NMOS

1.E-14

1.E-13

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

-1.5-1.0-0.50.00.5

Vg[V]-Id[A/cell]

Characteristics of p-type SV-MOSFET stacked on substrate MOSFET

substrate MOSFETsubstrate MOSFET

0.0 0.1 0.2 0.3 0.4 0.5.01

.1

1

5102030

50

70809095

99

99.9

99.99

Vth [V]

累積頻度　(%)

SVMOSFET

substrate MOSFET

0.06 0.07 0.08 0.09 0.10 0.11.01

.1

1

5102030

50

70809095

99

99.9

99.99

subthreshold voltage slope [V/dec]

累積頻度　(%)

SVMOSFET

substrate MOSFET

SVSV--MOSFETMOSFET

1.E-14

1.E-13

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

-1.5-1.0-0.50.00.5

Vg[V]

-Id[A/cell]

SVMOSFET

substrate MOSFET

VDS=-1.2V, RT

VDS=-1.2V, RTH Matsuoka, T Mine, K Nakazato, M Moniwa, Y Takahashi, M Matsuoka, H Chakihara, A Fujimoto, and K Okuyama, Symp. VLSI Technol. Dig. Papers 2004

PMOS

533MHz 64Mbit SRAM9kbit deficit

T Kikuchi, S Moriya, H Matsuoka, K Nakazato, A Nishida, H Chakihara, M Matsuoka, and M Moniwa, IEDM Dec. 2004

2.0

1.5

1.0

0.5

90 130 [nm]

32Mb

64Mb

128Mb

[μm2]

SRAM Ｃｅｌｌ Size vs Process Node

Conventional

SVMOS

Cell size of next generation can be achieved by the present process node

Huge investment is required for setting up next process node.Memory with minimum cell size may become standard cell finally.

Cel

l Siz

e

Process Node

Semiconductor Memories

SRAM DRAM FLASHhigh-speed low cost

high-densitylow cost

high-density

server, CPUcache memory

computermain memory replacement of hard disk

ROMmobile equipment

high-speed

Memory

Feature

Application

Memory Cell

low power

6 - 8 F2 4 - 10 F2130 F2

10 ns 40 ns 10 μs

Cell Size

Access Time

CL

(fF),

CS

(fF),

A(μ

m2 )

, VS

(V) 104

103

102

101

100

10-1

10-2

16K 256K 4M 64M 1G 16G

Memory Capacity (bits/chip)

CL

CS

AVS

DRAM 1-T cell

memory node(VDD, 0)

CS

CL

VSVDD2

bit line

word line

HM52Y64165FTT-75

cell area

VS ~ VDDCS

2CL

0

10

20

0.3 0.2 0.1 0.07 0.05minimum feature size (μm)

post DRAM

capacitor-lessFabrication Limit

aspe

ct ra

tio

1T cell

teff =0.5nm CS=30fF

post DRAM cell

J.M.Park et alIEDM 2002

VS

CS

VS

Gain Cell

memory node

large capacitor

memory node

large capacitor

100fF

0.1fF100fF

30fC 0.1fC

bit line

MOSFET

memorynode

word line

Minimum sized gain cell (~ half of DRAM 1-T cell)Stacked structure

Tunnel transistorhigh ON/OFF current ratio (high speed/long retention time)

PLEDM - memory cell

Si substrate

MOSFET

verticaltunnel

transistor

GND

word line

bit line

senseline

built-in coupling capacitor

Si Sii-Si

n+-Si

i-Si

n+-Si

gate

source

drain

barrier

insulator

(a) (b)

source

barrierdrain

shutter

gate

Conduction band energy diagramSchematic cross-sectional viewshowing device operating principle

energy

source

drain

modulationby gate bias

OFF

ON

Stacked Tunnel Transistor - PLEDTR

50nmDark field TEM

Source-barrier

Drain-barrier

SOURCE

DRAIN

GATE

Source/Drain Barriers

Impurity Diffusion Barrier from heavily doped source/drain

SOURCE

DRAIN

Diffusion constantthrough grain boundaries ismore than 100 times higherthan the diffusion constant in grain.

graingrain

741369

Effect of Source and Drain Barriers

without tunnel barrier

with tunnel barrier

Si3N4~0.8nm

CO

NC

EN

TRA

TIO

N

(ato

ms/

cc)

DEPTH(μm)0 0.5 1

intrinsic-Si

tunnel barrier

n+ -Si n+ -Si

CO

NC

EN

TRA

TIO

N

(ato

ms/

cc)

1021

1020

1019

1018

1017

1016

1015

1021

1020

1019

1018

1017

1016

1015

0

10

20

Vth (V)-1 0 1 2

Num

ber

0

10

20

30

40

50

60

Vth (V)-1 0 1 2

Num

ber

distribution of threshold voltage

μ= 43.3 cm2/Vsμ= 100 cm2/Vs

limited limitedmobility tunnel barrier

ON

cur

rent

(arb

. uni

t)

0 1 2

ON current

thickness of Si3N4 tunnel barrier (nm)

1

0.1

0.01

0.001

0.0001

0.00001

10

low pressure rapid thermal nitridation

1time (min.)

thic

knes

s (n

m)

0.8

direct nitridation of silicon

<< 1min.

>> 1min.

source barrier

drain barriershutter barrier

self-limiting growth

Formation of Stable Thin Tunnel Barriers

VDS =1.5V1μ

1n

1p

1f0 1 2

VGS (V)

I DS

(A)

3

source

drain

gate

barriers

45nm

60nm

0 1 2VDS (V)

301

234

I DS

(μA)

VGS =3V2.8V2.6V2.4V2.2V2V

60 nm channel PLEDTR

K Nakazato, K Ito, H Mizuta, and H AhmedElectron. Lett., 35 (1999), pp.848-850

I/O

VDD

φp

φY

φRW

VW1

VW2

VN1VN2

VDW

VDR

100fF100fF

VW

1φ p

φ RW

I/Oφ Y

VN

1 (V

)V

N2

(V)

VD

R (V

)V

DW

(V)

0 100 200

t (nsec)

high

low

WH WL

S R r S R rS R S R

Vth

0

0

0

0

0

0

1

0

1

01

-1-2

01

-1-2

Operation of PLEDM device

MOSFET

PLEDTR

VDS =1.5V1m

1μ

1n

1p

1f-1 0 1 2

VGS (V)

I DS

(A)

Vth

MOSFET

PLEDTR

VDS =1.5V1m

1μ

1n

1p

1f-1 0 1 2

VGS (V)

I DS

(A)

Vth

plan view cross sectional view

SiO 2

metal

n+

bit lineword line

p+-Si

Si substrate

Memory Cell Layout

DRAM 1-T cell 6-8F2

Unit cell2.5F x 2F = 5F2

1M 4M 16M 64MDRAM 1-T

256M

1G

PLEDM

SEM: single-electronmemory

107

Electron Number / bit

106

105

104

103

102

10

1

high-εcapacitor

1990 2000 2010 2020

Year

4G 16G 64G

3DCapacitor

withoutcapacitor

1T

gaincell

chargingenergy

SEM

Electron Number Stored in a Memory Cell

2Ce2

energy

eV

V

electron flow rate

Coulombblockade region

zero voltage

voltage applied

0

EC

E =C

Charging energy by one electron

VC

Coulomb gapvoltageV ~ E /eC C

Coulomb Blockadetunnel barrier

small island

memory node Cg

Vg

CSmultiple-tunnel-junction

V

I

0 VC

-VC

Coulomb blockade

eVC = 2Ce 2

Single-electron Memory

Cou

lom

b bl

ocka

deVg

memory-node voltage V

constant electron-number on memory node

V =Cg Vg – e n

C

C + Cg + CS

tunnel barriersmall island

T = 4.2K

Cur

rent

(nA)

offset 10nA per 0.1V gate step

VDS (V)

T = 4.2K

Cur

rent

(nA)

offset 10nA per 0.1V gate step

VDS (V)

SiO2Si substrate

Single-crystal Si, doped with P 1019cm-3

30nm

Silicon In-plane Gate Multiple-Tunnel-Junction

40nm

Electron islands Tunnel

junctions

Ionized donor

10 nm

20 nm400 nm

Naturally formed Electron Islands

• heavily doped silicon nanowire• Randomly distributed dopants• Self-consistent calculation with

Thomas-Fermi approximation

G. J. Evans, H. Mizuta, and H. Ahmed, Jpn. J. Appl. Phys. 40, pp. 5837-5840 (2001)

R. J. Blaikie, K. Nakazato, R. B. S. Oakeshott, J. R. A. Cleaver, and H. Ahmed, Appl. Phys. Lett. 64, pp. 118-120 (1994)

VDT

IDD

VG

IDD

VGVDT

electron storage node

VDT (Volts)

I DD

(nA)

-0.12 0.120

1

0

VG (Volts)

I DD

(nA)

-3.3 -3.2 -3.1 -3

1

0-2.9

Si Single-electron Memory

< 30nm

N. J. Stone and H. Ahmed, Appl. Phys. Lett. 77, pp. 744-746 (2000)

0.1

0.3

0.5

0.7

-0.03 0 0.03

Ele

ctro

met

er o

utpu

t I D

D(n

A)

Write line Voltage VDT (V)

0.2

0.3

0.4

-0.02 0 0.02

Ele

ctro

met

er o

utpu

t I D

D(n

A)Write line Voltage VDT (V)

one bit = one electron

bit l

ine,

VB

word line, VW

memory node

IS

bit l

ine,

VB

word line, VW

memory node

ISVB - VW

VW

VB

write “0” write “1”

VB - VW

VW

VB

write “0” write “1”

4.2K

70

80

90

100

0.4 0.6 0.8 1 1.2

time (sec)

I S(n

A)

VW

VB

4.2K

70

80

90

100

0.4 0.6 0.8 1 1.2

time (sec)

I S(n

A)

VW

VB

124

126

128

130

0 100 200 300

I S(n

A)

time (sec)

124

126

128

130

0 100 200 300

I S(n

A)

time (sec)

Random Write to Single-electron Memory Cell Array

write pulse width = 5ns

N J Stone, H Ahmed, and K Nakazato,IEEE EDL 20, pp. 583-585, 1999

3x3 bit L-SEM array0 0.5 1 1.5 2 2.5

time (s)

-0.2

0

0.2

0.4

0.6

0.8

'0''1'

'0'

1.01.5

2.0

2.5

3.0

5.0

Volta

ge (V

) 4.0

3.0

2.0

1.0

0

'0'Vo

ltage

(V)

IDS

(μA

)IDS0

VRWL

VWWL

VD

VSVD0

VS0

IDS

Single-electron Transistor – CMOS Hybrid Memory Array

high-drivability

single-electron control

Z. A. K. Durrani, A. C. Irvine, H. Ahmed, and K. Nakazato, Appl. Phys. Lett. 74, pp. 1293-1295 (1999)

109

106

103

100

10-3

10-6

10-9

0 0.5 1.0island size [nm]

rete

ntio

n tim

e [s

ec]

0.5nm

110C

1.5

Molecular Single-electron Memory

Molecular single-electron memory

Self-assembled monolayerdonor-(π-bridge)-acceptor dye

Collaboration with Cranfield University, U.K.

S(CH2)10

N

HCN

NCN

C

(CH2)n

S(CH2)10N

HCN

N

CN

(CH2)n

Au

Au

Au

C

Current–voltage characteristics of a self-assembled monolayer on a gold-coated substrate and investigated using a decanethiol-coated gold tip.

PLEDM

(1993)

multiple-tunneljunction

(2001)

0.2μm

2nm

commercialsingle-electron

memory

commercialsingle-electron

memory

First-demonstratedexperimental

single-electron memory

First-demonstratedexperimental

single-electron memory

sense transistor

precise controlof electrons

+large drivability

Summary

gate oxide

source

drain

gate

gatechannel

SVMOS

(2004)

molecularsingle-electron memory

tunnelbarrier