Overall Roadmap Technology Characteristics (ORTC) 2012 1 Alan Allan Winter Hsinchu Public Conference...

Overall Roadmap Technology Characteristics(ORTC) 2012

1

Alan Allan

Winter Hsinchu Public ConferenceRev 4, 12/05/12

Hsinchu Public Conference, Rev 4, 12/05/12

2012 ITRS WINTER PUBLIC CONFERENCEWednesday 5 December – Ambassador Hotel, HsinChu, Taiwan

Hosted by the TSIAJointly Sponsored by ESIA, JEITA, KSIA, SIA, TSIA, and SEMATECH

MORNING SESSIONS8:00-8:45 Registration and Continental Breakfast8:45-9:00 Opening Remarks & Orientation

TSIA Chair and ITRS Chairman Carlos Diaz and Paolo GarginiRegional Greetings by the International Roadmap Committee (IRC)ESIA Bert HuizingJEITA Hidemi IshiuchiKSIA Paolo Gargini (acting)TSIA Carlos DiazSIA Alan Allan

9:00 Session 1 Greetings by Europe IRC Bert Huizing9:00-9:15 Overall Roadmap Technology

CharacteristicsAlan Allan

9:15-9:30 More than Moore Bert Huizing9:30-10:00 System Drivers and Design Andrew Kahng10:00-10:15 Metrology Yaw Obeng10:15-10:25 Q&A10:25-10:45 Morning Break

Session 2 Greetings by Japan IRC Hidemi Ishiuchi10:45-11:00 Emerging Research Materials Mike Garner11:00-11:15 Emerging Research Devices An Chen11:15-11:30 Interconnect Paul Zimmerman11:30-11:45 Yield Enhancement Lothar Pfitzner11:45-11:55 Q&A12:00-13:30 Lunch


2012 ITRS WINTER PUBLIC CONFERENCE

Wednesday 5 December – Ambassador Hotel, HsinChu, TaiwanHosted by the TSIA

Jointly Sponsored by ESIA, JEITA, KSIA, SIA, TSIA, and SEMATECH

AFTERNOON SESSIONS

Session 3 Greetings by Korea IRC Paolo Gargini (acting)13:30-13:45 Environment, Safety, and Health Steve Moffat13:45-14:00 Test & Test Equipment Roger Barth14:00-14:15 MEMs Michael Gaitan14:15-14:30 RF and A/MS Technology Michael Gaitan14:30-14:40 Q&A

14:40-15:00 Afternoon Break

Session 4 Greetings by Taiwan IRC Carlos Diaz15:00-15:15 Front End Processes Mike Walden15:15-15:30 Factory Integration Jonathan Chang15:30-15:45 Assembly and Packaging Bill Bottoms15:45-16:00 Process Integration, Devices, & Structures Rich Liu16:00-16:10 Q&A

Session 5 Greetings by USA IRC Alan Allan (acting)16:10-16:25 Lithography Tatsuo Chijimatsu16:25-16:40 Modeling & Simulation Jürgen Lorenz16:40-16:45 Q&A

16:45-17:00 Open Discussion and Closing Remarks Paolo Gargini17:00 Adjourn Carlos Diaz


20 Years Of Technology Roadmap

• 1991. First NTRS workshop• 1992. 11 TWGs established. First edition of NTRS• 1994, 1997. Second and third NTRS editions• 1998. WSC approves internationalization of NTRS-

>ITRS with Europe, Japan, Korea and Taiwan participation

• ITWGs established• 3 workshops/year (Europe, US, and Asia)• 2012 ITRS underway with 17 ITWGs

4Hsinchu Public Conference, Rev 4, 12/05/12

2012 ITRS Meetings

Spring Meeting• April 23-25.Holland.

Summer Meeting• July 8,9. Workshop in Monterey, CA• July 12. Presentations within SEMI West

Winter Meeting• Dec 3-5 Taiwan• Dec 3,4. Workshop• Dec 5th. Public presentation


2012 ITRS ITWGs1. System Drivers2. Design3. Test & Test Equipment4. Process Integration, Devices, & Structures5. RF and A/MS Technologies 6. Emerging Research Devices7. Emerging Research Materials8. Front End Processes9. Lithography10. Interconnect11. Factory Integration12. Assembly & Packaging13. Environment, Safety, & Health14. Yield Enhancement15. Metrology16. Modeling & Simulation17. MEMs


7

2012 Update Figure X: Production Ramp-up Model and Technology/Cycle Timing

Months0-24

AlphaTool

12 24-12

BetaTool

Pre-ProductionTool

First Conference

Papers 2

20

200

2K

20K

200K

AdditionalLead-time: ERD/ERMResearch and PIDS Transfer

Volume (W

afers/Month)

Source: Semiconductor Industry Association. The International Technology Roadmap for Semiconductors, 2011 edition. SEMATECH: Albany, NY, 2011. Based on Figure 2a, Executive Summary

2012 UpdateNote:Fewer leadingIDM companies requiresadaption of definitionto allow oneIDM companyor a foundry representingmany fabless companiesto lead atechnology production ramp timing

First 1–2 CompaniesReaching

Combined Production

“Risk Start” Production

Development Production HVM*

*High Volume Manufacturing (HVM)


8

Months

Development Production

BetaTool

Pre-Production

Tool

Volume (W

afers/Month)

2

20

200

2K

20K

200KResearch

-72 0 24-48 -24-96

Transfer to PIDS/FEP(96–72 mo.Leadtime)

First Technical Conference

Device PapersUp to ~12 yrs

Prior to Product

20192017201520132011 2021*III/V Hi-m Channel Timing Example

1st 1–2 Companies

Reach Product*

AlphaTool

First Technical Conference

Circuits PapersUp to ~ 5 yrs

Prior to Product

Source: Semiconductor Industry Association. The International Technology Roadmap for Semiconductors, 2011 edition. SEMATECH: Albany, NY, 2011. Based on Figure 2b, Executive Summary

High Volume Manufacturing (HVM)

HVM


2012 Update Figure Y: A Typical Technology Production “Ramp” Curve for ERD/ERM Research and PIDS Transfer Timing * including an example for III/V Hi-Mobility Channel Technology Timing Scenario


9

2012 Update (from 2011 ITRS): Equiv Scaling & “Node Alignment” vs. ITRS Timing Trends

MetalHigh kGate-stack

material

2009 2012 2015 2018 2021

Bulk

FDSOI

Multi-gate(on bulk or SOI)Structure

(electrostatic control)

Channelmaterial

MetalHigh k

2nd generation

Si + Stress

S D

High-µInGaAs; Ge

S D

PDSOI

MetalHigh k

nth generation

PossibleDelay

Possible Pull -in

68nm 45nm 32nm 22nm 16nm2011 ITRS DRAM M1 :

2011 ITRS MPU/hpASIC M1 : 76nm 65nm 54nm 45nm 38nm 32nm 27nm 19nm 13nm

MPU/hpASIC “Node”: “45nm” “32nm” “22/20nm” “16/14nm” “11/10nm” “8/7nm”

2011 ITRS hi-perf GLph : 32nm 29nm 29nm 27nm 24nm 22nm 20nm 15nm 12nm

2011 ITRS hi-perf GLpr : 54nm 47nm 47nm 41nm 35nm 31nm 28nm 20nm 14nm

45nm 32nm 11nm2011 ITRS Flash Poly : 54nm2011 ITWG Table Timing: 2007 2010 2013 2016 2019 2021 22-24

8nm

20248nm

22nm 15nm

11nm

Source: 2011 ITRS - Executive Summary Fig 5

[ PIDS/FEP/DesignHP/LOP/LSTP

Sub-Team Transistor Modeling Work Underway for

2013 ITRS ]

PIDS Acceleration - for 2012 ITRS Update

2012 UpdateNote: Leadership company First Manu-facturingcould set more Aggressive first production target, since “fast followers” may trail 1–3 years


10


1

10

100

1000

1995 2000 2005 2010 2015 2020 2025 2030

Nan

om

eter

s (1

e-9)

Year of Production

2011 ITRS - Technology Trends

2011 ITRS Flash ½ Pitch (nm) (un-contacted Poly) -[2-yr cycle to 2009; then 8-yr cycle to 2020; then 3-yr cycle to 2022/8nm; then flat]

2011 ITRS DRAM ½ Pitch (nm) (Contacted M1) -[2.5-yr cycle to 2008; 45nm pull-in to 2009; then 3-yr cycle to 2026]

2011 ITRS: 2011-2026

3D - 8 layers

3D - 128 layers

PIDS 3DFlash :

Looser Polyhalf-pitch

2016-18/32;Then

2019-21/28nmThen

2022-25/24nmThen

2025-26/18nm~5.5-yr

Cycle

Long-Term ’19-’26

16nm

3D -16layers/48nm

3D -256layers/24nm4-yr cycle

5.5-yr cycle


11

1

10

100

1000

1995 2000 2005 2010 2015 2020 2025 2030

Nan

om

eter

s (1

e-9)

Year of Production


2009/10/11 ITRS MPU/ASIC Metal 1 (M1) ½ Pitch (nm) [historical trailing at 2-yr cycle; extended to 2013; then 3-yr cycle]

2009/10/11 ITRS MPU Printed Gate Length (GLpr) (nm) [3-yr cycle from 2011/35.3nm]

2009/10/11 ITRS MPU Physical Gate Length (nm) [begin 3.8-yr cycle from 2009/29.0nm]

2011 ITRS: 2011-2026


16nm

2011 ITRS Figure 4 Unchanged for 2012 – ORTC Table 1 Graphical Trends – Logic (MPU and high-performance ASIC) Half Pitch and Gate Length



12

1

10

100

1000

1995 2000 2005 2010 2015 2020 2025 2030

Nan

om

eter

s (1

e-9)

Year of Production





2011 ITRS: 2011-2026


16nm

2011 ITRS Figure 4 Unchanged for 2012 – ORTC Table 1 Graphical Trends – Logic (MPU and high-performance ASIC) Half Pitch and Gate Length



13

1

10

100

1000

1995 2000 2005 2010 2015 2020 2025 2030

Nan

om

eter

s (1

e-9)

Year of Production





2011 ITRS: 2011-2026


16nm

Transistor Gate TechnologyPower-performance Management Enabled by “Equivalent Scaling”

“Moore’s Law” Enabled byTransistor M1 Half Pitch Dimension Technology


Updated MPU/DRAM OptionsFigure LITH3A DRAM and MPU Potential Solutions

First Year of IC Production 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026

DRAM ½ pitch (nm) (contacted) 36 32 28 25 23 20.0 17.9 15.9 14.2 12.6 11.3 10.0 8.9 8.0 7.1 6.3

MPU/ASIC Metal 1 1/2 pitch (nm) 38 32 27 24 21 18.9 16.9 15.0 13.4 11.9 10.6 9.5 8.4 7.5 7.5 7.5

45 193nm Imm

32 193 nm DP

22 EUV193nm MPML2 (MPU)

16 EUV193nm MPML2DSA + LithoImprint

11 EUV higher NA / EUV + DPML2DSA + LithoEUV (new wavelength)ImprintInnovation

Narrow Options

Narrow Options

Narrow Options

MPU / DRAM time line

We will narrow options for 22nm hp in 2013.

14


Updated Flash Options

This table shows the requirements for 2-D flash development. The potential introduction of 3-D flash does not drive lithography.

Figure LITH3B Flash Potential Solutions

First Year of IC Production 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026

Flash ½ Pitch (nm) (un-contacted Poly)(f) 22 20 18 17 15 14 13 12 11 10.0 8.9 8.0 8.0 8.0 8.0 8.0

32 193 nm DP

22 193 nm DP

16 193nm MPEUV

Imprint

11 EUV higher NA / EUV + DP193nm MPDSA + LithoEUV (new wavelength)ImprintInnovation

Narrow Options

Narrow Options

NAND Flash Time Line

15


16

*Note: the IRC recommended updating the ITRS 450mm Timing Graphic for use in the 2011 ITRS Special Topic and 2012 Update Roadmap guidance; based on SEMATECH guidance

AlphaTool

BetaTool

Silicon is supporting development using partially-patterned and processed test wafers

Manufacturing

Demonstrations focus on 1xnm M1 half-pitch capable tools

Consortium

IDM and FoundryPilot Lines

IDM/Foundry Pilot Line

Pre-Production Tools

IDM/Foundry Pilot Line Beta Tools

Development Demonstration Production

2010 2011 2012 2013 2014 2015 2016

Increasing 450mm Silicon Demand From Demonstrations

HVM


Source: Semiconductor Industry Association. The International Technology Roadmap for Semiconductors, 2011 edition. SEMATECH: Albany, NY, 2011. Based on Figure 6, Executive Summary


Volume (W

afers/Month)

2013 Proposal Figure Z [to replace WAS: 2012 ITRS Fig Z]: A Typical Wafer Generation Pilot Line and Production “Ramp” Curve applied to Forecast Timing Targets of the 450 mm Wafer Generation


17


PilotProductionReady**

AlphaTool

BetaTool



2013 ITRS Proposal [IS]**2016-17: Pilot Lines[**Source: Public

Announcements, Sep’12]

[IS]**2018: High-

Volume (HVM)

Production

*Consortium Position Regarding 450mm Production: “Development by Suppliers is under way with support coordinated by 450mm consortium and the target to demonstrate a 450mm tool set ready for pilot operations by the end of 2014 – IC Makers are driving commercial pilot line** and HVM timing based on business considerations and tool readiness.”**

Consortium

Years


[WAS]

Manufacturing

2010 2011 2012 2013 2014 2015 2016 2017 2018

Development Demonstration …Production [IS]*…

[IS] “Risk Start”Production[IS]

“HVM”Production[IS]



Pre-Production Tools Set Ready*

IDM/Foundry

Pilot Line BetaTools

HVM

“HVM”Production[WAS]

“Risk Start”Production[WAS]


Volume (W

afers/Month)


18

PilotProductionReady**

AlphaTool

BetaTool



2013 ITRS Proposal [IS]**2016-17: Pilot Lines[**Source: Public

Announcements, Sep’12]

[IS]**2018: High-

Volume (HVM)

Production

*Consortium Position Regarding 450mm Production: “Development by Suppliers is under way with support coordinated by 450mm consortium and the target to demonstrate a 450mm tool set ready for pilot operations by the end of 2014 – IC Makers are driving commercial pilot line** and HVM timing based on business considerations and tool readiness.”**

Consortium

Years


“Risk Start”Production[IS]

“HVM”Production[IS]

Manufacturing

2010 2011 2012 2013 2014 2015 2016 2017 2018

Development Demonstration …Production [IS]*…



Pre-Production Tool Set Ready*

IDM/Foundry

Pilot Line BetaTools

HVM


Volume (W

afers/Month)



More than Moore: DiversificationM

ore

Mo

ore

: M

inia

turi

zati

on

Combining SoC and SiP: Higher Value SystemsBa

se

lin

e C

MO

S:

CP

U,

Me

mo

ry,

Lo

gic

BiochipsSensors

Actuators[e.g. MEMS]

HVPower

Analog/RF Passives

130nm

90nm

65nm

45nm

32nm

22nm

16 nm...V

Information Processing

Digital contentSystem-on-chip

(SoC)

Beyond CMOS

Interacting with people and environment

Non-digital contentSystem-in-package

(SiP)

Source: 2011 ITRS - Exec. Summary Fig. 4

Figure 4 The Concept of Moore’s Law and More


More than Moore: DiversificationM

ore

Mo

ore

: M

inia

turi

zati

on

Combining SoC and SiP: Higher Value SystemsBa

se

lin

e C

MO

S:

CP

U,

Me

mo

ry,

Lo

gic

BiochipsSensors

Actuators[e.g. MEMS]

HVPower

Analog/RF Passives

130nm

90nm

65nm

45nm

32nm

22nm

16 nm...V

Information Processing

Digital contentSystem-on-chip

(SoC)

Beyond CMOS

Interacting with people and environment

Non-digital contentSystem-in-package

(SiP)

Source: 2011 ITRS - Exec. Summary Fig. 4

Figure 4 The Concept of Moore’s Law and More

20

Processor

Memory

RF

MEMS

Si Interposer


1) Unchanged for 2012: MPU contacted M11) 2-year cycle trend through 2013 [27nm (“14nm” node)]; then 3-year trend to 20262) 60f2 SRAM 6t cell Design Factor3) 175f2 Logic Gate 4t Design Factor4) Proposal Consideration for 2013 ITRS: Extension of 2-year M1 Trend2) Unchanged for 2012 Tables: MPU Functions/Chip and Chip Size Models 1) Design TWG Model for Chip Size and Density Model trends – tied to technology

cycle timing trends and cell design factors2) ORTC line item OverHead (OH) area model, includes non-active area3) Proposal Consideration for 2013 ITRS: Extension of 2-year M1 Trend3) Unchanged for 2012 Tables: MPU GLpr, GLph – trends “smoothed” by 2011

PIDS modeling*4) Unchanged for 2012 Tables: Max Chip Frequency trends (reset in 2011 to

3.6Ghz/2010 plus 4% CAGR trend)5) Unchanged for 2012 Tables: Vdd High Performance, Low operating and standby

line items from 2011 PIDS model track “smoothed” gate length changes*

*Note: See PIDS tables for 2012 Update to be released at end of 2012 for impact due to acceleration of MugFET and FDSOI “Equivalent Scaling” timing into 2012

2012 Update ITRS ORTC Technology Trend Summary


6) Unchanged for 2012 Tables: DRAM contacted M1:1) One-year M1 acceleration2) New for 2012: 4f2 one-year delay to 2014 (affects Chip Size Model*)

7) Unchanged for 2012 Tables: Flash Un-contacted Poly:1) 2+-year pull-in of Poly; however slower 4-year cycle (0.5x per 8yrs) trend to

2020/10nm; then 3-year trend to 2022/8nm; then Flat Poly after 2022/8nm2) and 3bits/cell extended to 2018; 4bits/cell delay to 2022

8) Unchanged for 2012 Tables: DRAM Bits/Chip; Chip Size Model adjusted*:1) 3-year generation “Moore’s Law” bits/chip doubling cycle target (1-2yr delay for

smaller chip sizes <30mm2 – 2x/2.5yrs)2) *Chip Size Model adjusted for 4f2 one-year delay to 2014

9) Unchanged for 2012 Tables: Flash Bits/Chip and Chip Size Model:1) 3-year generation “Moore’s Law” bits/chip doubling cycle target (after 1-yr

acceleration; then flat @ 1-2Tbits; keep chip size <160mm2)2) 3D on-chip bit layers with relaxed half-pitch tradeoffs are included for

maximum bits per chip 1) New 2012 Update Survey Emphasis: 2016-2025 layer range from

8/32nm -128/18nm Layers to 16/48nm – 256/24nm Layers (option C in 2011 ORTC Table 2)

2012 Update ITRS ORTC Technology Trend Summary (cont.)


10) Unchanged for 2012 Tables: ORTC Table 5 - Litho # of Mask Counts MPU, DRAM, 1) Litho Survey inputs Unchanged for 20122) IC Knowledge (ICK) model contribution extends mask levels range to 2024

2) 2013 Update: update ICK model to 2011 Mask Counts11) Updated for 2012 Update [and 2013 ITRS Preparation]: IRC 450mm Timing Graphic Position: 1) Timing Status Updated for 2012 and 2013 ITRS guidance

1) Consortia work continues2) IDM and Foundry Pilot lines: 2013-14; 3) “Risk Start” Production: 2015-16 [corrected early target in 2012 Update; move to 2016 in 2013

ITRS Targets]2) G450C Consortium continues good progress on 450mm program activities to meet the ITRS Timing

1) Consortium operations are using 450mm early test wafer process, metrology and patterning capability to support Supplier development

2) 193 immersion multiple exposure litho tools are under development to support consortium and manufacturers’ schedules for target “1xnm technology” goal

3) 450mm increasing silicon demand is needed from consortium demonstrations to support development

3) Europe Position Unchanged – EEMI450 status was reviewed with IRC in Netherlands Apr’124) 300mm wafer generation in parallel line item header with 450mm; 1) Including Technology upgrade assumptions2) Assuming compatibility of 300mm productivity extensions into the 450mm generation; 5) ITRS-based ICK Strategic Model commercially available and updated to 2011 ITRS, including

300mm and 450mm 2009-2026 Range Scenarios for silicon and equipment demand 12) Unchanged for 2012 Update: More than Moore white paper online at www.itrs.net 1) MtM Workshop completed in Netherlands, in April and reviewed at Summer ITRS meeting

1) Europe workshop included new iNEMI applications presentation (by Europe iNEMI Mgr. – highlights on Automotive; Medical; Energy; Lighting; et al)

2) ITRS MEMS TWG and Chapter cross-roadmap work underway for 2013 iNEMI Roadmap

2012 Update ITRS ORTC Technology Trend Summary (cont.)


http://www.itrs.net/

Technology Pacing Cross-TWG Study Group (CTSG) 2012 work preparation for 2013 ITRS Renewal (kickoff Dec’12), including:

2013 Renewal Preparation ITRS ORTC Technology Trend Summary (cont.)

24

– IRC Equivalent Scaling Graphic Update• Updated timing placement of MuGFET, FDSOI, and III/V Ge Timing; now based on one IDM

or Foundry company, who may lead technology production ramp

– Design and FEP Logic Technology Trends• Monitor and Update MPU and Leading Edge Logic technology trends, including• Ongoing- evaluate alignment of “nodes” with latest M1 industry status• Consider High Performance vs. Low Power transistor type needs• Consider extending 2yr cycle to at least 2017/14nm (”7nm” node)• Functions/Chip and Chip Size Models tbd; based on final consensus of new proposals• On-Chip Frequency Proposals – Align with PIDS modeling and evaluate/update to industry

trends

– PIDS and FEP Memory Survey Proposal Updates • Presently unchanged for 2013 – ongoing monitor of DRAM and Flash technology trends

– Litho and FEP (and PIDS and Design) Survey for CD Variability and Control• Monitor and Update Litho and Etch Gpr/Gph Ratio for CD control trends

– A&P/Design Power (Thermal) Model• Develop proposals for Power Dissipation "hot spot" model rather than chip area basis

– PIDS/Design Max On-chip Frequency vs Intrinsic Modeling• Targeted for 8% (vs. 13%) CAGR (1/CV/I) intrinsic transistor performance (to align with 2011

ITRS 4% Design Frequency trend)• Consider Intrinsic Transistor and Ring Oscillator model Changes • Including MASTAR static modeling near-term and Purdue dynamic long-term modeling• Including “equivalent scaling” tradeoffs (FDSOI, MuGFET, III-V/Ge) with dimensional scaling

– YE Defect Density Modeling• Update ORTC Defect Density model work to latest Litho Mask Count Model – still seeking

defect modeling resources supportHsinchu Public Conference, Rev 4, 12/05/12

Summary

• The Technology Roadmap turns 20!• ITRS is a live and evolving process, mapping

semiconductor industry needs and challenges ahead of implementation

• The initial NTRS 11 chapters have became 17• The ITRS is used as a reference document by the whole

semiconductor industry• Public presentations: July 12, 2012 during SEMICON

West; and December 5, 2012 in Hsinchu Taiwan• Publicly accessible on line at www.itrs.net


http://www.itrs.net/

Public Conference Backup

• Industry Historical Gate Density and SRAM Cell Size Trends

• 2012 ITRS Gate Density and SRAM Cell Size analysis

• Work in Progress Transistor Dimensional Definitions…

26


27

1.00E-06

1.00E-05

1.00E-04

1.00E-03

1.00E-02

1.00E-01

1.00E+00

1.00E+01

1.00E+02

1.00E+03

1.00E+04

1995 2000 2005 2010 2015 2020 2025 2030

Sq

uar

e M

illi

met

ers

Year of Production

2011 ITRS - Function Size

2009 DRAM Cell area per bit (1 bits/cell) (um2)

2009 Flash SLC area per bit (1 bits/cell) [SLC cell area/1] (um2)

2009 Flash MLC Ave area per bit (2 bits/cell) [SLC cell area/2] (um2)



2011 SRAM Cell (6-transistor) Area (um2)

2011 Logic Gate (4-transistor) Area (um2)


2011 ITRS: 2011-2026

2011 ORTC Figure 6Product Function

Size Trends

[transistor + capacitor]


MPU/ASIC ITRS 2011Target 6-transistor

“22nm” Node SRAM [60f2]= 0.0859um2 cell area

@ 37.84nm M1 half-pitch0.18u x 0.48u = 0.0864um2

ITRS MPU/ASICAlignment

Design TWGActual SRAM [60f2]

& Logic Gate [175f2]

MPU/ASIC ITRS 2011Target 6-transistor

“32nm” Node SRAM [60f2]= 0.172um2 cell area

@ 53.51nm M1 half-pitch0.25u x 0.68u = 0.172um2

“22 nm”/39.8nm h-p, 0.092 um2 [= 58.0 x 0.03978^2]

[IDF 2009]

“32 nm”/56.25nm h-p, 0.171 um2 [= 54.0 x 0.05625^2]

[IDF 2009]

< 201360f2 area

@2yrM1 cycle

0.5x/2yrs =-29%

CAGR

[4 plus Resistor Load]



1000.0

10000.0

100000.0

1000000.0

2010 2015 2020 2025 2030

4T NAND gate density(K/mm2)

4T NAND gate density(K/mm2)< 2013

2x/2yrs =41%

CAGR

> 20172x/3yrs =

26% CAGR

Near Term2013-2020

Long Term2021-2028

ITRS Flash Poly H-pitch 45 38 20 14 10 8 8 8 8ITRS DRAM M1 H-pitch 45 32 22 16 11 8 5.5 4“Logic Node”: 45 32 22 14 10 7 5 3.5 2.5 1.8ITRS M1 H-pitch [2013 Proposal]: 76 54 38 27 19 13 10 6.7 4.7 3.3

28

Gate Density2011 and 2012 ITRS: Unchanged 2-year cycle through 2013


ITRS : < 2013

10x/7yrs ~2x/2yrs =

41% CAGR

Gate Density Historical PerspectiveIC Insights Historical Data: 1995-2010 on ~2-year cycle


0.0010

0.0100

0.1000

1.00002010 2015 2020 2025 2030

6T SRAM cell area(um2)

6T SRAM cell area(um2)

< 20130.5x/2yrs =

-29% CAGR

> 20170.5x/3yrs =

-21% CAGR

Near Term2013-2020

Long Term2021-2028

SRAM Cell Size2011 and 2012 ITRS: Unchanged 2-year cycle through 2013

30

ITRS Flash Poly H-pitch 45 38 20 14 10 8 8 8 8ITRS DRAM M1 H-pitch 45 32 22 16 11 8 5.5 4“Logic Node”: 45 32 22 14 10 7 5 3.5 2.5 1.8ITRS M1 H-pitch [2013 Proposal]: 76 54 38 27 19 13 10 6.7 4.7 3.3


31

0.1

1

10

1995 2000 2005 2010

Ce

ll A

rea

(u

m 2)

0.5x every 2 years

SRAM Cell Size Scaling

Transistor density continues to double every 2 years

45 nm, 0.346 um2 (193 nm dry)

32 nm, 0.171 um2 (193 nm immersion)

65 nm, 0.570 um2 (193 nm dry)

< 201360f2 area

@2yrM1 cycle

0.5x/2yrs =-29%

CAGR

SRAM Historical Perspective(Data: on ~2-year cycle)

[Source: VLSIR weSRCH Website]


32

Transistor Density and Performance

Drive currents continue to increase while gate pitch scales

100

1000

1995 2000 2005 2010

Gat

e P

itch

(nm

)

0.7x every 2 years

32nm

65nm

45nm

112.5 nm

PitchPitchPitch

1001000Gate Pitch (nm)

Driv

e C

urre

nt

(mA

/um

)0.0

0.5

1.0

1.5

2.0

1.0 V, 100 nA IOFF

45nm

32nm

65nm

90nm

NMOS

PMOS

130nm

Transistor and M1 Pitch Perspective vs. Drive Current/Performance(Data: on ~2-year cycle)

[Source: VLSIR weSRCH Website]


33

2012 ITRS Definition Work – Clarification of the M1 Half Pitch To clarify the ORTC Table 1 relationship to Gate Length*

And for consistency with Interconnect TWG Transistor M1 contacted half-pitch [and public - sometimes presented (IEDM, etc) as “Transistor Pitch” or “Gate Pitch”] ; *vs. Printed Gate Length (GLpr) (sometimes compared to “CD” or Critical

Dimension for manufacturing process control); and finally the publically-measurable Physical Gate Length, (GLph – see also the PIDS chapter)

[Note: The ITRS does not utilize any single-product “node” designation reference; Flash Poly and DRAM M1 half-pitch are still litho drivers; however, other product technology trends may be drivers on

individual TWG tables]

Contacted M1 Half-Pitch vs.

0.5 x “Transistor or Gate Pitch?”

[CD]

[GLph]

Contact

Width

Metal 1 Pitch [Interconnect TWG Example; 2011 graphic

= 2x M1 Half-Pitch]

Metal 1 half-pitch = 0.5 x M1 Pitch]

Other ITRS MPU Model Consideration:

[SRAM (6-transistor) Cell Area = 60f2

= 60 x (M1 h-p)^2]

Industry Example:“32 nm”/56.25nm h-p, 0.171 um2

[= 62.0 x 0.05625^2][IDF 2009]

GLph


2011 Interconnect TWG -Hierarchical Cross Sections

34

MPU Cross-Section

Dielectric Capping

LayerCopper

Conductor with

Barrier / Nucleation

Layer

Pre-Metal Dielectric

Tungsten Contact Plug

Inter-Mediate(=M1x1)

Metal 1

Passivation

DielectricEtch Stop

Layer

ASIC Cross-Section

Semi-Global (=M1x2)

Metal 1 Pitch

Via

Wire

Via

Wire

Via

Wire

Metal 1 Pitch

Global(=IMx1.5~2µm)

Inter-Mediate(=M1x1)Metal 1

Global(=IMx1.5~2µm)

1) MPU: Revised hierarchy2) ASIC: No drastic change, however semi-global should be kept at 2 x M1 3) Flash: The new technology driver for M1 also?

Flash Cross-Section

Metal 3

Metal 0Metal 1

Metal 2

Poly Pitch

Metal 1 Pitch


Overall Roadmap Technology Characteristics (ORTC) 2012 1 Alan Allan Winter Hsinchu Public Conference...

Documents

Transcript of Overall Roadmap Technology Characteristics (ORTC) 2012 1 Alan Allan Winter Hsinchu Public Conference...