Outline - Indian Institute of Technology Guwahati · Modelling: level of detail • Behavioral...
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9/4/2018 1 Lect 17 Hardware Programming (Verilog HDL) CS221: Digital Design Dr. A. Sahu Dept of Comp. Sc. & Engg. Indian Institute of Technology Guwahati 9/4/2018 Outline • FPGA/ASIC Design Flow • HDL Programming : Verilog HDL • HDL Rules HDLM d l dE l • HDL Module andExamples • HDL levels : Data flow, Structural and Behavioral, UDP • Testing and Simulation 9/4/2018 FPGA ‐ Field Programmable Gate Array •Programmable logic blocks or CLB (Logic Element “LE”) Implement combinatorial and sequential logic. Based on LUT and DFF. 9/4/2018 FPGA ‐ Field Programmable Gate Array Logic block Logic block Interconnection switches Interconnection switches I/O I/O I/O I/O 9/4/2018 IC Design Process Design Fabrica‐ tion Testing Packaging Idea Idea Layout Die Tested Die Specification Implementation Model Synthesis Verification & Simulation 9/4/2018 Hardware/Software Design Flow HW Specification Synthesis SW Specification Compilation Layout IC Fabrication Binary Code 9/4/2018
Transcript of Outline - Indian Institute of Technology Guwahati · Modelling: level of detail • Behavioral...
9/4/2018
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Lect 17
Hardware Programming (Verilog HDL)
CS221: Digital Design
Dr. A. SahuDept of Comp. Sc. & Engg.
Indian Institute of Technology Guwahati9/4/2018
Outline• FPGA/ASIC Design Flow • HDL Programming : Verilog HDL• HDL RulesHDL M d l d E l• HDL Module and Examples
• HDL levels : Data flow, Structural and Behavioral, UDP
• Testing and Simulation
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FPGA ‐ Field Programmable Gate Array•Programmable logic blocks or CLB
(Logic Element “LE”)Implement combinatorial and sequential logic. Based on LUT and DFF.
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FPGA ‐ Field Programmable Gate ArrayLogic blockLogic block Interconnection switchesInterconnection switches
I/OI/O
I/O
I/OI/O
I/O
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IC Design Process
DesignFabrica‐tion Testing Packaging
IdeaIdea Layout Die Tested Die
SpecificationImplementationModelSynthesisVerification & Simulation
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Hardware/Software Design Flow
HWSpecification
Synthesis
SWSpecification
Compilation
Layout
IC
y
Fabrication
Binary Code
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Model
• Representation of abstract view of the System
• Varying abstractionsf ti l l– functional only
– timing only– functional + timing
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Hardware Specification• Layout editor
– directly enter layout– Up to ~102 of unique transistors– Complex circuits– Memory, aided by generators
a• Schematic Capture– Enter gates and interconnections– Up to ~104 transistors
• Hardware Description Languages– Enter text description– 107 transistors
ab
F
module ..If (x < y) then Y=x and z;….9/4/2018
Hardware Specification
a
ComplexityMaintainability and Modifiability
Optimal Efficiency
bF
Entity ..If (x < y) then Y=x and z;….
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Modelling: level of detail• Behavioral Level
– no clock cycle level commitment• Register‐Transfer Level (RTL)
– Operations committed to clock cycles
for (i=0;i <4;i++)S = S+ A[i]
• Gate level– structural netlist
Cycle 1: T1 = A[0] + A[1]T2 = A[2] + A[3]
Cycle 2: S = T1 + T2
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Synthesis
• HDL → Layout– HDL → Gates– Gates → Layout
module ..If (x < y) then Y=x and z;….
HWSpecification
Layout
Synthesis
ab
F
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Synthesis
• Behavioral Synthesis (Process & Sequential )–Behavioral HDL → RTL HDLN ti f l k t Cl k d–No notion of clock to Clocked
• RTL Synthesis –RTL HDL → Gates
• Layout Synthesis–Gates → Layout
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Design Flow
Behavioral Model
RTL Model
for (i=0;i <4;i++)S = S+ A[i]
Cycle 1: T1 = A[0] + A[1]T2 = A[2] + A[3]
Cycle 2: S = T1 + T2
Behavioral Synthesis
RTL Synthesis
Gate Model
Optimal Gate Model
Layout
ab F
y
Logic Synthesis
Layout Synthesis
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FPGA Design flowSpecification
HDL Verilog, VHDL, SystemC
Simulation ModelSim/ISim
SynthesisConvert HDL tp FPGA Logic
Timing Constraints
Place and Route
Timing Analysis
Bit File Conf.ig Gen
FPGA Configuration
Timing Simulation If Needed
ConstraintsTiming
ConstraintsPin‐out
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VerilogHDL
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What is Verilog
• Hardware Description Language (HDL)• Developed in 1984• Standard: IEEE 1364, Dec 1995
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Application Areas of Verilog
System Specification
HW/SW PartitionHardware Softwre
Suitable for all levelsBehavioral levelNot suitable
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Hardware Spec
Softwre Spec
ASIC
FPGA
PLD
Std Parts
Boards&
Systems
Software
HDL, Area of Application
• Design Entry• Logic Simulation• Functional Verification
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• Digital Circuit Synthesis• Timing Verification• Fault Simulation• Documntation
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Description of digital systems only
Basic Limitation of Verilog
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Abstraction Levels in Verilog
Behavioral
RTL Our focus
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RTL
Gate
Layout (VLSI)
Our focus
Main Language Concepts (i)
• Concurrency AB
CD
Z
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• Structure
D
U1 U2
U3
AB
Cin
Sum
Carry
Main Language Concepts (ii)
• Procedural Statements
• Time
ExcutionFlow
Selection of Code
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Lets Start with an Example of
Verilog HDL moduleVerilog HDL module
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Module
in1
in2
out1
out2
my_module
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f
inN outM
Everything you write in Verilog must be inside a moduleexception: compiler directives
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Modulemodule my_module(out1, .., inN);
output out1, .., outM;
input in1, .., inN;
// declarations
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.. // declarations
.. // description of f (maybe
.. // sequential)
endmodule
Everything you write in Verilog must be inside a moduleexception: compiler directives
Example: Half Adder(Data Flow Model: using Boolean Equations)
module half_adder(S,C,A,B);output S, C;input A, B;
wire S, C, A, B;
A
BS
C
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assign S = A ^ B;assign C = A & B;
endmoduleHalfAdder
A
B
S
C
Example: Half Adder(Data Flow Model: using Boolean Equations)
module half_adder(S,C,A,B);output S, C;input A, B;
wire S, C, A, B;
A
BS
C
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assign S = A ^ B;assign C = A & B;
endmodule
assign S = A ^ B;assign C = A & B;
assign C = A & B;assign S = A ^ B;Same
Example: Half Adder, 2nd Implementation Using Structural/gate
primitive inter connection
module half_adder(S,C,A,B);output S, C;input A, B;
A
B
S
C
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wire S, C, A, B;
xor (S, A, B);and (C, A, B);
endmodule
C
Example: Half Adder, 2nd Implementation Using Structural/gate
primitive inter connection module half_adder(S,C,A,B);output S, C;input A, B;
wire S, C, A, B;
A
B
S
C
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, , , ;
xor (S, A, B);and (C, A, B);
endmodule
C
xor (S, A, B);and (C, A, B);
and (C, A, B);xor (S, A, B);Same
Verilog HDL Languages
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User Identifiers• Formed from {[A‐Z], [a‐z], [0‐9], _, $}• Can’t begin with $ or [0‐9]
– myidentifier
– m y identifier
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m_y_identifier
– 3my_identifier
– $my_identifier
– _myidentifier$
• Case sensitivity : myid ≠ Myid
Comments : same as C++ Style• // The rest of the line is a comment
• /* Multiple linecomment */
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• /* Nesting /* comments */ do NOT work */
Verilog Value Set
• 0 represents low logic level or false condition
• 1 represents high logic level or true condition
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• x represents unknown logic level
• z represents high impedance logic level == > open circuit
Truth Tables (Updated..)AND 0 1 X Z
0 0 0 0 01 0 1 X XX 0 x x XZ
OR 0 1 X Z
0 0 1 X X1 1 1 1 1X X 1 X X
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Z 0 x x x Z X 1 X X
XOR 0 1 X Z
0 0 1 X X1 1 0 X XX X x x XZ x x x x
NOT 0 1 X Z
OUT 1 0 X X
Sorry: There were two mistakes in this Slide, now corrected
