Outline

MISTRAL & ASTRAL SensorsReadout & Testability

From FSBB 0 (Full Scale Building Bloc) toward FSP (Full Scale Prototype)

Christine Hu-Guo - Gilles CLAUS (on behalf of PICSEL and ALICE teams of IPHC-Strasbourg)

IPHC [email protected] 2 / 17ALICE ITS upgrade - Mini week 10-12 March 2014

FSBB 0 (Full Scale Building Bloc Version 0)

Main characteristics Testability Readout

FSP (Full Scale Prototype) : MISTRAL & ASTRAL

Main characteristics Testability Readout

Outline

EUDET Beam Telescope

FSBB (Full Scale Building Bloc)

FSP (Full Scale Prototype)

FSBB 0

13,7

mm

9,2 mm

16,9

mm

12-1

3 m

m

15 m

m

FSBB FSBB FSBB

30 mm


MISTRAL

Pixel + Amplifier + CDS (Correlqted Double Sampling)

Analogic Digital conversion Discriminators One discriminator at end of each column

Data compression logic SUZE 02

Data transmission Serialiser

ASTRAL

Improvement of Upstream part One discriminator per pixel

Same downstream part

MISTRAL – ASTRAL : Simplified Bloc Diagram

IPHC [email protected] 15IEEE-NSS 2013

Upstream Downstream

²

Amp cDS ADC SUZE Data trans

Steering, Slow control, Bias DAC

Pixel 1Pixel 2

Pixel N


FSBB 0 (Full Scale Building Bloc Version 0)

Two versions : FSBB MISTRAL & FSBB ASTRAL

Matrix 9,2 x 13,7 mm² - 416 x 416 pixels – Pixels 22 x 33 µm²

CMOS-Opto 0,18 µm process Tower Jazz

3 x FSBB Submitted in February 2014

FSP (Full Scale Prototype) : MISTRAL & ASTRAL

Based on a building block : FSP = 3 x FSBB

Matrix : 30 x 12-13 µm² ~ 1248 columns x 416 rows

MISTRAL : Matrix 30 x ~ 13 mm² - 22 x 33 µm² One discriminator per column T r.o ~ 35 µs - P ~ 200 mW/cm²

ASTRAL Matrix 30 x ~ 12 mm² - 24 x 31 µm² One discriminator per pixel T r.o <= 20 µs - P ~ 85 mW/cm²

Submission plans for end of 2014

From FSBB toward FSP


FSBB (Full Scale Building Bloc)

FSP (Full Scale Prototype)

FSBB 0

13,7

mm

9,2 mm

16,9

mm

12-1

3 m

m

15 m

m

FSBB FSBB FSBB

30 mm


FSBB 0 : Full Scale Building Block (Version 0)EUDET Beam Telescope


Full Scale Building Block (FSBB 0): MISTRAL & ASTRAL Two versions : MISTRAL & ASTRAL

Three FSBB 0 submitted in One single chip Chip ~ Equivalent size as FSP (Full Scale Prototype) Two MISTRAL (M0a, M0b) One ASTRAL (A0)

MISTRAL T r.o 41,6 µs - ASTRAL T r.o 20,8 µs

Chip organisation 3 Sensors in one chip Each sensor has its own steering & readout – Common power bus for MISTRAL A & B 3 Matrix 9,2 x 13,7 mm² - 416 x 416 pixels – Pixels 22 x 33 µm²

Steering: Reset + FSBB Configuration (operating mode, bias, … ) by JTAG slow control Input clock @ 160 MHz Start signal (to synchronize the readout of multiple FSBB)

Readout: Normal operation mode (After zero suppression) 4 Wires link @ DDR 640 Mb/s Test modes (Analogue & Digital) to characterize pixels, discriminators

Digital : 4 Wires protocol Analogue : 16 Analogue outputs

13,7

mm

9,2 mm

16,9

mm

27,6 mm

Mistral A

AstralMistral B


Steering & readout signals

Full Scale Building Block (FSBB 0): MISTRAL & ASTRAL

9,2 mm

TDO

JTAG (CMOS)

13,7

mmPixel Array

SUZEJTAG Readout ControlSerial OutputTest PADS

TDI

TMS

TCK

RST

Star

t

CK (1

60 M

Hz)

Data out (LVDS)

MK_

DCL

K_D

D0 D1

(LVDS)

Steering 5 CMOS + 2 LVDS JTAG 5 CMOS lines

RST, TMS, TCK : Common all sensors TDI, TDO : Daisy chained

Clock in (160 MHz) 1 LVDS Start in 1 LVDS

Readout (640 Mb/s) 4 LVDS MK_D (Synchro) 1 LVDS CLK_D (160 MHz) 1 LVDS Data D0, D1 DDR 320 Mb/s 2 LVDS

Testability Test points : 11 Analogues + 2 Digital CMOS MISTRAL

4 VRef discri + 3 VTests discri 4 bias 2 digital (CMOS) Spy internal signals

ASTRAL 3 VRef discri 2 Bias 2 digital (CMOS) Spy internal signals


Testability implemented on FSBB :

Sensors configuration and status JTAG slow control (5 wires link)

Digital pads interconnection testing JTAG boundary scan

Pixel characterization at analogue level Analogue outputs of 8 columns Fe55, Calibration peak, CCE, Noise

All discriminators characterization Discri input = On-chip analogue signal Scurve : Noise, Pedestal

All Pixel + discriminators characterization Scurve : Noise, Pedestal + Fake hits rate

Data transmission & SUZE02 logic test Pixels patterns emulation by JTAG

Sensor temperature Read as analogue (2 pads)

Spy internal digital & analogue signals 2 LVDS test pads + n Analogues test pads


Full Scale Building Block (FSBB 0): MISTRAL & ASTRAL


FSBB 0 Normal Readout & Data stream Readout configuration:

Double Data Rate (DDR) @ 160 MHz 320 Mbit/s Two options

Full memory : Two data link DDR @ 160 MHz 640 Mbit/s Half memory : One data link DDR @ 160 MHz 320 Mbit/s

Data stream organization Data generated on both edges (DDR) of FSBB output clock Synchronization signal MKD Data LSB first Data stream is organized in 30 bits words multiplexed over the two links First bit of frame = LSB of Header (30 bits)

0 3 91 2 4 865 7 10 1311 12 14

CLKDT

DO0 Header 0 & Header 1b0

4.TMKD

DO1 b0

Header 0 & Header 1

One link @ 320 Mbit/s Two links @ 320 Mbit/s

3 91 2 4 865 7 10 1311 12 14

CLKDT

DO0 Header 0b0

8.TMKD

Header 1b14 b29


FSBB 0 Data stream : Service & Data fields Data words: 30 bits W30 (30 bits words)

Mono output:

Dual output:

Data generated on both edges (DDR) of FSBB output clock @ 160 MHz (Bit time slot = 3,125 ns)

Service fields Total 4 W30 / output

Header 1 W30 / output (Header 0 + Header 1) Trigger 1 W30 / output Frame counter, data length 1 W30 / output Trailer 1 W30 / output (Trailer 0 + Trailer 1)

Data fields ( format on next slide )

MISTRAL Maximum = 416 x W30 / output ASTRAL Maximum = 208 x W30 / output

Total data stream size per output

MISTRAL Max 13 312 bits / Output / 41,6 µs Total (2 outputs) 76 MB/s ASTRAL Max 6 656 bits / Output / 20,8 µs Total (2 outputs) 76 MB/s

n = data length x 4 + rem

trailerHeader Frame ct & data length Trigger DATA0 DATAn-1Do0

n = data length x 4 + rem

trailerHeader

Frame ct & data length

Trigger DATA0

DATAn-1

Do0

Header DATA1

DATAn-2

trailerDo1


FSBB 0 Data stream : Data fields format

The useful data is the daisy chain of "status" and "hit-windows"

Status: "FSBB user manual" for details One status field per super line Indicates row address + the number of Hit-Windows

Hit-windows: "FSBB user manual" for details Up to 9 hit-windows / ½ line Indicates : column address + Hit map + Window offset in super Line

2 1 022 2129

Column address(8 bits)

code (20 bits) Delta2 bits

…………………….. ………………………………………………………………………...

3

7

11

15

2

6

1014

1

59

13

04

8

12

19 18 17 16

code

Column Address

MSB LSBstate

3210

416 224 223 0

3210

Super Line X

Super Line X-1

State 0State 1

…Delta (2bits) State 0State 1 …

G1 G0

3

7

11

15

2

6

1014

1

59

13

04

8

12

19 18 17 16

code

Column Address

MSB LSB

state


Full Scale Prototype : MISTRAL & ASTRALEUDET Beam Telescope


Full Scale Prototype : MISTRAL & ASTRAL Sensor organisation:

Composed of 3 x FSBB (Full Scale Building Block

Two versions MISTAL = Mature architecture (STAR)

End of column discriminator T r.o ~ 35 µs, Power ~ 200 mW/cm²

ASTRAL = Innovative architecture In-pixel discriminator T r.o < 20 µs, Power ~ 85 mW/cm²

Steering: Reset + FSBB Configuration (operating mode, bias, … ) by JTAG slow control Input clock 160 MHz or 40 MHz with on-chip PLL implemented Start signal (to synchronize the readout of multiple FSBB)

Readout:

Normal operation mode (After zero suppression) One wire link 8B/10B @ 2 Gb/s Test modes (Analogue & Digital) to characterize pixels, discriminators

Digital : One wire link Analogue To be define

12-1

3 m

m

15 m

m

FSBB FSBB FSBB

30 mm


Steering 5 CMOS + 2 LVDS / Ladder

JTAG 5 CMOS lines / ladder RST, TMS, TCK : Common all sensors TDI, TDO : Daisy chained

Clock in 1 LVDS / ladder

Start in 1 LVDS / ladder (Optional ? )

Readout 1 LVDS / Sensor Data out 8B/10B 1 LVDS / sensor

Clock embeded in data stream

Testability 0 Pads / Ladder

No pads required on the ladder

Pads required for probe testing Nb ? 2 LVDS outputs 4 pads N Analogue outputs N pads 1 Input to characterization ADC 1 pad n Analogue internal references n

Full Scale Prototype : MISTRAL & ASTRAL Steering & readout signals

30 mm

13 m

mPixel Array Pixel Array Pixel Array

SUZE SUZE SUZEJTAG Readout Controller PLLSerial OutputTest PADS

TDO

TDI

TMS

TCK

RST

Star

t

CK (4

0 M

Hz)

Input clock 40 MHzVia on-chip PLL

Only one output8B/10B Protocol

@ ~ 2 Gb/s

JTAG (CMOS)

CK (1

60 M

Hz)

Data out (LVDS)

(LVDS)

(LVDS)


Full Scale Prototype : Serial output 8B/10B FSBB

One link / sensor 4 LVDS pairs / link

Pixel ArrayFSBB M0a

SUZE

MEMORY

SERIALISER

Data out FSBB M0 A640 Mb/s /

13 m

m

30 mm

Pixel ArrayFSBB M0b

Pixel ArrayFSBB A0

SUZE SUZE

MEMORY

SERIALISER

MEMORY

SERIALISER

MK_

DCL

K_D

D0 D1

Data out FSBB M0 B640 Mb/s

MK_

DCL

K_D

D0 D1

Data out FSBB A0640 Mb/s

MK_

DCL

K_D

D0 D1

3 x // Bus 120 bits @ 5,5 MHz

30 mm

13 m

m

Pixel ArrayFSBB

Pixel ArrayFSBB

Pixel ArrayFSBB

SUZE SUZE SUZE

MEMORY MEMORY

SERIALISER8B/10B Encoding

(INFN Torino)

MEMORY BUFFER ? + MANAGMENT

MEMORY

Worst case Data out 3 x 640 Mb/s ~ 1,9 Gb/s

3 x // Bus 120 bits @ 5,5 MHz

Single outputClock emdeded in data stream8B/10B Protocol

FSS Three sensors mutiplexed on one link 1 LVDS pairs / link (8B/10B protocol)

Safety factor of ~ 2 Can reduce output data rate 2 Gb/s 1 Gb/s


Full Scale Prototype : MISTRAL & ASTRAL Testability Green = OK / Orange = To Do / Wish list

Sensors configuration and status JTAG slow control (5 wires link)

Digital pads interconnection testing JTAG boundary scan

Pixel characterization at analogue level Fe55, Calibration peak, CCE, Noise Easy to implement on MISTRAL Study needed on ASTRAL

All discriminators characterization S curves : Noise, Pedestal

All Pixels + discriminators characterization Scurve : Noise, Pedestal + Fake hits rate

Data transmission & SUZE02 logic test Hard coded pixels patterns emulation

Sensor temperature Read as analogue (2 pads) & By JTAG

Power supply measurement & bias Internal ADC read by JTAG

Spy internal digital & analogue signals 2 LVDS test pads + n Analogues test pads



Summary

FSBB 0

Submitted in February 2014 Detailed documentation for ~ 1 April 2014 FSBB User manual Should be back from foundry ~ end of May 2014

Next steps

First Tests & Characterization results (at laboratory) expected for end of June Define testability to be implemented in Final Sensor Prototype (FSP) FSBB 0 beam test in October 2014 (Using FSBB Telescope) FSP submission at the end of 2014


Backup


Full Scale Sensors (FSS): JTAG Slow control

JTAG via PC // Port

Slow Control ( JTAG ) – Mimosa 26 configuration

TCK frequency Using PC // port Few 100 Khz Mimosa / FSBB limits 10 – 20 MHz

Run on STAR Experiment @ 1,5 MHz

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